CN108400166B - 在端子降低表面电场区域中具有端子沟槽的功率晶体管 - Google Patents
在端子降低表面电场区域中具有端子沟槽的功率晶体管 Download PDFInfo
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Abstract
一种装置(100)包含形成于衬底(302)上的晶体管。所述晶体管包含n型漏极接触层(312)、n型漏极层(314)、氧化物层(332)、p型主体区域(324)、p型端子区域(322)、主体沟槽(110)及端子沟槽(122)。所述n型漏极接触层在所述衬底的底部表面(306)附近。所述n型漏极层定位于所述n型漏极接触层上。所述氧化物层外接晶体管区域(102)。所述p型主体区域定位于所述晶体管区域内。所述p型端子区域从所述氧化物层下方延伸到所述晶体管区域的边缘,借此与所述p型主体区域形成连续的结。所述主体沟槽在所述晶体管区域内且与所述p型主体区域交插,然而所述端子沟槽在所述晶体管区域外侧且与所述p型端子区域交插。
Description
技术领域
背景技术
具有高电压能力的电路具有广泛工业应用,所述工业应用包含供在汽车中使用的功率管理系统。这些电路包含以高电压范围(例如,高于100V)操作的功率晶体管(例如,高电压晶体管)且还可包含以低得多的电压范围(例如,1v到5V)操作的低电压晶体管。为保护低电压晶体管免受高电压操作影响,功率晶体管可采用一或多个隔离方案。举例来说,一个隔离方案涉及在功率晶体管周围形成隔离结构。所述隔离结构可在环绕功率晶体管的晶体管区域的外围区域中包含一或多个端子沟槽。在高电压操作期间,外围区域与晶体管区域之间的结V可经历升高的电场强度,借此导致击穿电压的减少。且在某些情形中,经减少击穿电压可导致从晶体管区域的低电平电流泄漏。
发明内容
本发明描述与制造可处置高电压操作(例如,高于500V)的半导体装置有关的系统及技术。所述半导体装置可为独立离散组件或作为集成电路的一部分而并入。所述半导体装置采用隔离方案来保护低电压晶体管免受高电压操作影响。所揭示隔离方案允许高电压晶体管以高电压范围操作同时减少晶体管区域与环绕且隔离所述晶体管区域的端子区域之间的电压应力。有利地,所揭示隔离方案提供低成本且高性能解决方案以减轻所述半导体装置的结击穿及电流泄漏。
附图说明
图1展示根据本发明的方面的晶体管装置的局部俯视图。
图2A展示根据本发明的方面的晶体管装置的隅角区域的局部俯视图。
图2B展示根据本发明的另一方面的晶体管装置的隅角区域的局部俯视图。
图3展示根据本发明的方面的晶体管装置的外围区域与晶体管区域之间的结的横截面视图。
图4A到4C展示根据本发明的方面的用于制造晶体管装置的方法的流程图。
图5A到5K展示根据本发明的方面的在制造工艺期间的晶体管装置的横截面视图。
在各图式中,相似参考符号指示相似元件。在附图及下文描述中陈述本发明的一或多个实施方案的细节。各图未按比例绘制且其仅为了图解说明本发明而提供。陈述特定细节、关系及方法以提供对本发明的理解。可从所述描述及图式且从权利要求书明了其它特征及优点。
具体实施方式
图1展示根据本发明的方面的晶体管装置100的局部俯视图。晶体管装置100可为在单个半导体裸片上制作的独立离散装置。或者,晶体管装置100可并入到在单个集成电路裸片上制作的一或多个电路。
晶体管装置100形成于衬底(例如,图3中的302)上,所述衬底具有界定晶体管区域102及外围区域104的顶部表面(例如,图3中的304)。一般来说,晶体管区域102 为功率晶体管的有源组件所定位的地方,然而外围区域104用作晶体管区域102的端子区域且提供与晶体管区域102的绝缘。在一个实施方案中,举例来说,外围区域104侧向环绕晶体管区域102。
晶体管装置100包含位于晶体管区域102内的一或多个晶体管主体沟槽(例如,第一沟槽)110。晶体管主体沟槽110可沿着顶部表面的纵向方向彼此平行而对准。晶体管装置100还包含位于外围区域104内的一或多个端子沟槽(例如,第二沟槽)120及130。一般来说,端子沟槽120及130侧向环绕晶体管区域102,且因此还侧向环绕晶体管主体沟槽110。更特定来说,纵向端子沟槽120在纵向方向上且因此平行于晶体管主体沟槽110而延伸。通过对比,横向端子沟槽130在横向方向上且因此垂直于晶体管主体沟槽110而延伸。
图2A展示根据本发明的方面的晶体管装置100的隅角区域(例如,顶部左隅角区域) 103的局部俯视图。在此配置中,端子沟槽120及130具有正交对准,此允许横向端子沟槽130沿着隅角区域103与纵向端子沟槽120交错。举例来说,横向端子沟槽132、 134、136及138与纵向端子沟槽122、124、126及128在不接触彼此的情况下以之字形次序布置。
由于端子沟槽120及130可填充有外延生长的材料,因此此正交交错图案可帮助减少与外延生长工艺相关联的堆垛层错。有利地,堆垛层错减少可帮助降低跨越晶体管区域102与外围区域104之间的隅角结(例如,隅角区域103)的电压平衡的灵敏度。通过增强对隅角结中的不平衡电荷共享的免疫力,正交交错图案还可改进晶体管装置100的击穿电压及电流泄漏。
当端子沟槽(例如,120及130)具有充分大的纵横比(例如,大于10:1的宽度与深度比)时,还可显著降低堆垛层错的风险。如此,端子沟槽可以跑道图案布置,如图2B中所展示。在此跑道图案中,举例来说,横向端子沟槽132、134、136及138在隅角区域 103周围连续地连接到纵向端子沟槽122、124、126及128。
为增强可靠性及性能,晶体管装置100在外围区域104与晶体管区域102之间包含具有降低表面电场(RESURF)能力的一或多个超级结结构。参考图3,举例来说,晶体管装置100的外围区域104与晶体管区域102之间的横截面结包含此类RESURF能力。与以上描述一致,晶体管装置100包含具有顶部表面304及底部表面306的半导体衬底302。衬底302可为其上发展有多个外延层的单个块状衬底或晶片。晶体管装置100为垂直装置,因为其漏极到源极电流路径从衬底302的底部表面304延伸到顶部表面306。
一般来说,晶体管装置100的漏极区域包含漏极接触层312、漏极漂移层314及任选地一或多个经轻掺杂漏极(LDD)区域316。在晶体管装置100为n沟道装置的情况下,漏极接触层312可为在底部表面306附近的n型层,且其可具有重n++掺杂(例如,1× 1019cm-3或更大)。类似地,漏极漂移层314可为定位在漏极接触层312上的n型层。漏极漂移层314具有低于漏极接触层312的掺杂浓度(例如,从1×1015cm-3到2×1016 cm-3)。在漏极接触层312形成于起始晶片上的情况下,漏极漂移层314可外延地生长于其上。或者,在漏极接触层312作为经掺杂区域形成于块状衬底上的情况下,漏极漂移层314也可作为经掺杂区域形成于漏极接触层312上面。LDD区域316中的每一者定位在漏极漂移层314的上部部分当中且在衬底302的顶部表面304附近。与漏极漂移层314 一样,LDD区域316中的每一者也是经n掺杂的,但具有比漏极漂移层314重的掺杂浓度Ldd掺杂(例如,从1×1016cm-3到1×1017cm-3)。
晶体管装置100包含与漏极漂移层314及任选地LDD区域316介接的一或多个主体区域324。在漏极区域为n型的情况下,主体区域324可为p型。主体区域324定位在晶体管区域102内且在漏极漂移层314的顶部部分附近。共同地,主体区域324可为邻接晶体管主体沟槽110的第一经p掺杂区域。如图3的实例性配置中所展示,晶体管主体沟槽112、114及116中的每一者与晶体管区域102内的主体区域324交插。
晶体管装置100包含通过主体区域324与漏极区域(例如,312、314及316)分开的一或多个源极区域318。在一个实施方案中,举例来说,源极区域318中的每一者可定位在主体区域324中的对应一者内且在衬底的顶部表面304附近。与漏极区域一样,源极区域318也是经n掺杂的,且其可具有高于定位在主体区域324外侧的LDD区域316 的掺杂浓度(例如,从1×1019cm-3到5×1019cm-3)。
晶体管装置100包含在漏极漂移层314上面的顶部表面304上的漏极电介质层332。漏极电介质层332可为外接晶体管区域102且划定外围区域104的边界的氧化物层。与对图1的描述一致,晶体管主体沟槽(例如,第一沟槽)110定位在晶体管区域102内,且其从顶部表面304延伸以部分地穿透经n掺杂漏极漂移层314。此外,端子沟槽(例如,第二沟槽)122定位在外围区域104内且与晶体管主体沟槽110共同延伸以部分地穿透经 n掺杂漏极漂移层314。端子沟槽120及130以及晶体管主体沟槽110中的每一者填充有导电材料以形成场板。在一个实施方案中,举例来说,导电材料可为经p掺杂外延层。如此,端子场板123定位在端子沟槽122内,且晶体管场板113、115及117分别定位在晶体管主体沟槽112、114及116内。
晶体管装置100包含定位在顶部表面304上面且在两个邻近晶体管主体沟槽(例如晶体管主体沟槽112及114)之间的一或多个栅极结构342。应力减轻层334经沉积以覆盖栅极结构342及漏极电介质层332。为了接达源极区域318及主体区域324,晶体管装置100包含在栅极结构342及应力减轻层334上面的源极金属层346。源极金属层346 穿透晶体管场板113、115及117的顶部部分,借此与源极区域318及主体区域324进行欧姆接触。晶体管装置100也可包含用于保护下伏结构的绝缘层336及338。
晶体管装置100包含用于减少在晶体管区域102与外围区域104之间的装置结(例如,如图2A及2B中所展示的隅角区域103)周围的表面场密度的构件。除如图2A中所描述的端子沟槽120及130的交错图案以外或作为所述交替图案的替代方案,晶体管装置100还可包含端子区域322以减轻装置结周围的表面场密度。一般来说,端子区域322 具有与主体区域324相同的导电类型,此导电类型与漏极区域312、314及316以及源极区域318相反。举例来说,端子区域322可为在第一经p掺杂区域(例如,主体区域 324)之前或之后形成的第二经p掺杂区域。在一个实施方案中,端子区域322可在晶体管装置100的一或多个隅角区域(例如隅角区域103)处的结周围形成。在另一实施方案中,端子区域322可经形成以侧向环绕晶体管区域102。
端子区域322邻近于顶部表面304且从漏极电介质层332下方延伸到晶体管区域102 的边缘。端子区域322与主体区域324形成连续的结,且因此端子区域322可邻接端子沟槽122及晶体管主体沟槽112两者。当端子区域322可延伸超过端子沟槽122从而远离晶体管区域102时,如图1及2A到2B中所展示的两个或多于两个端子沟槽120可与端子区域322交插。
虽然主体区域(例如,第一经p掺杂区域)324在由漏极电介质层332划定的边界周围终止,但端子区域(例如,第二经p掺杂区域)322延伸跨越所述边界。如此,端子区域322夹置在主体区域324与端子沟槽122之间。一般来说,端子区域322扩散到比主体区域324大的深度以用于减小晶体管装置100的表面场密度。在一个实施方案中,举例来说,端子区域322可具有介于从0.2um到3.0um的范围内的扩散深度d1,然而主体区域324可具有介于从0.3um到1um的范围内的扩散深度d2。此外,端子区域322 可具有低于主体区域324的掺杂浓度以减小晶体管装置100的表面场密度。在一个实施方案中,举例来说,端子区域322可具有介于从1×1016cm-3到3×1016cm-3的范围内的掺杂浓度,然而主体区域324可具有介于从1×1017cm-3到3×1017cm-3的范围内的掺杂浓度。
端子区域322用作增强对晶体管装置100的隅角区域(例如,隅角区域103)周围的不平衡电荷共享的免疫力的RESURF区域。有利地,端子区域322帮助在高电压操作期间增强pn结的击穿电压(例如,主体区域324到漏极漂移层314)且因此最小化泄漏电流。
尽管图3中的某些层及区域被指定具有特定导电类型(条件是晶体管装置100为n沟道装置),但在晶体管装置100为p沟道装置的情况下可指派相反导电类型给这些层及区域。举例来说,在其中晶体管装置100为p沟道装置的替代实施方案中,漏极区域312、 312及316为经p掺杂区域,主体区域324为经n掺杂区域,源极区域318为经p掺杂区域,且端子区域322为经n掺杂区域。
转向图4A到4B,本发明介绍用于制造与对图1、2A到2B及3的描述一致的晶体管装置100的方法400。方法400可在步骤410处开始且在步骤480处终止。步骤410 涉及提供经n掺杂衬底。如图5A中所展示,举例来说,半导体衬底302具备经n++掺杂层(即,经重掺杂n型层)312及经n掺杂层314。经n++掺杂层312可为具有介于从1 ×1019cm-3到5×1019cm-3的范围内的掺杂浓度的起始晶片。经n掺杂层314可借助于以磷、砷及/或锑掺杂剂进行外延生长而在经n++掺杂层312上发展。经n掺杂层314可具有介于从1×1015cm-3到2×1016cm-3的范围内的掺杂浓度。与对图1、2A到2B及3 的描述一致,衬底302具有顶部表面304及底部表面306,其中任一者可界定晶体管区域102及侧向环绕晶体管区域102的外围区域104。
在完成步骤410之后,方法400继续进行到步骤420,步骤420涉及在晶体管区域中形成第一深沟槽且在外围区域中形成第二深沟槽。如图5A中所展示,举例来说,在衬底302的顶部表面304上形成硬掩模510。硬掩模510可通过顶部表面304的氧化或通过将氧化硅沉积到顶部表面304上而形成。在硬掩模510上形成经图案化光致抗蚀剂层512。经图案化光致抗蚀剂层512界定用于形成外围区域104中的端子沟槽(即,第二深沟槽)120及130且用于形成晶体管区域102中的晶体管主体沟槽(即,第一深沟槽)110 的开口513。
在光刻工艺期间,蚀刻硬掩模510的由经图案化光致抗蚀剂层512暴露的若干部分。在所述蚀刻之后,形成经图案化硬掩模511。如图5B中所展示,移除经图案化光致抗蚀剂层512且清洁经图案化硬掩模511。接着,执行硅蚀刻以从由经图案化硬掩模511 的开口暴露的顶部表面304开始进行蚀刻。在硅蚀刻之后,形成深沟槽阵列。如图5B 中所展示,举例来说,深沟槽阵列包含端子沟槽122(以及如图1中所展示的端子沟槽 120及130)及晶体管主体沟槽110(包含晶体管主体沟槽112、114及116)。这些深沟槽(例如,122、112、114及116)中的每一者具有从顶部表面304延伸以穿透经n掺杂层314 的一部分的沟槽深度dT。在一个实施方案中,沟槽深度dT可介于从25um到100um的范围内。
在完成步骤420之后,方法400继续进行到步骤430,步骤430涉及在第一深沟槽及第二深沟槽中形成经p掺杂场板。如图5C中所展示,举例来说,执行选择性外延工艺以填充深沟槽122、112、114及116。选择性外延工艺将原位掺杂有p型掺杂剂(例如,硼)的硅施加到顶部表面304,后续接着高温(例如,1050℃到1200℃)氢(H2)及/或氮(N2) 退火工艺。因此,分别在沟槽122、112、114及116中形成经p掺杂场板123、113、115 及117,且在经图案化硬掩模511上面形成p型外延层514。在一个实施方案中,可在形成经p掺杂场板123、113、115及117之前在沟槽122、112、114及116中形成沟槽衬里。所述沟槽衬里可包含SiO2。
在选择性外延之后,执行化学机械抛光(CMP)工艺以移除p型外延层514及经图案化硬掩模511。如图5D中所展示,举例来说,在CMP工艺之后顶部表面304没有经图案化硬掩模511及p型外延层514。如此,经p掺杂场板123、113、115及117各自具有与衬底302的顶部表面304平准的顶部表面。
在完成步骤430之后,方法400继续进行到步骤440,步骤440涉及跨越晶体管区域及外围区域形成第一经p掺杂区域。第一经p掺杂区域邻接在第二深沟槽中且在第一深沟槽中的至少一者中的经p掺杂场板。根据本发明的方面,可由如图4B中所概述的工艺流程实施步骤440,所述工艺流程可在步骤442处开始且在步骤446处终止。
步骤442涉及形成仅暴露外围区域及晶体管区域的紧邻于外围区域的一部分的第一掩模。如图5E中所展示,举例来说,在晶体管区域102内形成第一掩模522。第一掩模 522可包含通过热氧化工艺形成的丝网氧化物层。第一掩模522从晶体管区域102与外围区域104之间的结后退凹陷距离dR。在一个实施方案中,凹陷距离dR可介于从3um 到6um的范围内。在另一实施方案中,凹陷距离dR可由晶体管主体沟槽112的位置界定,晶体管主体沟槽112为最接近于结的晶体管主体沟槽110。
步骤444涉及将第一p型掺杂剂植入到由第一掩模暴露的区域中。如图5E中所展示,使用一或多个第一p型掺杂剂执行各向同性植入520。举例来说,第一p型掺杂剂可包含硼。由于凹陷距离dR,因此各向同性植入520可到达晶体管区域102的外边缘,借此允许第一p型掺杂剂植入到外围区域104以及晶体管区域102的外边缘中。在执行各向同性植入520之后,剥离第一掩模522。
步骤446涉及扩散所植入第一p型掺杂剂以跨越晶体管区域及外围区域形成第一经 p掺杂区域。如图5E中所展示,举例来说,在执行活化退火工艺之后形成第一经p掺杂区域(即,经p掺杂端子区域)322。第一经p掺杂区域322在顶部表面304下方延伸且从外围区域104横跨晶体管区域102的外边缘。第一经p掺杂区域322用作用于降低晶体管装置100的在晶体管区域102与外围区域104之间的装置结周围的电荷灵敏度的端子RESURF区域。水平地,第一经p掺杂区域322夹置在至少一个端子沟槽(例如端子沟槽122)与至少一个晶体管主体沟槽(例如晶体管主体沟槽112)之间。垂直地,扩散工艺致使第一经p掺杂区域322具有介于从0.2um到3um的范围内的扩散深度d1。
再次参考图4A,其中方法400在完成步骤440之后继续进行到步骤450。步骤450 涉及在晶体管区域中在不延伸到外围区域的情况下形成第二经p掺杂区域。第二经p掺杂区域邻接仅定位在第一深沟槽中的经p掺杂场板。根据本发明的方面,可由如图4C 中所概述的工艺流程来实施步骤450,所述工艺流程可在步骤451处开始且在步骤455 处终止。
步骤451涉及形成覆盖外围区域且暴露晶体管区域的电介质层。如图5F中所展示,举例来说,沿着外围区域104在顶部表面304上形成电介质层332。电介质层332用作用于使下伏经n掺杂层(即,漏极漂移层)314绝缘的绝缘构件。在晶体管区域102与外围区域104之间的结周围终止,电介质层332外接且暴露晶体管区域102。
电介质层332可包含通过正硅酸乙酯(TEOS)的经图案化沉积形成的氧化物层。在一个实施方案中,TEOS的经图案化沉积包含:将TEOS材料沉积到顶部表面304上以形成氧化硅层,后续接着在顶部表面304上形成光致抗蚀剂掩模,后续接着经缓冲氟氢酸 (BHF)蚀刻以暴露晶体管区域102,后续接着在顶部表面304处停止的氧化硅等离子体蚀刻。所述等离子体蚀刻移除在外围区域104外侧的氧化硅,借此留下在未经蚀刻光致抗蚀剂掩模下方的电介质层332。在执行等离子体蚀刻之后,可剥离未经蚀刻光致抗蚀剂掩模。
步骤452涉及在顶部表面上方在晶体管区域中的第一深沟槽之间形成栅极结构。如图5G中所展示,举例来说,在顶部表面306上面且在两个邻近晶体管主体沟槽110(例如晶体管主体沟槽112与114)之间形成一或多个栅极结构342。栅极结构342的形成可通过以下方式开始:执行热氧化以形成栅极电介质层341。接着,执行经原位掺杂多晶硅沉积以形成栅极结构342的多晶硅层。接下来,执行氟氢(HF)脱釉工艺以预清洁多晶硅层的表面。在HF脱釉工艺之后,执行钨硅(例如,WSix层,其中x介于从2um到2.5 um的范围内)的化学气相沉积(CVD)以在多晶硅层的经预清洁表面上形成钨硅层。
为图案化栅极结构342,在钨硅层上形成氧化硅硬掩模及经图案化光致抗蚀剂掩模,其中经图案化光致抗蚀剂硬掩模暴露不属于栅极结构342的区域。接着,执行硬掩模蚀刻,后续接着在栅极电介质层341处停止的钨硅蚀刻及多晶硅蚀刻。在图案化栅极结构 342之后,剥离经图案化光致抗蚀剂掩模。因此,每一栅极结构342包含在栅极电介质层341上的多晶硅层342a、在多晶硅层342a上的钨硅层342b及在钨硅层342b上的氧化物层342c。
步骤453涉及形成仅暴露晶体管区域的侧向环绕第一沟槽的一部分的第二掩模。如图5H中所展示,举例来说,第二掩模530暴露紧邻于晶体管主体沟槽110的区域。此外,电介质层332可用作在第二掩模530旁边的掩模。这是因为电介质层332在晶体管区域102与外围区域104之间的结周围终止。如此,电介质层332暴露晶体管区域102 以用于随后植入。
步骤454涉及将第二p型掺杂剂植入到由第二掩模暴露的区域中。如图5H中所展示,通过由第二掩模530及电介质层332界定的开口执行p型掺杂剂532的植入。p型掺杂剂可包含硼。在所述操作之后,移除第二掩模530同时电介质层332保持在顶部表面304上在外围区域104内。
步骤455涉及扩散所植入第二p型掺杂剂以在晶体管区域中在不延伸到外围区域的情况下形成第二经p掺杂区域。如图5H中所展示,在执行活化退火工艺之后形成第二经p掺杂区域(即,经p掺杂主体区域)324。第二经p掺杂区域324中的每一者在顶部表面304下方延伸。在外围区域104与晶体管区域102之间的装置结周围,最外部第二经p掺杂区域324形成与第一经p掺杂区域322连续的经p掺杂区域。所述连续经p掺杂区域横跨装置结且邻接端子沟槽122及晶体管主体沟槽112两者。水平地,第二经p 掺杂区域324中的每一者被晶体管主体沟槽110中的一者(例如晶体管主体沟槽112)夹置。垂直地,扩散工艺致使第二经p掺杂区域324中的每一者具有介于从0.10um到0.30 um的范围内的扩散深度d2。
再次参考图4A,其中方法400在完成步骤450之后继续进行到步骤460。步骤460 涉及在两个邻近栅极结构之间形成轻微地经n掺杂区域。如图5I中所展示,举例来说,执行n型掺杂剂540的植入。所述n型掺杂剂包含磷、砷及/或锑。在执行活化退火工艺之后形成轻微地经n掺杂区域(即,LDD区域)318中的每一者。轻微地经n掺杂区域316 中的每一者具有低于经n掺杂层314及经n++掺杂层312两者的掺杂浓度。在一个实施方案中,轻微地经n掺杂区域316中的每一者具有介于从1×1016cm-3到1×1017cm-3的范围内的掺杂浓度。水平地,轻微地经n掺杂区域316中的每一者横跨在两个邻近第二经p掺杂区域324之间。垂直地,扩散工艺致使轻微地经n掺杂区域316从顶部表面 304延伸到比第二经p掺杂区域324的扩散深度d2小的浅深度。
在完成步骤460之后,方法400继续进行到步骤470,步骤470涉及在第二经p掺杂区域内且紧邻于第一深沟槽形成经n掺杂区域。如图5J中所展示,举例来说,形成光致抗蚀剂掩模550以界定暴露紧邻于晶体管主体沟槽110的区域的开口。此外,光致抗蚀剂掩模550覆盖外围区域104与晶体管区域102之间的结。如此,光致抗蚀剂掩模 550延伸超过电介质层332以覆盖晶体管主体沟槽112的一部分。接下来,通过由光致抗蚀剂掩模550界定的开口执行n型掺杂剂552的植入。n型掺杂剂可包含砷、磷及/ 或锑。在所述操作之后,移除光致抗蚀剂掩模550且执行退火工艺。所述退火工艺扩散所植入n型掺杂剂以形成经n掺杂区域(即,经n掺杂源极区域)318。经n掺杂区域318 中的每一者在顶部表面304下方延伸。水平地及垂直地,经n掺杂区域318中的每一者横跨在第二经p掺杂区域324内。
在完成步骤470之后,方法400继续进行到步骤480,步骤480涉及形成与栅极结构绝缘且耦合到第一深沟槽中的经p掺杂场板的导电层。如图5K中所展示,应力减轻层334可通过TEOS沉积而形成。而且,应力减轻层334还用作栅极结构342的绝缘层。接着执行经图案化硅蚀刻及经图案化氧化硅蚀刻以移除晶体管主体沟槽110中的每一者的上部部分。可将势垒层344沉积到应力减轻层334以及晶体管主体沟槽110中的每一者的经蚀刻上部部分上。在一个实施方案中,势垒层344可包含氮化钛层及钛层。接下来,将导电层346沉积到势垒层344上。
导电层346与栅极结构342绝缘,同时与经n掺杂区域318、第二经p掺杂区域324 及晶体管经p掺杂场板113、115及117进行欧姆接触。导电层346可用作源极接触金属层,且其可包含铝层。在形成导电层346之后,可沉积第一绝缘层336及第二绝缘层 338以覆盖应力减轻层334及导电层346。在一个实施方案中,第一绝缘层336及第二绝缘层338可覆盖在外围区域104上面的应力减轻层334及导电层346。在另一实施方案中,第一绝缘层336及第二绝缘层338可暴露在晶体管区域102上面的导电层346。第一绝缘层336可包含磷硅酸盐玻璃层,且第二绝缘层338可包含氮化硅层。
与本发明一致,术语“经配置以”打算描述一或多个有形非暂时性组件的结构及功能特性。举例来说,术语“经配置以”可被理解为具有经设计或专用于执行某种功能的特定配置。在此理解内,如果装置包含可经启用、经激活或经供电以执行某种功能的有形非暂时性组件,那么此装置“经配置以”执行所述某种功能。虽然术语“经配置以”可囊括可配置的概念,但此术语不应限于此狭隘定义。因此,当用于描述装置时,术语“经配置以”不需要所描述装置在任何给定时间点为可配置的。
此外,术语“示范性”在本文中用于意指用作实例、例子、图解说明等,且未必为有利的。而且,尽管已关于一或多个实施方案展示及描述本发明,但在阅读并理解此说明书及附图之后将明了等效变更及修改。本发明包括所有此类修改及变更且仅受所附权利要求书的范围限制。尤其关于由上文所描述的组件(例如,元件、资源等)执行的各种功能,用于描述此类组件的术语打算对应于(除非另有指示)执行所描述组件的规定功能的任何组件(例如,为功能上等效的),即使并非结构上等效于所揭示结构。另外,虽然可已关于数个实施方案中的仅一者揭示了本发明的特定特征,但此特征可与其它实施方案的一或多个其它特征组合,如对于任何给定或特定应用可能为合意的及有利的。
虽然此说明书含有许多特定细节,但这些特定细节不应解释为对可主张的内容的范围的限制,而是应解释为对可为特定实施例特有的特征的描述。在单独实施例的上下文中于本说明书中描述的某些特征还可以组合方式实施于单个实施例中。相反地,在单个实施例的上下文中描述的各种特征还可单独地或以任何适合子组合方式实施于多个实施例中。此外,尽管上文可将特征描述为以某些组合起作用且甚至最初如此主张,但来自所主张组合的一或多个特征在一些情形中可从所述组合去除,且所述所主张组合可针对于子组合或子组合的变化形式。
类似地,虽然在图式中以特定次序描绘操作,但不应将此理解为需要以所展示的特定次序或按顺序次序执行此类操作,或执行所有所图解说明的操作以实现合意结果,除非在一或多个权利要求中陈述此次序。在某些情况中,多任务及并行处理可为有利的。此外,上文所描述的实施例中的各种系统组件的分开不应被理解为在所有实施例中需要此分开。
Claims (20)
1.一种半导体装置,其包括:
半导体衬底,其具有顶表面和底表面,所述顶表面包括第一区域及侧向环绕所述第一区域的第二区域;
经掺杂层,其在所述顶表面与所述底表面之间,所述经掺杂层具有第一导电类型;
第一沟槽,其在所述第一区域内,所述第一沟槽从所述顶表面延伸且部分地穿透所述经掺杂层;
第二沟槽,其在所述第二区域内,所述第二沟槽从所述表面延伸且部分地穿透所述经掺杂层;
第一经掺杂区域,其邻近于所述顶表面、在所述经掺杂层上面且介接所述第一沟槽,所述第一经掺杂区域具有第二导电类型;及
第二经掺杂区域,其邻近于所述顶表面、在所述经掺杂层上面且介接所述第一沟槽及所述第二沟槽,所述第二经掺杂区域具有所述第二导电类型。
2.根据权利要求1所述的半导体装置,其中:
所述第一经掺杂区域具有从所述顶表面延伸的第一深度;且
所述第二经掺杂区域具有从所述顶表面延伸且大于所述第一深度的第二深度。
3.根据权利要求1所述的半导体装置,其中:
所述第一经掺杂区域具有第一掺杂浓度;且
所述第二经掺杂区域具有低于所述第一掺杂浓度的第二掺杂浓度。
4.根据权利要求1所述的半导体装置,其中所述第二经掺杂区域夹置在所述第一经掺杂区域与所述第二沟槽之间。
5.根据权利要求1所述的半导体装置,其中所述第二经掺杂区域侧向环绕所述第一区域。
6.根据权利要求1所述的半导体装置,其中所述第二经掺杂区域侧向环绕所述第二沟槽。
7.根据权利要求1所述的半导体装置,其进一步包括:
第三经掺杂区域,其定位在所述第一经掺杂区域内且介接所述第一沟槽,所述第三经掺杂区域具有所述第一导电类型。
8.根据权利要求1所述的半导体装置,其进一步包括:
第四经掺杂区域,其在所述第一经掺杂区域及所述第二区域外侧,所述第四经掺杂区域定位在所述顶表面下面且在所述经掺杂层上面,所述第四经掺杂区域具有所述第一导电类型。
9.根据权利要求1所述的半导体装置,其进一步包括:
氧化物层,其在所述第二沟槽上面且划定所述第二区域的边界,其中所述第一经掺杂区域在所述边界周围终止且所述第二经掺杂区域延伸跨越所述边界。
10.根据权利要求1所述的半导体装置,其中所述第二沟槽包含:
纵向沟槽,其平行于所述第一沟槽;及
横向沟槽,其垂直于所述第一沟槽,所述横向沟槽与所述纵向沟槽分开,且所述横向沟槽沿着所述第二区域的隅角与所述纵向沟槽交错。
11.一种晶体管,其包括:
漏极接触层,其具有第一导电类型;
漏极层,其在所述漏极接触层上,并具有所述第一导电类型;
氧化物层,其在所述漏极层上面且外接第一区域;
主体区域,其在所述第一区域内且接近所述漏极层的顶部部分,所述主体区域具有第二导电类型;
端子区域,其具有所述第二导电类型,从所述氧化物层下方朝向所述漏极层水平地延伸到所述第一区域的边缘,且与所述主体区域形成连续的结;
主体沟槽,其在所述第一区域内且与所述主体区域交插;及
端子沟槽,其在所述第一区域外侧且与所述端子区域交插。
12.根据权利要求11所述的晶体管,其中:
所述主体区域具有从所述顶部部分延伸的第一深度;且
所述端子区域具有从所述顶部部分延伸且大于所述第一深度的第二深度。
13.根据权利要求11所述的晶体管,其中:
所述主体区域具有第一掺杂浓度;且
所述端子区域具有低于所述第一掺杂浓度的第二掺杂浓度。
14.根据权利要求11所述的晶体管,其进一步包括:
源极区域,其定位在所述主体区域内且接达所述主体沟槽,所述源极区域具有所述第一导电类型。
15.根据权利要求11所述的晶体管,其进一步包括:
经轻掺杂漏极LDD区域,其在所述主体区域外侧且夹置在所述主体沟槽中的两个主体沟槽之间,所述LDD区域具有所述第一导电类型。
16.根据权利要求11所述的晶体管,其中所述端子沟槽包含:
纵向沟槽,其平行于所述主体沟槽;及
横向沟槽,其垂直于所述主体沟槽,所述横向沟槽与所述纵向沟槽隔离,且所述横向沟槽与所述纵向沟槽一起布置成交错图案从而包围所述第一区域的隅角。
17.一种集成电路,其包括:
漏极接触层,其具有第一导电类型;
漏极层,其在所述漏极接触层上,且具有所述第一导电类型;
氧化物层,其在所述漏极层上面且外接第一区域;及
晶体管,其各自包含:
主体区域,其在所述第一区域中的至少一者内且在所述漏极层的顶部部分附近,所述主体区域具有第二导电类型;
端子区域,其具有所述第二导电类型,从所述氧化物层下方朝向所述漏极层水平地延伸到所述第一区域中的至少一者的边缘,且与所述主体区域形成连续的结;
主体沟槽,其在所述第一区域中的至少一者内且与所述主体区域交插;及
端子沟槽,其在所述第一区域中的至少一者外侧且与所述端子区域交插。
18.根据权利要求17所述的集成电路,其中:
所述主体区域具有从所述顶部部分延伸的第一深度;且
所述端子区域具有从所述顶部部分延伸且大于所述第一深度的第二深度。
19.根据权利要求17所述的集成电路,其中:
所述主体区域具有第一掺杂浓度;且
所述端子区域具有低于所述第一掺杂浓度的第二掺杂浓度。
20.根据权利要求17所述的集成电路,其中所述端子沟槽包含:
纵向沟槽,其平行于所述主体沟槽;及
横向沟槽,其垂直于所述主体沟槽,所述横向沟槽与所述纵向沟槽隔离,且所述横向沟槽与所述纵向沟槽一起布置成交错图案从而包围所述第一区域中的每一者的隅角。
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