JP7293293B2 - 高電圧隔離のためのデュアルディープトレンチ - Google Patents
高電圧隔離のためのデュアルディープトレンチ Download PDFInfo
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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Description
Claims (18)
- 集積回路であって、
頂部表面と底部表面とを有する基板と、
前記基板内に位置する埋め込み層と、
前記埋め込み層より上に位置するトランジスタウェル領域と、
前記埋め込み層を貫通するように前記頂部表面から延在する第1のトレンチであって、第1のトレンチ深さと前記頂部表面において画定される第1の開口とを有し、第1の導体を含む、前記第1のトレンチと、
前記埋め込み層を貫通するように前記頂部表面から延在する第2のトレンチであって、前記第1のトレンチと前記トランジスタウェル領域との間に置かれ、前記第1のトレンチ深さより浅い第2のトレンチ深さと前記頂部表面において画定される第2の開口とを有し、第2の導体を含み、前記第2の開口が前記第1の開口よりも小さい、前記第2のトレンチと、
を含む、集積回路。 - 請求項1に記載の集積回路であって、
前記第1の導体が、前記埋め込み層から絶縁されて前記第1のトレンチの底部辺りで前記基板とオーミック接触し、
前記第2の導体が、前記埋め込み層と前記基板とから絶縁される、集積回路。 - 請求項1に記載の集積回路であって、
前記第2のトレンチが、前記第2の導体を浮遊状態に絶縁する誘電体ライナーを更に含む、集積回路。 - 請求項1に記載の集積回路であって、
前記第2の導体が、前記埋め込み層と前記基板との間の接合の降伏電圧に関連するバイアス電圧を受け取るように構成される、集積回路。 - 請求項1に記載の集積回路であって、
前記第2の導体が、前記埋め込み層と前記基板との間の接合の電界密度閾値に関連するバイアス電圧を受け取るように構成される、集積回路。 - 請求項1に記載の集積回路であって、
前記第1のトレンチが、前記埋め込み層と前記基板との間の接合の降伏電圧に関連する距離で前記第2のトレンチから離間される、集積回路。 - 請求項1に記載の集積回路であって、
前記第1のトレンチが、埋め込み層と前記基板との間の接合の電界密度閾値に関連する距離で前記第2のトレンチから離間される、集積回路。 - 請求項1に記載の集積回路であって、
前記第1のトレンチが、1μmより大きい距離で前記第2のトレンチから離間される、集積回路。 - 請求項1に記載の集積回路であって、
前記トランジスタウェル領域の外につくられる高電圧回路と、
前記トランジスタウェル領域内につくられて前記第1のトレンチ及び前記第2のトレンチによって前記高電圧回路から遮蔽される低電圧回路と、
を更に含む、集積回路。 - 方法であって、
基板内に埋め込み層を形成することと、
前記埋め込み層より上にトランジスタウェル領域を形成することと、
前記埋め込み層を貫通するように前記基板の頂部表面から延在する第1のトレンチを形成することであって、前記第1のトレンチが第1のトレンチ深さと前記頂部表面において画定される第1の開口とを有する、前記第1のトレンチを形成することと、
前記第1のトレンチ内に第1の導体を形成することと、
前記埋め込み層を貫通するように前記基板の前記頂部表面から延在する第2のトレンチを形成することであって、前記第2のトレンチが前記第1のトレンチと前記トランジスタウェル領域との間に置かれ、前記第2のトレンチが前記第1のトレンチ深さより浅い第2のトレンチ深さと前記頂部表面において画定される第2の開口とを有し、前記第2の開口が前記第1の開口よりも小さい、前記第2のトレンチを形成することと、
前記第2のトレンチ内に第2の導体を形成することと、
を含む、方法。 - 請求項10に記載の方法であって、
前記第1の導体が、前記埋め込み層から絶縁されて前記第1のトレンチの底部辺りで前記基板とオーミック接触し、
前記第2の導体が、前記埋め込み層と前記基板とから絶縁される、方法。 - 請求項10に記載の方法であって、
前記第2の導体を浮遊状態に絶縁することを更に含む、方法。 - 請求項10に記載の方法であって、
前記埋め込み層と前記基板との間の接合の降伏電圧に関連するバイアス電圧を受けるための前記第2の導体とのコンタクトを形成することを更に含む、方法。 - 請求項10に記載の方法であって、
前記第1のトレンチが、前記埋め込み層と前記基板との間の接合の降伏電圧に関連する距離で前記第2のトレンチから離間される、方法。 - 請求項10に記載の方法であって、
前記第1のトレンチが、前記埋め込み層と前記基板との間の接合の電界密度閾値に関連する距離で前記第2のトレンチから離間される、方法。 - 請求項10に記載の方法であって、
前記第1のトレンチが、1.5μmより大きい距離で前記第2のトレンチから離間される、方法。 - 請求項10に記載の方法であって、
前記第1のトレンチを前記形成することが、前記第1の開口を介して所定の時間期間の間に前記基板の頂部層と前記埋め込み層と前記基板の底部層とをエッチングすることを含み、
前記第2のトレンチを前記形成することが、前記第2の開口を介して前記所定の時間期間の間に前記基板の前記頂部層と前記埋め込み層と前記基板の前記底部層とをエッチングすることを含む、方法。 - 請求項17に記載の方法であって、
高電圧回路を前記トランジスタウェル領域の外に形成することと、
前記第1のトレンチと前記第2のトレンチとによって前記高電圧回路から遮蔽される低電圧回路を前記トランジスタウェル領域内に形成することと、
を更に含む、方法。
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US15/238,198 US9786665B1 (en) | 2016-08-16 | 2016-08-16 | Dual deep trenches for high voltage isolation |
US15/238,198 | 2016-08-16 | ||
JP2019509513A JP6936454B2 (ja) | 2016-08-16 | 2017-08-16 | 高電圧隔離のためのデュアルディープトレンチ |
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JP2019509513A Division JP6936454B2 (ja) | 2016-08-16 | 2017-08-16 | 高電圧隔離のためのデュアルディープトレンチ |
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US9786665B1 (en) * | 2016-08-16 | 2017-10-10 | Texas Instruments Incorporated | Dual deep trenches for high voltage isolation |
US10262997B2 (en) * | 2017-09-14 | 2019-04-16 | Vanguard International Semiconductor Corporation | High-voltage LDMOSFET devices having polysilicon trench-type guard rings |
CN111341847B (zh) * | 2018-12-19 | 2023-03-28 | 联华电子股份有限公司 | 半导体结构及其制作方法 |
US10811543B2 (en) | 2018-12-26 | 2020-10-20 | Texas Instruments Incorporated | Semiconductor device with deep trench isolation and trench capacitor |
US11158750B2 (en) | 2019-07-03 | 2021-10-26 | Texas Instruments Incorporated | Superlattice photo detector |
WO2022153693A1 (ja) * | 2021-01-15 | 2022-07-21 | ローム株式会社 | 半導体装置 |
JP2023032332A (ja) * | 2021-08-26 | 2023-03-09 | ローム株式会社 | 半導体装置 |
US20230261062A1 (en) * | 2022-02-15 | 2023-08-17 | Globalfoundries U.S. Inc. | Isolation regions for charge collection and removal |
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US20180053765A1 (en) | 2018-02-22 |
JP2021184491A (ja) | 2021-12-02 |
CN109564895A (zh) | 2019-04-02 |
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US9786665B1 (en) | 2017-10-10 |
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EP3501040B1 (en) | 2022-04-27 |
WO2018035229A3 (en) | 2018-04-05 |
CN109564895B (zh) | 2023-08-11 |
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