JP6936454B2 - 高電圧隔離のためのデュアルディープトレンチ - Google Patents
高電圧隔離のためのデュアルディープトレンチ Download PDFInfo
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- 238000002955 isolation Methods 0.000 title description 6
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- 238000005530 etching Methods 0.000 claims description 28
- 230000015556 catabolic process Effects 0.000 claims description 13
- 238000009271 trench method Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 101
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
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- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Description
Claims (23)
- 集積回路であって、
頂部表面と底部表面とを有する基板と、
前記基板内に位置する埋め込み層と、
前記埋め込み層の上に位置するトランジスタウェル領域と、
前記埋め込み層を貫通するように前記頂部表面から延在する第1のトレンチであって、第1のトレンチ深さを有する、前記第1のトレンチと、
前記埋め込み層を貫通するように前記頂部表面から延在する第2のトレンチであって、前記第1のトレンチと前記トランジスタウェル領域との間に置かれ、前記第1のトレンチ深さより浅い第2のトレンチ深さを有する、前記第2のトレンチと、
を含み、
前記第1のトレンチが、前記埋め込み層から絶縁されて前記第1のトレンチの底部辺りで前記基板とオーミック接触する第1の導体を含み、前記第2のトレンチが、前記埋め込み層と前記基板とから絶縁される第2の導体を含む、集積回路。 - 請求項1に記載の集積回路であって、
前記第2のトレンチが、前記第2の導体を浮遊状態に絶縁する誘電体ライナーを更に含む、集積回路。 - 請求項1に記載の集積回路であって、
前記第2の導体が、前記埋め込み層と前記基板との間の接合の降伏電圧に関連するバイアス電圧を受け取るように構成される、集積回路。 - 請求項1に記載の集積回路であって、
前記第2の導体が、前記埋め込み層と前記基板との間の接合の電界密度閾値に関連するバイアス電圧を受け取るように構成される、集積回路。 - 請求項1に記載の集積回路であって、
前記第1のトレンチが、前記埋め込み層と前記基板との間の接合の降伏電圧に関連する距離だけ前記第2のトレンチから離間される、集積回路。 - 請求項1に記載の集積回路であって、
前記第1のトレンチが、埋め込み層と前記基板との間の接合の電界密度閾値に関連する距離だけ前記第2のトレンチから離間される、集積回路。 - 請求項1に記載の集積回路であって、
前記第1のトレンチが、1μmより大きい距離だけ前記第2のトレンチから離間される、集積回路。 - 請求項1に記載の集積回路であって、
前記第1のトレンチが、前記頂部表面において画定される第1の開口を有し、前記第2のトレンチが、前記頂部表面において画定される前記第1の開口より小さい第2の開口を有する、集積回路。 - 請求項1に記載の集積回路であって、
前記トランジスタウェル領域の外につくられる高電圧回路と、
前記トランジスタウェル領域内につくられ、前記第1のトレンチと前記第2のトレンチとによって前記高電圧回路から遮蔽される低電圧回路と、
を更に含む、集積回路。 - 集積回路であって、
第1の導電型と頂部表面と底部表面とを有する基板と、
前記第1の導電型とは反対の第2の導電型を有し、前記基板内に位置する埋め込み層と、
前記埋め込み層の上に位置するトランジスタウェル領域と、
前記埋め込み層を貫通するように前記頂部表面から延在する第1のトレンチであって、前記第1のトレンチが、第1のトレンチ深さと第1の導体とを有し、前記第1の導体が、前記埋め込み層から絶縁され、前記第1のトレンチの底部辺りで前記基板とオーミック接触する、前記第1のトレンチと、
前記埋め込み層を貫通するように前記頂部表面から延在する第2のトレンチであって、前記第2のトレンチが、前記第1のトレンチと前記トランジスタウェル領域との間に置かれ、前記第1のトレンチ深さより浅い第2のトレンチ深さと第2の導体とを有し、前記第2の導体が、前記埋め込み層と前記基板とから絶縁される、前記第2のトレンチと、
を含む、集積回路。 - 請求項10に記載の集積回路であって、
前記第2の導体が浮遊状態に絶縁される、集積回路。 - 請求項10に記載の集積回路であって、
前記第2の導体が、前記埋め込み層と前記基板との間の接合の降伏電圧に関連するバイアス電圧を受け取るように構成される、集積回路。 - 請求項10に記載の集積回路であって、
前記第2の導体が、前記埋め込み層と前記基板との間の接合の電界密度閾値に関連するバイアス電圧を受け取るように構成される、集積回路。 - 請求項10に記載の集積回路であって、
前記第1のトレンチが、前記埋め込み層と前記基板との間の接合の降伏電圧に関連する距離だけ前記第2のトレンチから離間される、集積回路。 - 請求項10に記載の集積回路であって、
前記第1のトレンチが、埋め込み層と前記基板との間の接合の電界密度閾値に関連する距離だけ前記第2のトレンチから離間される、集積回路。 - 方法であって、
基板内に埋め込み層を形成することと、
前記埋め込み層の上にトランジスタウェル領域を形成することと、
前記埋め込み層を貫通するように前記基板の頂部表面から延在する第1のトレンチを形成することであって、前記第1のトレンチが第1のトレンチ深さを有する、前記第1のトレンチを形成することと、
前記埋め込み層を貫通するように前記基板の前記頂部表面から延在する第2のトレンチを形成することであって、前記第2のトレンチが、前記第1のトレンチと前記トランジスタウェル領域との間に置かれ、前記第1のトレンチ深さより浅い第2のトレンチ深さを有する、前記第2のトレンチを形成することと、
前記第1のトレンチ内に第1の導体を形成することであって、前記第1の導体が、前記埋め込み層から絶縁され、前記第1のトレンチの底部辺りで前記基板とオーミック接触する、前記第1の導体を形成することと、
前記第2のトレンチ内に第2の導体を形成することであって、第2の導体が、前記埋め込み層と前記基板とから絶縁される、前記第2の導体を形成することと、
を含む、方法。 - 請求項16に記載の方法であって、
前記第2の導体を浮遊状態に絶縁することを更に含む、方法。 - 請求項16に記載の方法であって、
前記埋め込み層と前記基板との間の接合の降伏電圧に関連するバイアス電圧を受けるための前記第2の導体とのコンタクトを形成することを更に含む、方法。 - 請求項16に記載の方法であって、
前記第1のトレンチが、前記埋め込み層と前記基板との間の接合の降伏電圧に関連する距離だけ前記第2のトレンチから離間される、方法。 - 請求項16に記載の方法であって、
前記第1のトレンチが、前記埋め込み層と前記基板との間の接合の電界密度閾値に関連する距離だけ前記第2のトレンチから離間される、方法。 - 請求項16に記載の方法であって、
前記第1のトレンチが、1.5μmより大きい距離だけ前記第2のトレンチから離間される、方法。 - 請求項16に記載の方法であって、
前記第1のトレンチを形成することが、
前記基板の前記頂部表面において第1の開口を画定することと、
前記第1の開口を介して所定の時間期間の間、前記基板の頂部層と前記埋め込み層と前記基板の底部層とをエッチングすることと、
を含み、
前記第2のトレンチを形成することが、
前記基板の前記頂部表面において前記第1の開口より小さい第2の開口を画定することと、
前記第2の開口を介して前記所定の時間期間の間、前記基板の前記頂部層と前記埋め込み層と前記基板の前記底部層とをエッチングすることと、
を含む、方法。 - 請求項16に記載の集積回路であって、
前記トランジスタウェル領域の外に高電圧回路を形成することと、
前記トランジスタウェル領域内に、前記第1のトレンチと前記第2のトレンチとによって前記高電圧回路から遮蔽される低電圧回路を形成することと、
を更に含む、方法。
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