TWI503984B - 積體電路裝置及其製造方法 - Google Patents
積體電路裝置及其製造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title description 29
- 239000003989 dielectric material Substances 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 38
- 230000005669 field effect Effects 0.000 description 32
- 239000000463 material Substances 0.000 description 24
- 239000000758 substrate Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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Description
本發明係有關於一種積體電路裝置及其製造方法,特別係有關於一種鰭式金氧半導體場效電晶體裝置及其製造方法。
半導體裝置可應用於大量的電子裝置,例如電腦、手機或其他的電子裝置。可藉由於半導體晶片上方沉積多種類型的材料薄膜,且圖案化上述材料薄膜以形成積體電路的方式,於半導體晶片上形成包括積體電路的半導體裝置。積體電路係包括例如金氧半導體(MOS)電晶體的場效電晶體(FETs)。
半導體工業的一個目標為持續微縮各別場效電晶體的尺寸和增加各別場效電晶體的速度。鰭式場效電晶體不僅可以提升元件的面積密度,而且可以改善通道的閘極控制。
鰭式場效電晶體的導通電阻(on-resistance)會被數個因子限制。舉例來說,這些因子包括通道密度和漂移區的摻質濃度。
有鑑於此,本發明揭露之一實施例係提供一種積體電路裝置。上述積體電路裝置包括一墊層,其具有一第一摻
雜類型的一主體部分,上述主體部分橫向鄰接於一第二摻雜類型一漂移區部分;一溝槽,形成於上述墊層中,上述溝槽係延伸穿過上述主體部分和上述漂移區部分之間的一介面;一閘極,形成於上述溝槽中,且位於上述墊層的一頂面上方,上述閘極沿著位於上述主體部分和上述漂移區部分之間的上述介面延伸;一介電材料,形成於上述溝槽中,且位於上述閘極的複數個相對側上;以及一場板,嵌入於位於上述閘極的上述些相對側的其中之一個上的上述介電材料中。
本發明揭露之另一實施例係提供一種積體電路裝置。上述積體電路裝置包括一基板;一墊層,藉由上述基板支撐,上述墊層具有一第一摻雜類型的一主體部分,上述主體部分橫向鄰接於一第二摻雜類型一漂移區部分;一溝槽,形成於上述墊層中,上述溝槽係延伸穿過上述主體部分和上述漂移區部分之間的一介面;一閘極,形成於上述溝槽中,且位於上述墊層的一頂面上方,上述閘極沿著位於上述主體部分和上述漂移區部分之間的上述介面延伸;一介電材料,形成於上述溝槽中,且位於上述閘極的複數個相對側上;以及一場板材料,嵌入於上述介電材料中,且位於上述閘極的一源極和一汲極兩者上,位於上述閘極的上述汲極上的上述場板材料係做為一場板。
本發明揭露之又另一實施例係提供一種鰭式場效電晶體裝置的製造方法。上述方法包括於一墊層中形成一溝槽,上述墊層具有一第一摻雜類型的一主體部分,上述主體部分橫向鄰接於一第二摻雜類型一漂移區部分,上述溝槽係延伸
穿過上述主體部分和上述漂移區部分之間的一介面;於上述溝槽中且於上述墊層的一頂面上方形成一閘極,上述閘極沿著位於上述主體部分和上述漂移區部分之間的上述介面延伸;於上述溝槽中且於上述閘極的複數個相對側上形成一介電材料;以及於上述閘極的上述些相對側的其中之一個上的上述介電材料中嵌入一場板。
10‧‧‧鰭式場效電晶體裝置
12‧‧‧墊層
14‧‧‧溝槽
16‧‧‧閘極
18‧‧‧介電材料
20‧‧‧場板材料
21‧‧‧場板
22‧‧‧基板
24‧‧‧埋藏層
26‧‧‧主體部分
28‧‧‧漂移區部分
30‧‧‧介面
32‧‧‧頂面
34‧‧‧薄層
36‧‧‧溝槽底面
38‧‧‧溝槽側壁
40‧‧‧閘極側壁
42‧‧‧厚度
44‧‧‧p型重摻雜區
46‧‧‧n型重摻雜區
48‧‧‧源極
50‧‧‧汲極
52‧‧‧電流
第1圖為本發明一實施例之包括一溝槽場板的一鰭式場效電晶體裝置的剖面圖。
第2圖為沿第1圖A-A’切線的剖面圖。
第3圖為沿第1圖B-B’切線的剖面圖。
第4-9圖為如第1圖所示的本發明一實施例之包括一溝槽場板的一鰭式場效電晶體裝置的製造方法。
以下以各實施例詳細說明並伴隨著圖式說明之範例,做為本發明之參考依據。在圖式或說明書描述中,相似或相同之部分皆使用相同之圖號。且在圖式中,實施例之形狀或是厚度可擴大,並以簡化或是方便標示。再者,圖式中各元件之部分將以分別描述說明之,值得注意的是,圖中未繪示或描述之元件,為所屬技術領域中具有通常知識者所知的形式。
本發明以實施例揭露鰭式金氧半導體場效電晶體(FinFET MOS)。然而,也可包括其他積體電路和電子結構,但未限制於多重閘極場效電晶體(MuGFET)和奈米線裝置
(nanowise devices)。
請參考第1-3圖,係顯示本發明一實施例之一鰭式場效電晶體裝置10。會詳細說明於後,鰭式場效電晶體裝置10係提供較小的通道和漂移區電阻,和較小的裝置整體導通電阻(on-resistance)。另外,鰭式場效電晶體裝置10係使用較少光罩數目的簡易製程。如第1-3圖所示,鰭式場效電晶體裝置10通常包括一墊層12、一溝槽14、一閘極16、一介電材料18和一場板材料20,場板材料20係用來形成一場板(field plate)21。
如第1-3圖所示,墊層12被一基板22和一埋藏層24支撐。在本發明一實施例中,基板22可由一半導體材料形成,且埋藏層24可為一絕緣層、一p型埋藏層或其他適當的材料。在本發明一實施例中,墊層12可由n型半導體材料形成或摻雜n型摻質。墊層12通常分為p型摻雜的一主體部分26,上述主體部分26係橫向或垂直鄰接於n型摻雜的一漂移區部分28。在不同實施例中,可用其他的方式摻雜上述主體部分26和漂移區部分28以及鰭式場效電晶體裝置10的其他部分。
請再參考第1-3圖,溝槽14通常會形成於墊層12內。在本發明一實施例中,溝槽14係延伸穿過上述主體部分26和漂移區部分28之間的一介面30。換句話說,係部分形成於上述主體部分26和漂移區部分28兩者中。在本發明一實施例中,溝槽14的長軸,其於第1圖中為溝槽14的水平長度,係正交於上述主體部分26和漂移區部分28之間的介面30。在本發明一實施例中,可使用遮罩和乾蝕刻製程形成溝槽14。
在本發明一實施例中,一閘極16係形成於溝槽14
中,且位於墊層12的一頂面32上方,且上述閘極16沿著位於上述主體部分26和漂移區部分28之間的介面30延伸。在本發明一實施例中,溝槽14的長軸,其於第1圖中為溝槽14的水平長度,係正交於上述閘極16的長軸。在本發明一實施例中,可由多晶矽及/或其他適當閘極材料形成上述閘極16。如第1圖所示,上述閘極16的一垂直高度係大於溝槽14的一深度。因此,上述閘極16會突出於墊層12的頂面32上。藉由使用一三維(3D)閘極16(也稱為一摺疊閘極(folded gate)),可增加鰭式場效電晶體裝置10的通道密度,且可降低鰭式場效電晶體裝置10的通道電阻。
如第1-3圖所示,在本發明一實施例中,鄰接於上述閘極16之墊層12的主體部分26的一薄層34的n型摻質摻雜濃度大於n型摻雜的漂移區部分28的n型摻質摻雜濃度。上述主體部分26的n型重摻雜的薄層34通常設置接近於一溝槽底面36,且在溝槽側壁38背後,且接近於鄰接閘極16之墊層12的頂面32,如第2圖所示。在本發明一實施例中,可藉由摻雜製程形成薄層34。
請再參考第1-3圖,介電材料18係形成於位於閘極16相對側的溝槽14中。可藉由例如沉積或一熱氧化製程形成介電材料18。在本發明一實施例中,介電材料18包括一氧化層。在本發明一實施例中,如第2圖所示,介電材料18係形成於溝槽底面36、溝槽側壁38和閘極側壁40上。在本發明一實施例中,介電材料18的厚度42介於100Å和10μm之間。
如第1-2圖所示,一場板材料20係嵌入介電材料中
且位於閘極16的右手側(意即汲極側)以形成場板21。在本發明一實施例中,相同或相似的場板材料20也會嵌入介電材料18中且位於於閘極16的左手側。然而,閘極16的左手側沒有場板效應,因此,沒有場板21位於閘極16的左手側/源極側。在本發明一實施例中,場板材料20可包括多晶矽及/或具電導率(electrical conductivity)之其他適當材料。如圖所示,形成於溝槽14中的場板材料20,且位於閘極16兩側上的分開及各自獨立的部分。在本發明一實施例中,如第2圖所示,場板材料20的頂面和介電材料18的頂面共平面。藉由使用場板21,可於相同崩潰電壓下增加漂移區的摻質濃度,且可降低漂移區的電阻。藉由降低通道區和漂移區的電阻,可降低鰭式場效電晶體裝置10整體的導通電阻(on-resistance)。
請再參考第1-3圖,一p型重摻雜區44係形成於鰭式場效電晶體裝置10的一末端,而一n型重摻雜區46係形成於鰭式場效電晶體裝置10的另一末端。p型重摻雜區44可做為鰭式場效電晶體裝置10的一源極48的一部分。n型重摻雜區46可做為鰭式場效電晶體裝置10的一汲極50。
如第1-3圖所示,源極48、閘極16和場板21可使用相同的溝槽14形成。的確,溝槽14的尺寸和形狀係直接地影響源極48的尺寸和位置。另外,在本發明一實施例中,溝槽14通常容納場板材料20介電材料18和部分閘極16,或者,溝槽14通常被場板材料20、介電材料18和部分閘極16填充。
請參考第2-3圖,在本發明一實施例中,溝槽14係延伸至汲極50,以提供流經鰭式場效電晶體裝置10的均勻電流
52。另外,在本發明一實施例中,可藉由調整場板21的一長度及/或漂移區部分28的一長度來變更鰭式場效電晶體裝置10的崩潰電壓。
請參考第4-9圖,第4-9圖係顯示本發明一實施例之鰭式場效電晶體裝置10的製造方法。首先,請參考第4圖,於基板22和埋藏層24上方形成墊層12。之後,進行一第一遮罩製程,以定義主動區,其為如第4圖所示之墊層12的區域。換句話說,如第4圖所示區域以外的區域係被遮罩覆蓋。定義出主動區之後,氧化墊層12,且對墊層12的主體部分26進行一p型離子植入製程,以與n型摻雜的漂移區部分區分。在本發明一實施例中,可由一n型半導體材料形成墊層12。
接著,如第5圖所示,形成一溝槽14。在本發明一實施例中,可藉由一第二遮罩製程和一乾蝕刻製程形成溝槽14。然而,在不同實施例中可以其他的方式形成溝槽14。如第5圖所示,溝槽14係延伸穿過介面30,且延伸進入主體部分26和漂移區部分28。之後,如第6圖所示,進行一閘極氧化製程和一多晶矽沉積製程,以形成閘極16。可藉由一第三遮罩製程和一蝕刻製程定義閘極16的尺寸和維度。再者,可藉由一乾蝕刻製程或其他適當的蝕刻製程形成閘極16。
請參考第7圖,進行一第四遮罩製程,且對鄰接閘極16的墊層12的主體部分26進行n型離子植入製程,以形成n型重摻雜薄層34和n型重摻雜區46。然後,如第8圖所示,進行一氧化物沉積製程和一多晶矽沉積製程,以於結構上方依序全面性沉積一氧化物和一多晶矽(圖未顯示)。如第8圖所示,當沉積
氧化物和多晶矽之後,可進行一第五遮罩製程、一多晶矽蝕刻製程和一氧化物蝕刻製程以定義場板21,上述場板21係內嵌於介電材料18中。
如第9圖所示,可進行一第六遮罩製程和一p型離子植入製程,以於閘極16之與汲極50的相對側形成源極48。接著,可進行一第七遮罩製程和一金屬化製程。另外,可進行一第八遮罩製程和一保護層製程(圖未顯示),以完成鰭式場效電晶體裝置10。應該理解的是,也可使用其他常用的半導體製程或製造步驟,為了方便起見在此不再詳細描述,以一起形成或部分形成如第4-9圖所示的鰭式場效電晶體裝置10的製造方法的步驟。
從前述應該理解可鰭式場效電晶體裝置10係提供降低的通道電阻和漂移區電阻,且可降低裝置整體的導通電阻(on-resistance)。藉由使用相同的溝槽形成源極、汲極和閘極(也稱為一摺疊閘極)和場板的方式,以一簡單且具較少光罩數目的製程來形成鰭式場效電晶體裝置10。另外,可藉由調整場板及/或漂移區的長度,於相同矽基板上製造數個鰭式場效電晶體裝置10,且每一個鰭式場效電晶體裝置10係具有不同的崩潰電壓(breakdown voltage)。此外,可於相同矽基板上整合鰭式場效電晶體裝置10和其他裝置。
在本發明一實施例中,一積體電路裝置包括一墊層,其具有一第一摻雜類型的一主體部分,上述主體部分橫向鄰接於一第二摻雜類型一漂移區部分;一溝槽,形成於上述墊層中,上述溝槽係延伸穿過上述主體部分和上述漂移區部分之
間的一介面;一閘極,形成於上述溝槽中,且位於上述墊層的一頂面上方,上述閘極沿著位於上述主體部分和上述漂移區部分之間的上述介面延伸;一介電材料,形成於上述溝槽中,且位於上述閘極的複數個相對側上;以及一場板,嵌入於位於上述閘極的上述些相對側的其中之一個上的上述介電材料中。
在本發明一實施例中,一積體電路裝置包括一基板;一墊層,藉由上述基板支撐,上述墊層具有一第一摻雜類型的一主體部分,上述主體部分橫向鄰接於一第二摻雜類型一漂移區部分;一溝槽,形成於上述墊層中,上述溝槽係延伸穿過上述主體部分和上述漂移區部分之間的一介面;一閘極,形成於上述溝槽中,且位於上述墊層的一頂面上方,上述閘極沿著位於上述主體部分和上述漂移區部分之間的上述介面延伸;一介電材料,形成於上述溝槽中,且位於上述閘極的複數個相對側上;以及一場板材料,嵌入於上述介電材料中,且位於上述閘極的一源極和一汲極兩者上,位於上述閘極的上述汲極上的上述場板材料係做為一場板。
在本發明一實施例中,一鰭式場效電晶體裝置的製造方法包括於一墊層中形成一溝槽,上述墊層具有一第一摻雜類型的一主體部分,上述主體部分橫向鄰接於一第二摻雜類型一漂移區部分,上述溝槽係延伸穿過上述主體部分和上述漂移區部分之間的一介面;於上述溝槽中且於上述墊層的一頂面上方形成一閘極,上述閘極沿著位於上述主體部分和上述漂移區部分之間的上述介面延伸;於上述溝槽中且於上述閘極的複數個相對側上形成一介電材料;以及於上述閘極的上述些相對
側的其中之一個上的上述介電材料中嵌入一場板。
雖然本發明已以實施例揭露於上,然其並非用以限定本發明,任何熟習此項技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧鰭式場效電晶體裝置
12‧‧‧墊層
14‧‧‧溝槽
16‧‧‧閘極
18‧‧‧介電材料
20‧‧‧場板材料
21‧‧‧場板
22‧‧‧基板
24‧‧‧埋藏層
26‧‧‧主體部分
28‧‧‧漂移區部分
30‧‧‧介面
34‧‧‧薄層
44‧‧‧p型重摻雜區
46‧‧‧n型重摻雜區
48‧‧‧源極
50‧‧‧汲極
Claims (10)
- 一種積體電路裝置,包括:一墊層,其具有一第一摻雜類型的一主體部分,該主體部分橫向鄰接於一第二摻雜類型一漂移區部分;一溝槽,形成於該墊層中,該溝槽係延伸穿過該主體部分和該漂移區部分之間的一介面;一閘極,形成於該溝槽中,且位於該墊層的一頂面上方,該閘極覆蓋位於該主體部分和該漂移區部分之間的該介面;一介電材料,形成於該溝槽中,且位於該閘極的複數個相對側上;以及一場板,嵌入於位於該閘極的該些相對側的其中之一個上的該介電材料中。
- 如申請專利範圍第1項所述之積體電路裝置,更包括一源極,至少部分形成於接近該主體部分的該墊層的該溝槽內。
- 如申請專利範圍第1項所述之積體電路裝置,其中該溝槽的一長軸與該閘極的一長軸正交及與該主體部分和該漂移區部分之間的該介面正交。
- 如申請專利範圍第1項所述之積體電路裝置,其中形成於該溝槽中的該介電材料係設置於複數個溝槽側壁及至少一溝槽側壁和一溝槽底面上。
- 如申請專利範圍第1項所述之積體電路裝置,其中該溝槽的深度少於該閘極的一高度,且其中該場板和該介電材料的頂面為共平面。
- 如申請專利範圍第1項所述之積體電路裝置,其中於接近該主體部分的該墊層的該溝槽的一底面和側壁係摻雜該第二摻雜類型,且其摻雜濃度高於該漂移區部分的摻雜濃度。
- 如申請專利範圍第1項所述之積體電路裝置,其中位於該溝槽外的該墊層的該漂移區部分係定義為一漂移區。
- 一種積體電路裝置的製造方法,包括下列步驟:於一墊層中形成一溝槽,該墊層具有一第一摻雜類型的一主體部分,該主體部分橫向鄰接於一第二摻雜類型一漂移區部分,該溝槽係延伸穿過該主體部分和該漂移區部分之間的一介面;於該溝槽中且於該墊層的一頂面上方形成一閘極,該閘極覆蓋位於該主體部分和該漂移區部分之間的該介面;於該溝槽中且於該閘極的複數個相對側上形成一介電材料;以及於該閘極的該些相對側的其中之一個上的該介電材料中嵌入一場板。
- 如申請專利範圍第8項所述之積體電路裝置的製造方法,更包括使用該溝槽形成一源極。
- 如申請專利範圍第8項所述之積體電路裝置的製造方法,更包括該溝槽的一長軸定向以與該閘極的一長軸正交。
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Also Published As
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US20140015048A1 (en) | 2014-01-16 |
US20170301762A1 (en) | 2017-10-19 |
US10090390B2 (en) | 2018-10-02 |
US9698227B2 (en) | 2017-07-04 |
US20150118814A1 (en) | 2015-04-30 |
US8921934B2 (en) | 2014-12-30 |
TW201403825A (zh) | 2014-01-16 |
CN103545372B (zh) | 2016-05-04 |
CN103545372A (zh) | 2014-01-29 |
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