TWI556442B - 積體電路元件及其製造方法 - Google Patents

積體電路元件及其製造方法 Download PDF

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TWI556442B
TWI556442B TW102121291A TW102121291A TWI556442B TW I556442 B TWI556442 B TW I556442B TW 102121291 A TW102121291 A TW 102121291A TW 102121291 A TW102121291 A TW 102121291A TW I556442 B TWI556442 B TW I556442B
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source
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李後儒
賴高廷
丁國強
吳集錫
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台灣積體電路製造股份有限公司
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Description

積體電路元件及其製造方法
本發明係有關於一種電子元件及其製造方法，特別是有關於一種半導體元件及其製造方法。
半導體元件係廣泛的用於電子元件，例如電腦、手機和其它元件。半導體元件包括積體電路，其藉由以下製程形成：沉積許多型態的薄膜材料於半導體晶圓上；圖案化薄膜材料以形成積體電路。積體電路包括場效電晶體(FETs)，例如金氧半導體(MOS)電晶體。
半導體工業之目標之一是持續的微縮尺寸和增加場效電晶體之速度。為了達到上述目標，業界發展出鰭式場效電晶體(FinFET)和多閘極場效電晶體(multiple gate field-effect transistor，簡稱MuGFETs)。這些元件不僅改善面積密度，亦增加對於通道之閘極控制。
根據上述，本發明提供一種積體電路元件，包括：一鰭，具有一閘極區，閘極區位於一閘電極結構下；一源/汲極區，設置於超出鰭之末端的區域；及一第一保形層，圍繞源/汲極區之鑲嵌部分設置，其中第一保形層包括一垂直側壁，以平行閘極區之方位配置。
本發明提供一種積體電路元件，包括：一鰭，具 有一閘極區，閘極區係垂直地位於一閘電極結構下；一源/汲極區，形成於超出鰭和閘電極結構之末端的區域；及一第一保形層，圍繞源/汲極區之鑲嵌部分形成，其中第一保形層具有一包括外表面之垂直側壁，外表面平行閘極區之一垂直邊界線。
本發明提供一種積體電路元件之製造方法，包括：形成一凹槽，鄰近一鰭之一末端，其中鰭具有一閘極區，位於一閘電極結構下；形成一第一保形層於凹槽之暴露表面上方，其中第一保形層之垂直側壁平行閘極區；及形成一源/汲極區於凹槽中之第一保形層的內表面上方。
10‧‧‧鰭式場效電晶體元件
12‧‧‧基底
14‧‧‧鰭
16‧‧‧源極/汲極區
18‧‧‧摻雜半導體層
20‧‧‧閘電極結構
22‧‧‧間隙壁
24‧‧‧金屬接觸
26‧‧‧閘極區
28‧‧‧鰭式場效電晶體元件
30‧‧‧鰭
32‧‧‧閘電極結構
34‧‧‧源/汲極區
36‧‧‧第一保形層
38‧‧‧基底
40‧‧‧間隙壁
42‧‧‧金屬接觸
44‧‧‧閘極區
46‧‧‧凹槽
48‧‧‧垂直側壁
50‧‧‧底牆
52‧‧‧垂直邊界線
54‧‧‧外表面
56‧‧‧厚度
58‧‧‧距離
60‧‧‧厚度
62‧‧‧距離
64‧‧‧界面
66‧‧‧長度
68‧‧‧深度
70‧‧‧厚度
72‧‧‧第二保形層
74‧‧‧第三保形層
76‧‧‧方法
78‧‧‧方塊
80‧‧‧方塊
82‧‧‧方塊
第1圖顯示一傳統鰭式場效電晶體元件之代表部分的剖面圖。
第2圖顯示一實施例鰭式場效電晶體元件之代表部分的剖面圖，其中鰭式場效電晶體元件包括一保形層，具有一平行一鰭之閘極區的側壁。
第3圖顯示第2圖一範例鰭式場效電晶體元件之示意圖，其中第一保形層和閘極區分隔一固定距離。
第4圖顯示第2圖另一範例鰭式場效電晶體元件之示意圖，其具有各種其它尺寸和配置。
第5圖顯示一實施例鰭式場效電晶體元件之代表部分的剖面圖，其具有複數個保形層。
第6圖顯示一實施例鰭式場效電晶體元件之製造方法之流 程圖。
以下詳細討論實施本發明實施例之製作和使用。可以理解的是，實施例提供許多可應用的發明概念，其可以較廣的變化實施。所討論之特定實施例僅用來發明使用實施例的特定方法，而不用來限定發明的範疇。
以下段落將描述本發明實施例之鰭式金氧半導體場效電晶體，然而，所描述的技術亦可應用於其它積體電路和電子結構，包括但不限定於多閘極場效電晶體(MuGFET)元件。
第1圖顯示一傳統鰭式場效電晶體元件10之代表部分，其可以稱為V形三層矽鍺元件。以下將簡要的描述傳統鰭式場效電晶體元件10，以供作背景敘述。鰭式場效電晶體元件10包括一位於下方之基底12，支撐數個鰭14。鰭14一般延伸於源極/汲極區16間，而源極/汲極區16係鄰近於鰭14之相對兩側(如第1圖之箭號所示)。為容易描述，第1圖僅揭示單一源極/汲極區16。然而，需了解的是，源極鄰近鰭14之一末端，而汲極鄰近鰭14之另一末端。如第1圖所示，源極/汲極區16係以源極/汲極材料(例如硼或磷)形成，且鑲嵌於摻雜半導體層18中。
仍請參照第1圖，一位於間隙壁22間之閘電極結構20堆疊於鰭式場效電晶體元件10之鰭14上方。即使為容易描述而未揭示，第1圖之閘電極結構20可包括數個分隔的層或構件，例如高介電常數介電層、界面氧化層(interfacial oxide layer)、金屬閘極層和矽化物層。在一些情形中，一金屬接觸24可形成於相對之閘電極結構20間。
如第1圖所示，一閘極區26(亦即鰭閘極區)設置於各閘電極結構20下。在第1圖中，閘極區26係以虛線表示。根據第1圖，當從二維結構(亦即平面結構)轉變成三維結構(亦即鰭式場效電晶體、多閘極場效電晶體)，特別是包圍源極/汲極區16之半導體層18的輪廓傾向於穿過或沿著相鄰閘極區26變化。現已發現此會造成穿過閘極區26不同的電性和應變特性。因此，傳統的鰭式場效電晶體和多閘極場效電晶體變的更難控制，且元件和元件間有相當大的變化。
請參照第2圖，其揭示一實施例之鰭式場效電晶體元件28。在一實施例中，第2圖之鰭式場效電晶體元件28可以稱為H形三層矽鍺元件。鰭式場效電晶體元件28提供三維電晶體更均勻的閘極控制和應變，以下會更詳細的解釋。此外，鰭式場效電晶體元件28減輕或消除元件和元件間的變化。如第2圖所示，鰭式場效電晶體元件28包括一個或多個鰭30、一位於各鰭30上方之閘電極結構32、源/汲極區34和一第一保形(conformal)層36。
鰭式場效電晶體元件28之各個鰭30一般是以其下之基底38支撐，其中鰭30可以是半導體材料或其它適合之材料。如圖所示，各鰭一般位於一閘電極結構32下。換句話說，設置於相對之間隙壁40間之一閘電極結構32係堆疊於鰭式場效電晶體元件28之各鰭30上。雖然為容易描述，於圖式中未繪示，第2圖之閘電極結構32可包括數個分隔的層或構件，例如高介電常數介電層、界面氧化層(interfacial oxide layer)、金屬閘極層和矽化物層。在一些情形中，一金屬接觸42可形成於相 對之閘電極結構32間。在第2圖中，閘極區44是以虛線表示，其一般是以閘電極結構32定義。
各鰭30一般延伸於源極/汲極區34間，而源極/汲極區34係鄰近於各鰭30之相對兩側。換句話說，鰭式場效電晶體元件28之源極/汲極區34一般超出鰭30之末端，為容易描述，第2圖僅揭示單一源極/汲極區34。然而，需了解的是，源極鄰近鰭30之一末端，而分隔之汲極鄰近鰭30之另一末端。如第2圖所示，源極/汲極區34係以鑲嵌於例如第一保形層36中之源極/汲極材料(例如硼或磷)形成。
第一保形層36可例如由化學氣相沉積法(CVD)、原子層沉積法(ALD)或磊晶成長製程形成。第一保形層36亦可例如以雜質摻雜部分的鰭30或基底38形成，或進行一雜質分凝製程(impurity segregation)形成。如第2圖所示，第一保形層36和源極/汲極區34形成於其中的凹槽46可藉由以下製程形成：乾蝕刻、濕蝕刻、氯化氫或添加雜質蝕刻製程(impurities plus etch process)。
第一保形層36一般是圍繞著源極/汲極區34之鑲嵌部分形成。在一實施例中，第一保形層36形成在源極/汲極區除了頂部表面以外之所有表面上。即使如此，在其它的實施例中，第一保形層36可形成在源極/汲極區34更多或更少的表面上。
仍請參照第2圖，第一保形層36包括垂直側壁48和底牆50，其中垂直側壁48係以底牆50彼此分隔(或位於底牆之兩側)。如第2圖所揭示，垂直側壁48係以平行相鄰閘極區44之 方位配置。換句話說，各垂直側壁48之外表面54係平行閘極區44之垂直邊界線52，且垂直側壁48之外表面係以其上之閘電極結構32定義。
由於第一保形層36之垂直側壁48係如第2圖所示，平行閘極區44，鰭式場效電晶體元件28一般來說提供均勻的閘極控制和應變(相較於第1圖之鰭式場效電晶體元件28)。更甚者，第一保形層36降低或消除元件和元件間不希望有的變化。
在一實施例中，第一保形層36可抑制摻雜從從源極/汲極區之外擴散。第一保形層36亦可提供閘極區44張應力或壓應力。在一實施例中，第一保形層36是輕摻雜矽，且源極/汲極區34是輕摻雜汲極(lightly doped drain，簡稱LDD)。在一實施例中，第一保形層36之厚度56約在5nm和50nm之間。
在一實施例中，鰭式場效電晶體元件28之輕摻雜側壁48提供輕摻雜汲極(LDD)足夠的硼外擴散。此外，鰭式場效電晶體元件28提供相較於V形三層和U形三層矽鍺元件較大的矽鍺量和較高的應變。另外，鰭式場效電晶體元件28相較於V形三層矽鍺元件有較小閘極氧化層損傷。
現在請參照第3圖，在一實施例中，第一保形層36和鰭30之閘極區44分隔一距離58，此距離58大於或等於垂直側壁48之厚度60。在一實施例中，第一保形層36之垂直側壁48的厚度60小於或等於閘極區44之邊界52和一界面64(第一保形層36和源極/汲極區34間界面)間之距離62。
現在請參照第4圖，在一實施例中，第一保形層36 之垂直側壁48的長度66大於或等於閘極區44深度68之二分之一。如第4圖所示，垂直側壁48之長度66的量側是從具有均勻厚度60之垂直側壁48作為起始。事實上，在這些實施例中，形成第一保形層36和源極/汲極區34所佔據之凹槽46的步驟使用氨或其它物質。垂直側壁48朝上之表面可具有角度，如第4圖之P所示。在一實施例中，垂直側壁48朝上之表面和鰭30之表面間的角度P可以為70°或更少的角度。如第3圖所揭示，垂直側壁朝48上之表面可以是水平的。在一實施例中，底牆50之厚度70可以大於垂直側壁48之厚度60。
現在請參照第5圖，形成一個或更多個額外的保形層。事實上，一第二保形層72可形成於第一保形層36上方。同樣的，一第三保形層74可形成於第二保形層72上方。雖然第5圖揭示三個保形層36、72、74，可以理解的是，鰭式場效電晶體元件28可併入更多或更少的保形層。
在一實施例中，第一保形層36與第二保形層72和第三保形層74之一或兩者由不同的材料組成。此外，在一實施例中，第一保形層36可與第二保形層72和第三保形層74之一或兩者由不同的方式摻雜或摻雜不同的濃度。如此，鰭式場效電晶體元件28可產生需求的傾斜摻雜輪廓。
現在請參照第6圖，其揭示形成積體電路元件之方法76。在方塊78中，於鄰近鰭30之一末端形成一凹槽。如上所述，鰭30之閘極區一般是以閘電極結構32定義。在方塊80中，形成第一保形層36於凹槽46之暴露表面上方，如此第一保形層36之垂直側壁平行閘極區44。在方塊82中，於凹槽中第一保形 層36之內表面上方形成源/汲極區34。
本發明一實施例提供一種積體電路元件，包括：一鰭，具有一閘極區，閘極區位於一閘電極結構下；一源/汲極區，設置於超出鰭之末端的區域；及一第一保形層，圍繞源/汲極區之鑲嵌部分設置，其中第一保形層包括一垂直側壁，以平行閘極區之方位配置。
本發明一實施例提供一種積體電路元件，包括：一鰭，具有一閘極區，閘極區係垂直地位於一閘電極結構下；一源/汲極區，形成於超出鰭和閘電極結構之末端的區域；及一第一保形層，圍繞源/汲極區之鑲嵌部分形成，其中第一保形層具有一包括外表面之垂直側壁，外表面平行閘極區之一垂直邊界線。
本發明一實施例提供一種積體電路元件之製造方法，包括：形成一凹槽，鄰近一鰭之一末端，其中鰭具有一閘極區，位於一閘電極結構下；形成一第一保形層於凹槽之暴露表面上方，其中第一保形層之垂直側壁平行閘極區；及形成一源/汲極區於凹槽中之第一保形層的內表面上方。
雖然本發明之較佳實施例說明如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
28‧‧‧鰭式場效電晶體元件
30‧‧‧鰭
32‧‧‧閘電極結構
34‧‧‧源/汲極區
36‧‧‧第一保形層
38‧‧‧基底
40‧‧‧間隙壁
42‧‧‧金屬接觸
44‧‧‧閘極區
46‧‧‧凹槽
48‧‧‧垂直側壁
50‧‧‧底牆
52‧‧‧垂直邊界線
54‧‧‧外表面
56‧‧‧厚度

Claims (9)

  1. 一種積體電路元件，包括：一鰭，具有一閘極區，位於一閘電極結構下；一源/汲極區，設置超出該鰭之末端；及一第一保形層，圍繞該源/汲極區之一鑲嵌部分形成，其中該源/汲極區的導電型態與該第一保形層的導電型態相同，且該第一保形層包括一垂直側壁，以平行該閘極區之方位配置，其中該第一保形層係配置以提供該源/汲極區之摻雜外擴散，且提供應變至該閘極區。
  2. 如申請專利範圍第1項所述之積體電路元件，其中該第一保形層之垂直側壁的長度至少等於或大於該閘極區之深度的一半。
  3. 如申請專利範圍第1項所述之積體電路元件，尚包括一第二保形層，形成於該第一保形層上方，其中各該第一保形層和該第二保形層具有不同的摻雜，以產生傾斜摻雜輪廓。
  4. 如申請專利範圍第1項所述之積體電路元件，其中該第一保形層之垂直側壁的厚度至少小於或等於一距離，該距離為該閘極區之邊界和該第一保形層與該源極/汲極區間界面的距離。
  5. 如申請專利範圍第1項所述之積體電路元件，其中該第一保形層之垂直側壁的上表面和該鰭之上表面間的角度為0~70°。
  6. 一種積體電路元件，包括：一鰭，具有一閘極區，該閘極區係垂直地位於一閘電極結 構下；一源/汲極區，形成於超出該鰭和該閘電極結構之末端的區域；及一第一保形層，圍繞該源/汲極區之鑲嵌部分形成，其中該源/汲極區的導電型態與該第一保形層的導電型態相同，且該第一保形層具有一包括外表面之垂直側壁，該外表面平行該閘極區之一垂直邊界線，其中該第一保形層係配置以提供該源/汲極區之摻雜外擴散，且提供應變至該閘極區。
  7. 如申請專利範圍第6項所述之積體電路元件，尚包括一第二保形層，形成於該第一保形層上方，其中該第一保形層和該第二保形層具有不同的摻雜，以產生傾斜摻雜輪廓。
  8. 如申請專利範圍第6項所述之積體電路元件，其中該第一保形層係與該鰭之閘極區至少分隔該第一保形層之垂直側壁的厚度之距離。
  9. 一種積體電路元件之製造方法，包括：形成一凹槽，鄰近一鰭之一末端，其中該鰭具有一閘極區，位於一閘電極結構下；形成一第一保形層於該凹槽之暴露表面上方，其中該第一保形層之垂直側壁平行該閘極區，其中該第一保形層係配置以提供該源/汲極區之摻雜外擴散，且提供應變至該閘極區；及形成一源/汲極區於該凹槽中之第一保形層的內表面上方，該源/汲極區的導電型態與該第一保形層的導電型態相同。
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US9368628B2 (en) 2016-06-14
US20140008736A1 (en) 2014-01-09
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US20160293762A1 (en) 2016-10-06
KR20140005742A (ko) 2014-01-15
US9997629B2 (en) 2018-06-12

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