TWI636574B - 半導體結構 - Google Patents
半導體結構 Download PDFInfo
- Publication number
- TWI636574B TWI636574B TW103142049A TW103142049A TWI636574B TW I636574 B TWI636574 B TW I636574B TW 103142049 A TW103142049 A TW 103142049A TW 103142049 A TW103142049 A TW 103142049A TW I636574 B TWI636574 B TW I636574B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor structure
- region
- disposed
- difference
- source
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000002955 isolation Methods 0.000 claims description 14
- 239000002019 doping agent Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 51
- 238000000034 method Methods 0.000 description 22
- 229910052732 germanium Inorganic materials 0.000 description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 9
- 239000000463 material Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- RBFDCQDDCJFGIK-UHFFFAOYSA-N arsenic germanium Chemical compound [Ge].[As] RBFDCQDDCJFGIK-UHFFFAOYSA-N 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- GPMBECJIPQBCKI-UHFFFAOYSA-N germanium telluride Chemical group [Te]=[Ge]=[Te] GPMBECJIPQBCKI-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000006210 lotion Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7847—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本發明係提供一種半導體結構，包含一基底、一閘極結構、一源極/汲極區以及至少一差排。閘極結構設置在基底上。源極/汲極區設置在閘極結構兩側的基底中。差排設置在源極/汲極區中，且該差排相較於該源極/汲極的一中心軸呈非鏡向對稱。
Description
本發明是關於一種半導體結構，特別來說，是關於一種具有非對稱差排的半導體結構。
近年來，隨著各種消費性電子產品不斷的朝小型化發展，半導體元件設計的尺寸亦不斷縮小，以符合高積集度、高效能和低耗電之潮流以及產品需求。
然而，隨著電子產品的小型化發展，現有的平面電晶體(planar transistor)已經無法滿足產品的需求。因此，目前發展出一種非平面電晶體(non-planar)之鰭狀電晶體(Fin-FET)技術，其係具有立體的閘極通道(channel)結構。鰭狀場效電晶體元件的製程能與傳統的邏輯元件製程整合，因此具有相當的製程相容性，且由於鰭狀結構之立體形狀增加了閘極與矽的接觸面積，因此可增加閘極對於通道區域電荷的控制，以降低小尺寸元件帶來的汲極引發的能帶降低(Drain Induced Barrier Lowering,DIBL)效應以及短通道效應(short channel effect)。現有的鰭狀電晶體也持續改良，以朝更小尺寸的方向邁進。
為求得更優異表現的元件性能，本發明於是提供了一種半導體結構，可應用在非平面電晶體或是平面電晶體上。
根據本發明其中一種實施方式，本發明係提供一種半導體結構，包含一基底、一閘極結構、一源極/汲極區以及至少一差排。閘極結構設置在基底上。源極/汲極區設置在閘極結構兩側的基底中。差排設置在源極/汲極區中，且該差排相較於該源極/汲極的一中心軸呈非鏡向對稱。
300‧‧‧基底
302a‧‧‧第一淺溝渠隔離
302b‧‧‧第二淺溝渠隔離
304,304A,304B‧‧‧鰭狀結構
306‧‧‧閘極結構
306a‧‧‧閘極介電層
306b‧‧‧導電層
306c‧‧‧蓋層
310‧‧‧側壁子
312‧‧‧凹槽
314‧‧‧緩衝層
316‧‧‧磊晶層
317‧‧‧源極/汲極區
318‧‧‧接觸洞蝕刻停止層
320,320A,320B‧‧‧差排
400‧‧‧區域
402‧‧‧第一方向
404‧‧‧第二方向
第1圖、第2圖、第3圖、第4A圖、第4B圖、第5A圖、第5B圖、第6A圖、第6B圖與第7圖為本發明一種形成半導體結構的方法步驟示意圖。
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之數個較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。
請參考第1圖、第2圖、第3圖、第4A圖、第4B圖、第5A圖、第5B圖、第6A圖、第6B圖與第7圖，所繪示為本發明一種形成半導體結構的方法的步驟示意圖。其中第1圖為一立體圖，而第2圖、第3圖、第4A圖、第5A圖、第6A圖與第7圖為沿著第1圖的AA'切線所繪製的剖面圖，而第4B圖、第5B圖與第6B圖則是沿著第1圖的BB'切線所繪製的剖面圖。
首先請參考第1圖，提供一基底300，其係用來在其上形成所需之元件或電路，較佳具有含矽材質，例如是矽、單晶矽(single crystal silicon)、單晶矽鍺(single crystal silicon germanium)、非晶矽(amorphous silicon)或是上述的組合。於另一實施例中，基底300也可以包含其他半導體材質，例如是鍺或III/V族的複合半導體材料，如鍺砷等。於另一實施例中，基底300也可以包含其他介電材料，例如是矽覆絕緣基底(silicon on insulator,SOI)。基底300
上定義有一區域400，區域400中設置有複數個鰭狀結構(fin structure)304、複數個第一淺溝渠隔離(shallow trench isolation,STI)302A以及(複數個閘極結構(gate structure)306。於本發明之一實施例中，區域400被一第二淺溝渠隔離302B所包圍，第二淺溝渠隔離302B的深度大於第一淺溝渠隔離302A的深度；但於另一實施例中，第二淺溝渠隔離302B的深度也可以和第一淺溝渠隔離302A的深度相同。於另一實施例中，區域400是一緻密區(dense region)，其相較於區域400以外的疏離區(isolation region)，具有較大的元件密度，例如鰭狀結構304所排列的密度較高，較佳鰭狀結構304具有一臨界尺寸(critical dimension,CD)。
如第1圖所示，鰭狀結構304大體上沿著一第一方向402延伸，且與第一淺溝渠隔離302A彼此間隔地(alternatively)均勻排列。在第1圖中係以4個鰭狀結構304為示例，而本領域具有通常知識者也應了解在區域400內亦可包含有4個以上或以下的鰭狀結構304。於本發明較佳實施例中，最靠近區域400邊緣的兩個鰭狀結構304A，相較位在區域400中央的鰭狀結構304B具有較大的寬度，例如是1.5倍至3倍的寬度。形成鰭狀結構304的步驟，例如是先在基底300上形成圖案化硬遮罩層(圖未示)，然後再進行一蝕刻製程以在基底300中形成複數個溝渠(圖未示)。接著以絕緣材料例如二氧化矽填滿溝渠，在進行一平坦化及/或蝕刻製程，以形成第一淺溝渠隔離302A，使著突出於淺溝渠隔離302之基底300部分形成鰭狀結構304。
後續，在基底300上形成複數個閘極結構306，大體上沿著一第二方向404延伸，第二方向404大體上與第一方向402垂直。於一實施例中，閘極結構306由下至上包含一閘極介電層306A、一導電層306B以及一蓋層306C。於一實施例中，閘極介電層306A例如是二氧化矽，或是高介電材料，例如是介電常數高於4的材料。導電層306B例如是多晶矽(poly silicon)或是
金屬。蓋層306C例如包含氮化矽(SiN)、碳化矽(SiC)或氮氧化矽(SiON)。於一實施例中，蓋層306C可以是一層或多層不同介電材料所組成，例如可以包含一第一蓋層(圖未示)與第二蓋層(圖未示)，分別包含氧化矽和氮化矽。後續，在閘極結構306的側壁上形成一側壁子(spacer)310。側壁子310可以是單層或複合膜層之結構，其可包含高溫氧化矽層(high temperature oxide,HTO)、氮化矽、氧化矽或使用六氯二矽烷(hexachlorodisilane,Si2Cl6)形成的氮化矽(HCD-SiN)。
後續，請參考第2圖所繪示的剖面圖，進行一次或多次的蝕刻製程，以在閘極結構306兩側之鰭狀結構304中形成至少一凹槽(recess)312。於本發明較佳實施例中，所形成的凹槽312的輪廓較佳為圓弧狀，其形成方式例如用一次或多次的乾蝕刻製程，並在越後段執行的乾蝕刻製程中調整偏壓功率(bias power)，直至產生圓弧狀凹槽312為止。所形成的凹槽312並不會如習知使用濕蝕刻技術會具有如鑽石或六角等多邊形的角度。在形成凹槽312後，可選擇性進行一清洗步驟，以稀釋氫氟酸(diluted hydrofluoric acid)或其他洗劑以去除不純物質。
如第3圖所示，在凹槽312中形成一緩衝層(buffer layer)314，以覆蓋在凹槽312內鰭狀結構304或基底300的表面上。在本實施例中，緩衝層314是以共形(conformally)的方式選擇性磊晶成長於凹槽312圓弧基底300的表面上，因此所形成的緩衝層314也會具有圓弧剖面，且較佳具有均一厚度。於本發明之一實施例中，若後續形成的電晶體為N形電晶體，則緩衝層314的材料可以是矽化磷(SiP)，且磷的濃度較佳大於1*10-21顆原子/平方公分，以提供後續N形電晶體適當的伸張應力(tensile)。而於另一實施例中，若後續形成的電晶體為P形電晶體，則緩衝層的材料則為矽化鍺。
接著請參考第4A圖與第4B圖，其中第4A圖為第1圖沿AA'剖面切線，而第4B圖為第1圖沿BB'剖面切線繪製。首先請參考第4A圖，進行一選擇性磊晶成長製程，以形成一磊晶層316於緩衝層314上。於一實施例中，磊晶層316會填滿凹槽312，並稍微突出於凹槽312，或者，與凹槽312的開口大體上齊平。於一實施例中，磊晶層316的鍺或矽的濃度大於緩衝層314的鍺或矽的濃度，如此一來可以減少磊晶層316中的缺陷。後續，進行一離子佈植(implant)製程，以在磊晶層316的一部或全部中植入適當的摻質(dopant)，以形成源極/汲極區317。若電晶體為N形電晶體，則源極/汲極區317係植入N形摻質；若電晶體為P形電晶體，則源極/汲極區317植入P形摻質。於本發明之一實施例中，前述形成源極/汲極區317的離子佈植製程可作為一非晶化植入製程(pre-amorphous implantation,PAI)，以使部分或全部的磊晶層316非晶化。於本發明另一實施例中，亦可在形成磊晶層316時以原位處理(in-situ)的方式伴隨著磊晶成長製程導入摻質，而一併形成磊晶層316和源極/汲極區317。後續，則需進行一非晶化植入製程(pre-amorphous implantation,PAI)，例如使用鍺或砷等原子以對磊晶層316進行植入，而將部分或全部的磊晶層316非晶化。值得注意的是，前述無論是源極/汲極區317的植入製程或是非晶化植入製程，較佳都不會作用在緩衝層314上。另一方面，如第4B圖所示，由於靠近區域400邊緣的鰭狀結構304A具有較大的寬度，所形成的磊晶層316A也具有較大的體積，而鰭狀結構304B上的磊晶層316B則具有較小的體積。此外，於本發明另一實施例中，請參考第5A圖與第5B圖，所繪示為本發明另一實施例中的步驟示意圖。如第5A圖與第5B圖所示，所形成的磊晶層316也可以具有非圓弧狀的頂面，例如具有一個或一個以上的角(corner)，而在突出於鰭狀結構304的部份形成類似於五邊形的剖面。但本發明的磊晶層316也可視產品設計或製程而具有不同的剖面結構。下文步驟仍以第4A圖與第4B圖的實施例為說明。
接著請參考第6A圖與第6B圖，第6A圖為第1圖沿AA'剖面切線，而第6B圖為第1圖沿BB'剖面切線繪製。如第6A圖所示，在基底300上全面形成一接觸蝕刻停止層(contact etch stop layer,CESL)318，以覆蓋在磊晶層316(或是覆蓋層)、側壁子310以及閘極結構306上。在本發明中，接觸洞蝕刻停止層318具有一應力(stress)，以作為一選擇性應力系統(selective strain scheme,SSS)。於本發明之一實施例中，若後續形成的電晶體為N型電晶體，則接觸洞蝕刻停止層318的應力較佳是伸張應力，若為P型電晶體，則較佳是壓縮應力，但亦可視元件設計而有所調整。
後續，如第7圖所示，進行一退火製程(annealing)，以將磊晶層316再次結晶(re-crystallization)。於一實施例中，退火製程例如是在攝氏400度至700度的環境下進行。在經過退火製程後，磊晶層316中即會形成複數個差排(dislocation)，且位在每個磊晶層316中的差排相較於磊晶層316(或是源極/汲極區317)的中心軸線I而言，呈現非鏡向對稱(asymmetrical)的排列。於本發明之一實施例中，以第6圖左側磊晶層316中的差排320為例，右邊(靠近區域400邊緣)的差排320B較嚴重，換句話說，右邊的差排320B較粗，而左邊的差排320A則較細。而於另一實施例中，差排320B相較於另一個差排320A的延伸距離較長。而於另一實施例中，以第7圖右邊磊晶層316為例，左邊並沒有差排，而右邊則有差排320C。此外，本發明另外一個特徵在於，這種非對稱性的差排320並不會穿過緩衝層316，並且。此種差排結構可在N型電晶體或是P型電晶體中。
值得注意的是，前述實施例是以非平面電晶體(non-planar transistor)的實施態樣進行說明，但本領域技術人員應可理解本發明亦可應用於平面電晶體(planar transistor)。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
Claims (20)
- 一種半導體結構，包含：一閘極結構設置在一基底上；至少一源極/汲極區設置在該閘極結構兩側的該基底中；以及至少一差排(dislocation)設置在其中一個直接相鄰且位在兩個該閘極結構的該源極/汲極區中，其中該差排相較於該差別所位在的該源極/汲極區的一垂直中心軸呈非鏡向對稱(asymmetrical)。
- 如申請專利範圍第1項所述的半導體結構，其中該差排具有一個，設在該中心軸的一側。
- 如申請專利範圍第1項所述的半導體結構，其中該差排具有兩個，分別設置在該中心軸的兩側。
- 如申請專利範圍第3項所述的半導體結構，其中一個差排相較於另一個差排嚴重(server)。
- 如申請專利範圍第3項所述的半導體結構，其中一個差排相較於另一個差排的延伸距離較長。
- 如申請專利範圍第1項所述的半導體結構，還包含複數個鰭狀結構設置在該基底中，其中該源極/汲極區設置在該閘極結構兩側的該鰭狀結構中。
- 如申請專利範圍第6項所述的半導體結構，其中該基底定義有一區域，且該區域最靠近邊緣的兩個該鰭狀結構的寬度大於其他鰭狀結構的寬度。
- 如申請專利範圍第7項所述的半導體結構，其中該差排具有兩個，分別設置在該中心軸的兩側，且遠離該區域的邊緣的該差排相較於靠近該區域的邊緣的該差排嚴重(server)。
- 如申請專利範圍第7項所述的半導體結構，其中該區域為緻密區(dense region)。
- 如申請專利範圍第7項所述的半導體結構，還包含複數個第一淺溝渠隔離與該等鰭狀結構交替排列。
- 如申請專利範圍第10項所述的半導體結構，其中該區域被一第二淺溝渠隔離包圍，且該第二淺溝渠隔離的深度大於該第一淺溝渠隔離的深度。
- 如申請專利範圍第7項所述的半導體結構，其中還包含至少一磊晶層設置在該鰭狀結構中，其中該源極/汲極區設置在該閘極結構兩側的該磊晶層中。
- 如申請專利範圍第12項所述的半導體結構，其中該區域最靠近邊緣的兩個該鰭狀結構的該磊晶層體積大於其他鰭狀結構中該磊晶層的體積。
- 如申請專利範圍第12項所述的半導體結構，還包含一緩衝層設置在該磊晶層與該鰭狀結構之間。
- 如申請專利範圍第14項所述的半導體結構，其中該緩衝層具有一實質上圓弧狀之剖面。
- 如申請專利範圍第14項所述的半導體結構，其中該緩衝層具有一均勻厚 度。
- 如申請專利範圍第14項所述的半導體結構，其中該緩衝層直接包圍且接觸該磊晶層且與該磊晶層邊緣共形。
- 如申請專利範圍第14項所述的半導體結構，其中該差排沒有穿過該緩衝層。
- 如申請專利範圍第1項所述的半導體結構，其中該源極/汲極區包含N型摻質。
- 如申請專利範圍第1項所述的半導體結構，其中該源極/汲極區包含P型摻質。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103142049A TWI636574B (zh) | 2014-12-03 | 2014-12-03 | 半導體結構 |
| US14/594,159 US9899523B2 (en) | 2014-12-03 | 2015-01-11 | Semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103142049A TWI636574B (zh) | 2014-12-03 | 2014-12-03 | 半導體結構 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201622157A TW201622157A (zh) | 2016-06-16 |
| TWI636574B true TWI636574B (zh) | 2018-09-21 |
Family
ID=56095051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103142049A TWI636574B (zh) | 2014-12-03 | 2014-12-03 | 半導體結構 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9899523B2 (zh) |
| TW (1) | TWI636574B (zh) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10249502B2 (en) * | 2016-01-22 | 2019-04-02 | International Business Machines Corporation | Low resistance source drain contact formation with trench metastable alloys and laser annealing |
| TWI736644B (zh) * | 2017-06-29 | 2021-08-21 | 聯華電子股份有限公司 | 場效電晶體及元件 |
| CN109817713B (zh) * | 2017-11-22 | 2022-04-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
| CN111435679B (zh) * | 2019-01-14 | 2023-06-13 | 联华电子股份有限公司 | 具有非对称应变源极/漏极结构的半导体元件其制作方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130099314A1 (en) * | 2011-10-20 | 2013-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device With Multiple Stress Structures And Method Of Forming The Same |
| US20130228862A1 (en) * | 2012-03-02 | 2013-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") | Semiconductor device having a strained region |
| US20140131812A1 (en) * | 2012-11-09 | 2014-05-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source and Drain Dislocation Fabrication in FinFETs |
| US20140167120A1 (en) * | 2012-12-17 | 2014-06-19 | Globalfoundries Inc. | Methods of forming a finfet semiconductor device by performing an epitaxial growth process |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7696019B2 (en) | 2006-03-09 | 2010-04-13 | Infineon Technologies Ag | Semiconductor devices and methods of manufacturing thereof |
| US7618866B2 (en) | 2006-06-09 | 2009-11-17 | International Business Machines Corporation | Structure and method to form multilayer embedded stressors |
| US7772074B2 (en) | 2007-10-18 | 2010-08-10 | Applied Materials, Inc. | Method of forming conformal silicon layer for recessed source-drain |
| US8115194B2 (en) * | 2008-02-21 | 2012-02-14 | United Microelectronics Corp. | Semiconductor device capable of providing identical strains to each channel region of the transistors |
| US7838887B2 (en) | 2008-04-30 | 2010-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain carbon implant and RTA anneal, pre-SiGe deposition |
| US8779477B2 (en) | 2008-08-14 | 2014-07-15 | Intel Corporation | Enhanced dislocation stress transistor |
| US8193049B2 (en) | 2008-12-17 | 2012-06-05 | Intel Corporation | Methods of channel stress engineering and structures formed thereby |
| US8952429B2 (en) * | 2010-09-15 | 2015-02-10 | Institute of Microelectronics, Chinese Academy of Sciences | Transistor and method for forming the same |
| US8629046B2 (en) | 2011-07-06 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with a dislocation structure and method of forming the same |
| US20130069172A1 (en) | 2011-09-16 | 2013-03-21 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
| US8809918B2 (en) * | 2011-10-24 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOSFETs with multiple dislocation planes |
| US8674453B2 (en) | 2011-12-13 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming stressor regions in a semiconductor device |
| US8723266B2 (en) | 2011-12-13 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pinch-off control of gate edge dislocation |
| DE112011105973T5 (de) | 2011-12-19 | 2014-09-25 | Intel Corporation | Halbleitervorrichtung mit metallischen Quellen- und Senkenregionen |
| US8916428B2 (en) | 2012-01-05 | 2014-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device |
| US8828817B2 (en) | 2012-01-23 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
| US20130200455A1 (en) | 2012-02-08 | 2013-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dislocation smt for finfet device |
| US8785285B2 (en) | 2012-03-08 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
| US8877599B2 (en) | 2012-05-15 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device |
| US8889501B2 (en) | 2012-06-01 | 2014-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming MOS devices with raised source/drain regions |
| US8610241B1 (en) * | 2012-06-12 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Homo-junction diode structures using fin field effect transistor processing |
| US9368628B2 (en) | 2012-07-05 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with high mobility and strain channel |
| US9324622B2 (en) | 2012-08-15 | 2016-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
| US20140120678A1 (en) | 2012-10-29 | 2014-05-01 | Matheson Tri-Gas | Methods for Selective and Conformal Epitaxy of Highly Doped Si-containing Materials for Three Dimensional Structures |
| US9252008B2 (en) | 2013-01-11 | 2016-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxial formation mechanisms of source and drain regions |
| US8853039B2 (en) | 2013-01-17 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect reduction for formation of epitaxial layer in source and drain regions |
| US9293466B2 (en) * | 2013-06-19 | 2016-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded SRAM and methods of forming the same |
-
2014
- 2014-12-03 TW TW103142049A patent/TWI636574B/zh active
-
2015
- 2015-01-11 US US14/594,159 patent/US9899523B2/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130099314A1 (en) * | 2011-10-20 | 2013-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device With Multiple Stress Structures And Method Of Forming The Same |
| US20130228862A1 (en) * | 2012-03-02 | 2013-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") | Semiconductor device having a strained region |
| US20140131812A1 (en) * | 2012-11-09 | 2014-05-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source and Drain Dislocation Fabrication in FinFETs |
| US20140167120A1 (en) * | 2012-12-17 | 2014-06-19 | Globalfoundries Inc. | Methods of forming a finfet semiconductor device by performing an epitaxial growth process |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201622157A (zh) | 2016-06-16 |
| US9899523B2 (en) | 2018-02-20 |
| US20160163797A1 (en) | 2016-06-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11121213B2 (en) | Fin recess last process for FinFET fabrication | |
| US20200303258A1 (en) | Fin Spacer Protected Source and Drain Regions in FinFETs | |
| US10868186B2 (en) | FinFETs with source/drain cladding | |
| KR101637679B1 (ko) | Ｆⅰｎｆｅｔ을 형성하기 위한 메커니즘들을 포함하는 반도체 디바이스및 그 형성 방법 | |
| TWI590451B (zh) | 鰭式場效電晶體結構及其形成方法 | |
| US8987791B2 (en) | FinFETs and methods for forming the same | |
| TWI699885B (zh) | 半導體結構與其製作方法 | |
| KR101802715B1 (ko) | 반도체 디바이스의 제조 방법 | |
| US9159552B2 (en) | Method of forming a germanium-containing FinFET | |
| KR101496519B1 (ko) | 더미 ＦｉｎＦＥＴ 구조 및 더미 ＦｉｎＦＥＴ 구조를 만드는 방법 | |
| KR20160099447A (ko) | 랩어라운드 실리사이드를 구비한 ｆｉｎｆｅｔ 및 그 형성 방법 | |
| US9530871B1 (en) | Method for fabricating a semiconductor device | |
| US9691901B2 (en) | Semiconductor device | |
| US9570606B2 (en) | FinFET LDMOS device and manufacturing methods | |
| TWI678732B (zh) | 一種形成半導體鰭狀結構的方法 | |
| US10014406B2 (en) | Semiconductor device and method of forming the same | |
| TW201714309A (zh) | 鰭式場效應電晶體結構及其製造方法 | |
| TWI671901B (zh) | 半導體元件及其製造方法 | |
| TWI636574B (zh) | 半導體結構 | |
| TW201803113A (zh) | 金氧半導體與形成方法 | |
| US20180097109A1 (en) | Semiconductor device | |
| WO2022048134A1 (zh) | 带铁电或负电容材料的器件及制造方法及电子设备 | |
| KR102610265B1 (ko) | 반도체 소자 및 이의 제조 방법 | |
| TWI527229B (zh) | 半導體元件 |