TWI678732B - 一種形成半導體鰭狀結構的方法 - Google Patents

一種形成半導體鰭狀結構的方法 Download PDF

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TWI678732B
TWI678732B TW105108732A TW105108732A TWI678732B TW I678732 B TWI678732 B TW I678732B TW 105108732 A TW105108732 A TW 105108732A TW 105108732 A TW105108732 A TW 105108732A TW I678732 B TWI678732 B TW I678732B
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fin structure
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TW201735131A (zh
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馮立偉
Li-wei FENG
蔡世鴻
Shih-Hung Tsai
許智凱
Chih-Kai Hsu
鄭志祥
Jyh-Shyang Jenq
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聯華電子股份有限公司
United Microelectronics Corp.
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Priority to US15/196,024 priority patent/US10056467B2/en
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Priority to US15/995,083 priority patent/US10263095B2/en
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Abstract

本發明提供一種形成半導體鰭狀結構的方法。首先提供一基底，該基底具有至少兩個次區域以及一個虛置區，該虛置區設置在該兩個次區域之間，各該次區域中具有一溝渠。形成一半導體層完全填滿該溝渠。接著形成一圖案化遮罩層於次區域的半導體層上以及虛置區的基底上。最後，以圖案化遮罩層為遮罩，移除部分的半導體層以及基底，以在次區域中形成複數個鰭狀結構，以及在虛置區中形成複數個虛置鰭狀結構。本發明還包含一種半導體鰭狀結構。

Description

一種形成半導體鰭狀結構的方法
本發明係關於一種在半導體領域中形成鰭狀結構的方法，特別來說，係關於一種能在形成具有兩種半導體材質的鰭狀結構的方法。
近年來，隨著各種消費性電子產品不斷的朝小型化發展，半導體元件設計的尺寸亦不斷縮小，以符合高積集度、高效能和低耗電之潮流以及產品需求。
然而，隨著電子產品的小型化發展，現有的平面電晶體(planar transistor)已經無法滿足產品的需求。因此，目前發展出一種非平面電晶體(non-planar)之鰭狀電晶體(Fin-FET)技術，其係具有立體的閘極通道(channel)結構。鰭狀場效電晶體元件的製程能與傳統的邏輯元件製程整合，因此具有相當的製程相容性，且由於鰭狀結構之立體形狀增加了閘極與矽的接觸面積，因此可增加閘極對於通道區域電荷的控制，以降低小尺寸元件帶來的汲極引發的能帶降低(Drain Induced Barrier Lowering,DIBL)效應以及短通道效應(short channel effect)。現有的鰭狀電晶體也持續改良，以朝更小尺寸的方向邁進。
本發明提供了一種半導體鰭狀結構的製作方法，可以具有較佳的產品效能。
根據本發明其中一種實施例，是提供一種形成鰭狀結構的方法。首先提供一基底，該基底具有至少兩個次區域以及一個虛置區，該虛置區設置在該兩個次區域之間，各該次區域中具有一溝渠。形成一半導體層完全填滿該溝渠。接著形成一圖案化遮罩層於次區域的半導體層上以及虛置區的基底上。最後，以圖案化遮罩層為遮罩，移除部分的半導體層以及基底，以在次區域中形成複數個鰭狀結構，以及在虛置區中形成複數個虛置鰭狀結構。
本發明係提供了一種形成半導體鰭狀結構的方法，其特徵在於在第一區域中劃分有較小的次區域，故後續半導體層形成時會各自形成在次區域中，減小在形成半導體層時頂面下凹的現象。
300‧‧‧基底
300A‧‧‧頂面
302‧‧‧襯墊層
304‧‧‧圖案化遮罩層
306‧‧‧氧化層
308‧‧‧氮化層
310‧‧‧氧化層
312‧‧‧堆疊結構
314‧‧‧中柱層
316‧‧‧側壁子
400‧‧‧第一區域
400A‧‧‧次區域
400B‧‧‧虛置區
406‧‧‧半導體層
408‧‧‧第一鰭狀結構
408A‧‧‧第一部分
408B‧‧‧第二部分
410‧‧‧虛置鰭狀結構
412‧‧‧第一隔離結構
414‧‧‧第一閘極介電層
416‧‧‧第一閘極
500‧‧‧第二區域
502‧‧‧P型井
508‧‧‧第二鰭狀結構
512‧‧‧第二隔離結構
514‧‧‧第二閘極介電層
402‧‧‧N型井
404‧‧‧溝渠
516‧‧‧第二閘極
第1圖至第8圖繪示了本發明一種形成鰭狀結構的方法的步驟示意圖。
第9圖繪示為本發明一實施例中形成電晶體的步驟示意圖。
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之數個較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。
請參考第1圖至第8圖，所繪示為本發明一種形成鰭狀結構的方法的 步驟示意圖。如第1圖所示，首先提供一基底300具有一頂面300A，其係用來形成所需之元件或電路，較佳具有含矽材質，例如是矽、單晶矽(single crystal silicon)、單晶矽鍺(single crystal silicon germanium)、非晶矽(amorphous silicon)或是上述的組合。於另一實施例中，基底300也可以包含其他半導體材質，例如是鍺或III/V族的複合半導體材料，如鍺砷等。於另一實施例中，基底300也可以包含其他介電材料，例如是矽覆絕緣基底(silicon on insulator,SOI)。基底300上具有一第一區域400以及一第二區域500。於一實施例中，第一區域400是一P型電晶體區，故在第一區域400的基底300中具有一N型井402；而第二區域500是一N型電晶體區，故在第二區域500的基底300中具有一P型井502。形成N型井402與P型井502的方法，例如先在基底300之頂面300A形成一襯墊層302，襯墊層302較佳是由熱氧化製程形成的二氧化矽(silicon oxide)，而具有一預定厚度。接著在襯墊層302上形成一第一圖案化層(圖未示)，以第一圖案化層為遮罩進行離子佈植製程形成N型井402，移除第一圖案化層；在襯墊層302上形成一第二圖案化層(圖未示)，以第二圖案化層為遮罩進行離子佈植製程形成P型井502，移除第二圖案化層。當然，視製程情況而定，形成N型井402與P型井502的順序可以顛倒。此外，第一區域400中具有複數個次區域400A以及至少一個虛置區400B，虛置區400B設置在兩個次區域400A之間。而於另一實施例中，襯墊層302也可以省略。
如第2圖所示，在襯墊層302上形成一圖案化遮罩層304。在第一區域400中，圖案化遮罩層304暴露出次區域400A中的襯墊層302，並覆蓋次區域400A以外的襯墊層302，包括覆蓋虛置區400B的襯墊層302；在第二區域500中，襯墊層302同樣也會被覆蓋。圖案化遮罩層304可以是適合作為遮罩的材料，例如是氮化矽(SiN)、氮氧化矽(SiON)、碳化矽(SiC)或由應用材料公司提供之進階圖案化薄膜(advanced pattern film,APF)。於本發明之一實施例中，圖案化遮罩層304 為光阻層。
如第3圖所示，以圖案化遮罩層304為遮罩，圖案化暴露出之襯墊層302以及基底300，而在基底300之次區域400A中形成複數個溝渠404。如第3圖所示，溝渠404的深度不會超過N型井402的深度。於一實施例中，溝渠404的深度與N型井的深度介於1：2~1：3之間。然後，將圖案化遮罩層304移除。
如第4圖所示，在溝渠404中形成一半導體層406，並且使之填滿溝渠404。於一實施例中，半導體層406是透過一選擇性磊晶成長(selective epitaxial growth,SEG)製程形成，其材質可以是任何矽及/或鍺化合物，且可任意摻雜III族及/或V族元素。於一實施例中，半導體層406是矽化鍺(SiGe)。由於半導體層406是在同一個磊晶成長製程各自分開地形成在次區域400A中的溝渠404，故磊晶成長後之半導體層406的頂面僅有微幅的下凹現象(dishing)，可使形成之半導體層406均勻性較佳。
如第5圖所示，進行一平坦化(planarization)製程，使半導體層406與襯墊層302齊平。於本發明之一實施例中，平坦化製程例如是化學機械研磨(chemical mechanical polishing,CMP)製程，並以襯墊層302的頂面為研磨停止層，因此，半導體層406的頂面會高於基底300之頂面300A。
如第6圖所示，在基底300上形成一堆疊結構312，例如一氧化層306、一氮化層308與一氧化層310，以及在堆疊結構312上形成複數中柱層314，並在每個中柱層314之側壁上形成一側壁子316。於一實施例中，中柱層314的材料例如是多晶矽(poly-silicon)或非晶矽(amorphous silicon)，而側壁子316的材料例如 是氧化矽、氮化矽、高溫氧化矽層(high temperature oxide,HTO)或包含六氯二矽烷(hexachlorodisilane,Si2Cl6)形成的氮化矽(HCD-SiN)，但並不以此為限。
如第7圖所示，在移除中柱層314後，以側壁子316為遮罩，依序蝕刻堆疊結構312以及基底300至一預定深度。是以，在第一區域400的次區域400A中形成複數個第一鰭狀結構408，在第一區域400的虛置區400B中形成複數個虛置鰭狀結構410，而在第二區域400中形成複數個第二鰭狀結構508。在蝕刻製程後，還有部分的堆疊結構312位在第一鰭狀結構408、虛置鰭狀結構410以及第二鰭狀結構508上。值的注意的是，前述第6圖與第7圖之圖案化過程是以側面圖案轉移(sidewall image transfer,SIT)步驟為示例，本發明具有通常知識者也應了解，可以使用一般的圖案化製程，例如在第5圖的結構上直接形成一圖案化遮罩層對應各鰭狀結構的位置，在蝕刻製程後也同樣可以形成所述的鰭狀結構。在形成第一鰭狀結構408以及虛置鰭狀結構410之後，N型井402會位於第一鰭狀結構408以及虛置鰭狀結構410內，且虛置鰭狀結構410內的N型井402的頂面高度會高於第一鰭狀結構408內的N型井402的頂面高度。
如第8圖所示，移除位在虛置區400B中的虛置鰭狀結構410，使虛置區400B中的最底面與次區域400A中的最底面大體上齊平。而於本發明另一實施例中，也可以不移除虛置鰭狀結構410或者僅移除虛置鰭狀結構410至一預定高度。此外，將第一鰭狀結構408以及第二鰭狀結構508上的堆疊結構312完全移除，使第一鰭狀結構408以及第二鰭狀結構508的頂面暴露出來。如第8圖所示，第一鰭狀結構408包含一第一部分408A以及一第二部分408B，第一部分408A即為半導體層406之材質，第二部分408B為基底300之材質。第一鰭狀結構408突出於基底300之頂面300A，第二鰭狀結構508的頂面與基底300的頂面300A齊平。 而於本發明另一實施例中，也可不移除堆疊結構312。
透過上述的步驟，即可完成半導體之鰭狀結構。於本發明之一實施例中，可視產品需求而再進行其他半導體製程，請參考第9圖，所繪示為本發明一實施例中形成電晶體的步驟示意圖。在完成第8圖所示的鰭狀結構後，可在第一鰭狀結構408之間形成一第一隔離結構412，在第一鰭狀結構408上形成一第一閘極介電層414與第一閘極416，並在第一閘極416兩側的第一鰭狀結構408中形成適當摻質，即可在第一區域400中形成P型電晶體。同樣的，在第二鰭狀結構508之間形成一第二隔離結構512，在第二鰭狀結構508上形成一第二閘極介電層514與第一閘極516，並在第二閘極516兩側的第二鰭狀結構508中形成適當摻質，即可在第二區域500中形成N型電晶體。在其他實施例中，可視情況再進行其他半導體製程，例如金屬閘極置換製程。
本發明主要特點在於，在同一個導電型的井中(例如N型井402)，形成較小面積的半導體層406，可避免半導體層406的頂面下凹(dishing)的現象。前述實施例是在複數個溝渠404中，同時形成一半導體層406，而在本發明另一實施例中，也可在同一個導電型的井中(例如N型井402)先後形成相同或不同大小的複數個溝渠，以先後在不同的溝渠中形成不同的半導體層，每個溝渠中的半導體層也可避免下凹現象。
此外，在前述實施例中，是以第一區域400中形成半導體層406，第二區域500中沒有形成半導體層為示例。而在本發明其他實施例中，第二區域500也可形成半導體層，例如在第2圖中部分或全部的襯墊層302可以被圖案化遮罩層304暴露出來，後續形成溝渠時可以產生半導體層，而使第二鰭狀結構508也 具有不同的半導體材料。而在本發明另一實施例中，第二區域500也可以是用以形成一般的平面電晶體(planar transistor)。
綜上所述，本發明係提供了一種形成半導體鰭狀結構的方法，其特徵在於在第一區域中劃分有較小的次區域，故後續半導體層形成時會各自形成在次區域中，減小在形成半導體層時頂面下凹的現象。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (14)

  1. 一種形成半導體鰭狀結構的方法，包含：提供一基底，該基底具有至少兩個次區域以及一個虛置區，該虛置區設置在該兩個次區域之間；在該些次區域以及該虛置區中形成一摻質井；在形成該摻質井之後，於各該次區域中形成一溝渠；形成一半導體層完全填滿該等溝渠；形成一圖案化遮罩層於該等次區域的該半導體層上以及該虛置區的該基底上；以及移除部分的該半導體層以及該基底，以在該次區域中形成複數個鰭狀結構，以及在該虛置區中形成複數個虛置鰭狀結構，其中該摻質井會位於該些鰭狀結構及該些虛置鰭狀結構內，且該些虛置鰭狀結構內的該摻質井的頂面高度會高於該些鰭狀結構內的該摻質井的頂面高度。
  2. 如申請專利範圍第1項所述之形成半導體鰭狀結構的方法，其中該摻質井的深度大於該溝渠的深度。
  3. 如申請專利範圍第1項所述之形成半導體鰭狀結構的方法，其中形成該半導體層的方法包含一選擇性磊晶成長製程。
  4. 如申請專利範圍第1項所述之形成半導體鰭狀結構的方法，在形成該溝渠之前，還包含在該基底之一頂面上形成一襯墊層。
  5. 如申請專利範圍第4項所述之形成半導體鰭狀結構的方法，在形成該半導體層後，還包含進行一平坦化製程。
  6. 如申請專利範圍第5項所述之形成半導體鰭狀結構的方法，在進行完該平坦化製程後，該半導體層的頂面與該襯墊層的頂面齊平。
  7. 如申請專利範圍第1項所述之形成半導體鰭狀結構的方法，其中形成該圖案化遮罩層的步驟包含一側面圖案轉移(sidewall image transfer,SIT)製程。
  8. 如申請專利範圍第1項所述之形成半導體鰭狀結構的方法，其中各該鰭狀結構的頂面高於各該虛置鰭狀結構的頂面。
  9. 如申請專利範圍第1項所述之形成半導體鰭狀結構的方法，其中各該鰭狀結構的頂面高於該基底的頂面。
  10. 如申請專利範圍第1項所述之形成半導體鰭狀結構的方法，還包含移除該等虛置鰭狀結構。
  11. 如申請專利範圍第1項所述之形成半導體鰭狀結構的方法，其中該基底中還包含一第二區域，在形成該等溝渠前，還包含在該第二區域中形成一第二摻質井，以及在該第一區域中形成一第一摻質井，該第一摻質井的導電型不同於該第二摻質井的導電型。
  12. 如申請專利範圍第11項所述之形成半導體鰭狀結構的方法，其中該圖案化遮罩層也會設置在該第二區域的該基底上。
  13. 如申請專利範圍第11項所述之形成半導體鰭狀結構的方法，其中在形成該等鰭狀結構以及該等虛置鰭狀結構的步驟中，也會在該第二區域的基底中形成複數個第二鰭狀結構。
  14. 如申請專利範圍第13項所述之形成半導體鰭狀結構的方法，其中該等第二鰭狀結構的頂面低於位於該次區域中的該等鰭狀結構的頂面。
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