CN109786458B - 半导体器件及其形成方法 - Google Patents
半导体器件及其形成方法 Download PDFInfo
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- CN109786458B CN109786458B CN201711116553.3A CN201711116553A CN109786458B CN 109786458 B CN109786458 B CN 109786458B CN 201711116553 A CN201711116553 A CN 201711116553A CN 109786458 B CN109786458 B CN 109786458B
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- 238000000034 method Methods 0.000 title claims abstract description 107
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000002955 isolation Methods 0.000 claims abstract description 170
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- 239000010410 layer Substances 0.000 claims description 416
- 239000000463 material Substances 0.000 claims description 120
- 238000005530 etching Methods 0.000 claims description 63
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 230000001681 protective effect Effects 0.000 claims description 16
- 239000011241 protective layer Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 229910003697 SiBN Inorganic materials 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- 230000007704 transition Effects 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
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- 238000005520 cutting process Methods 0.000 description 2
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- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
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- 229910052799 carbon Inorganic materials 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
一种半导体器件及其形成方法,其中方法包括:提供半导体衬底,半导体衬底包括密集区和稀疏区;在所述半导体衬底上形成第一鳍部组、第二鳍部组和伪鳍部,第一鳍部组位于半导体衬底稀疏区上,第二鳍部组位于半导体衬底密集区上,第一鳍部组和第二鳍部组均包括若干本征鳍部,密集区本征鳍部的排列密度大于稀疏区本征鳍部的排列密度,所述伪鳍部分别位于第一鳍部组两侧、第二鳍部组两侧、以及稀疏区相邻的本征鳍部之间;在半导体衬底上形成第一隔离层,第一隔离层覆盖伪鳍部的部分侧壁和本征鳍部的部分侧壁;去除伪鳍部,在第一隔离层中形成第一槽;在所述第一槽中形成第二隔离层。所述方法提高了半导体器件的性能。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种半导体器件及其形成方法。
背景技术
MOS(金属-氧化物-半导体)晶体管,是现代集成电路中最重要的元件之一。MOS晶体管的基本结构包括:半导体衬底;位于半导体衬底表面的栅极结构,所述栅极结构包括:位于半导体衬底表面的栅介质层以及位于栅介质层表面的栅电极层;位于栅极结构两侧半导体衬底中的源漏掺杂区。
随着半导体技术的发展,传统的平面式的MOS晶体管对沟道电流的控制能力变弱,造成严重的漏电流。鳍式场效应晶体管(Fin FET)是一种新兴的多栅器件,它一般包括凸出于半导体衬底表面的鳍部,覆盖部分所述鳍部的顶部表面和侧壁的栅极结构,位于栅极结构两侧的鳍部中的源漏掺杂区。
然而,现有技术中鳍式场效应晶体管构成的半导体器件的性能仍有待提高。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法,以提高半导体器件的性能。
为解决上述问题,本发明提供一种半导体器件的形成方法,包括:提供半导体衬底,半导体衬底包括密集区和稀疏区;在所述半导体衬底上形成第一鳍部组、第二鳍部组和伪鳍部,第一鳍部组位于半导体衬底稀疏区上,第二鳍部组位于半导体衬底密集区上,第一鳍部组和第二鳍部组均包括若干本征鳍部,密集区本征鳍部的排列密度大于稀疏区本征鳍部的排列密度,所述伪鳍部分别位于第一鳍部组两侧、第二鳍部组两侧、以及稀疏区相邻的本征鳍部之间;在半导体衬底上形成第一隔离层,第一隔离层覆盖伪鳍部的部分侧壁和本征鳍部的部分侧壁;去除伪鳍部,在第一隔离层中形成第一槽;在所述第一槽中形成第二隔离层。
可选的,还包括:在形成第一隔离层之前,在所述半导体衬底上形成附加鳍部;所述本征鳍部和伪鳍部均为初始鳍部;附加鳍部和初始鳍部构成若干分立的鳍部环,在各个鳍部环中,初始鳍部相对排布,附加鳍部相对排布,附加鳍部的两端分别与相邻的初始鳍部连接;初始鳍部的排列方向垂直于初始鳍部的延伸方向,附加鳍部的排列方向平行于附加鳍部的延伸方向;所述半导体器件的形成方法还包括:形成所述第一隔离层之后,第一隔离层还覆盖附加鳍部的部分侧壁;在去除所述伪鳍部的过程中去除所述附加鳍部,在第一隔离层中形成第二槽;形成第二隔离层后,第二隔离层还位于第二槽中。
可选的,所述初始鳍部等距排列。
可选的,形成所述若干鳍部环的方法包括:在所述半导体衬底密集区和稀疏区上形成鳍部材料层;在密集区和稀疏区的鳍部材料层上形成多个分立的牺牲层;在所述牺牲层的两侧侧壁形成第一侧墙,在形成第一侧墙的过程中,在牺牲层的两侧侧壁形成第二侧墙,第二侧墙的两端分别与相邻的第一侧墙连接,第二侧墙和第一侧墙呈环状结构;形成第一侧墙和第二侧墙后,去除牺牲层;去除牺牲层后,以第一侧墙和第二侧墙为掩膜刻蚀鳍部材料层,在半导体衬底密集区和稀疏区上形成若干鳍部环;以第一侧墙和第二侧墙为掩膜刻蚀鳍部材料层后,去除第一侧墙和第二侧墙。
可选的,形成所述第一隔离层的方法包括:在所述半导体衬底、伪鳍部、第一鳍部组和第二鳍部组上形成第一隔离材料层;回刻蚀部分第一隔离材料膜,使第一隔离材料层形成所述第一隔离层。
可选的,还包括:在去除所述伪鳍部之前,在所述本征鳍部表面和第一隔离层的顶部表面形成掩膜保护层,且所述掩膜保护层暴露出伪鳍部表面;以所述掩膜保护层为掩膜刻蚀去除伪鳍部,在第一隔离层中形成第一槽;形成所述第二隔离层后,去除所述掩膜保护层。
可选的,在刻蚀去除伪鳍部的工艺中,对伪鳍部的刻蚀速率相对于对掩膜保护层的刻蚀速率之比值为100:1~1000:1。
可选的,所述掩膜保护层为单层结构;所述掩膜保护层的材料为SiN、SiCN、SiBN、TiN或TaN。
可选的,所述掩膜保护层为叠层结构;所述掩膜保护层包括第一保护层和位于第一保护层表面的第二保护层,第一保护层位于所述本征鳍部表面和第一隔离层的顶部表面,且第一保护层暴露出伪鳍部表面。
可选的,所述第一保护层的材料包括氧化硅;所述第二保护层的材料为SiN、SiCN、SiBN、TiN或TaN。
可选的,还包括:在形成所述掩膜保护层之前,在本征鳍部表面、伪鳍部表面和第一隔离层的顶部表面形成掩膜保护材料层;在掩膜保护材料层上形成平坦层,所述平坦层的整个顶部表面高于本征鳍部顶部表面的掩膜保护材料层、以及伪鳍部顶部表面的掩膜保护材料层;在平坦层表面形成底部抗反射层;在底部抗反射层表面形成图形化的光刻胶层;以所述光刻胶层为掩膜刻蚀底部抗反射层和平坦层,形成贯穿底部抗反射层和平坦层的第一开口,所述第一开口暴露出伪鳍部表面的掩膜保护材料层;去除所述第一开口底部的掩膜保护材料层,使所述第一开口暴露出伪鳍部表面,且使掩膜保护材料层形成掩膜保护层;去除第一开口底部的掩膜保护材料层后,去除光刻胶层、底部抗反射层和平坦层;去除光刻胶层、底部抗反射层和平坦层后,以掩膜保护层为掩膜刻蚀去除伪鳍部。
可选的,形成所述掩膜保护材料层的工艺包括原子层沉积工艺。
可选的,在所述第一槽中形成第二隔离层的方法包括:在所述第一槽中、以及掩膜保护层上形成第二隔离材料层;平坦化第二隔离材料层直至暴露出本征鳍部顶部表面的掩膜保护层,使第二隔离材料层形成第二隔离过度层;以所述掩膜保护层为掩膜,回刻蚀部分第二隔离过渡层以形成所述第二隔离层。
可选的,平坦化所述第二隔离材料层的工艺为化学机械研磨工艺或回刻蚀工艺。
可选的,形成所述第二隔离材料层的工艺包括流体化学气相沉积工艺。
可选的,所述第一隔离层的材料包括氧化硅;所述第二隔离层的材料包括氧化硅。
可选的,还包括:在第一隔离层和第二隔离层上形成第一栅极结构,第一栅极结构横跨所述稀疏区的本征鳍部,且覆盖稀疏区本征鳍部的部分顶部表面和部分侧壁表面;在第一隔离层和第二隔离层上形成第二栅极结构,第二栅极结构横跨所述密集区的本征鳍部,且覆盖密集区本征鳍部的部分顶部表面和部分侧壁表面。
本发明还提供一种采用上述任意一项方法形成的半导体器件。
与现有技术相比,本发明的技术方案具有以下优点:
本发明技术方案提供的半导体器件的形成方法中,形成伪鳍部,伪鳍部用于改善第一隔离层的高度均匀性。形成第一隔离层后,去除伪鳍部,在半导体衬底稀疏区和密集区上保留本征鳍部,且密集区本征鳍部的排列密度大于稀疏区本征鳍部的排列密度。之后在第一槽中形成第二隔离层,第二隔离层和第一隔离层用于构成位于本征鳍部之间的隔离结构。所述伪鳍部分别位于第一鳍部组两侧、第二鳍部组两侧以及稀疏区相邻的本征鳍部之间,因此使稀疏区相邻的本征鳍部和伪鳍部之间的距离、密集区相邻的本征鳍部之间的距离、以及密集区相邻本征鳍部和伪鳍部之间的距离差别较小。进而使得形成第一隔离层材料的源气体,在稀疏区相邻的本征鳍部和伪鳍部之间、密集区相邻的本征鳍部之间、以及密集区相邻本征鳍部和伪鳍部之间的分别较为均匀,形成第一隔离层后,稀疏区相邻的本征鳍部和伪鳍部之间的第一隔离层、密集区相邻的本征鳍部之间的第一隔离层、密集区相邻本征鳍部和伪鳍部之间的第一隔离层的高度较为一致。因此密集区和稀疏区各个本征鳍部两侧的第一隔离层的高度之差较小,满足工艺设计的要求,提高了半导体器件的性能。
进一步,在去除所述伪鳍部之前,在所述本征鳍部表面和第一隔离层的顶部表面形成掩膜保护层,且所述掩膜保护层暴露出伪鳍部表面。在刻蚀去除伪鳍部的工艺中,对伪鳍部的刻蚀速率相对于对掩膜保护层的刻蚀速率之比值较大,相应的,对掩膜保护层的损耗较小,这样掩膜保护层能够较好的保护本征鳍部两侧附近的第一隔离层顶部表面。
进一步,形成第二隔离层的方法中,掩膜保护层能够作为平坦化第二隔离材料层的停止层,保护本征鳍部的顶部表面,且掩膜保护层能够在回刻蚀部分第二隔离过渡层的过程中保护第一隔离层,避免第一隔离层受到刻蚀损伤,避免改变第一隔离层的高度。
进一步,在第一隔离层和第二隔离层上形成第一栅极结构,第一栅极结构横跨所述稀疏区的本征鳍部;在第一隔离层和第二隔离层上形成第二栅极结构,第二栅极结构横跨所述密集区的本征鳍部。由于稀疏区各个本征鳍部两侧的第一隔离层的高度之差较小,因此第一栅极结构横跨的本征鳍部两侧侧壁的高度较为一致,第一栅极结构对本征鳍部中两侧沟道的控制较为一致,降低稀疏区对应晶体管中的漏电。由于密集区各个本征鳍部两侧的第一隔离层的高度之差较小,因此第二栅极结构横跨的本征鳍部两侧侧壁的高度较为一致,第二栅极结构对本征鳍部中两侧沟道的控制较为一致,降低密集区对应晶体管中的漏电。
附图说明
图1至图3是一种半导体器件形成过程的结构示意图;
图4至图15是本发明一实施例中半导体器件形成过程的结构示意图。
具体实施方式
正如背景技术所述,现有技术形成的半导体器件的性能较差。
图1至图3是一种半导体器件形成过程的结构示意图。
参考图1,提供半导体衬底100,半导体衬底100包括稀疏区X和密集区Y;在半导体衬底100上形成若干分立的鳍部110,稀疏区X鳍部110的排列密度小于密集区Y鳍部110的排列密度。
参考图2,在半导体衬底100上形成隔离层120,隔离层120覆盖稀疏区X鳍部110的部分侧壁和密集区Y鳍部100的部分侧壁。
参考图3,在隔离层120上形成横跨稀疏区X鳍部110的第一栅极结构131;在隔离层120上形成横跨密集区Y鳍部110的第二栅极结构。
形成隔离层120的步骤包括:在半导体衬底100和鳍部110上形成隔离材料层;平坦化隔离材料层直至暴露出鳍部110顶部表面;之后,回刻蚀隔离材料层以形成隔离层120。
由于稀疏区X相邻鳍部110之间的距离小于密集区Y相邻鳍部110之间的距离,因此,基于刻蚀的负载效应,在形成隔离层120材料的过程中,稀疏区刻蚀气体的消耗大于供给引起刻蚀速率下降的程度小于密集区刻蚀气体的消耗大于供给引起刻蚀速率下降的程度。因此稀疏区X相邻鳍部110之间形成的隔离层120高度,与密集区相邻的鳍部110之间形成的隔离层120的高度差别较大。
其次,为了方便说明,稀疏区X鳍部110构成第一鳍部组,密集区Y鳍部110构成第二鳍部组。对于稀疏区X边缘的鳍部,鳍部靠近稀疏区X边缘一侧的区域相对于相邻鳍部之间的区域较大,需要刻蚀鳍部靠近稀疏区X边缘一侧隔离材料层的面积较大,相应的,鳍部靠近稀疏区X边缘一侧对刻蚀气体消耗的较多,刻蚀气体的消耗大于供给引起刻蚀速率下降的程度较大。对于密集区Y边缘的鳍部,鳍部靠近密集区Y边缘一侧的区域相对于相邻鳍部之间的区域较大,需要刻蚀鳍部靠近密集区Y边缘一侧隔离材料层的面积较大,相应的,鳍部靠近密集区Y边缘一侧对刻蚀气体消耗的较多,刻蚀气体的消耗大于供给引起刻蚀速率下降的程度较大。进而使得第一鳍部组两侧形成的隔离层120的高度相对于稀疏区X相邻鳍部之间隔离层120的高度较大,第二鳍部组两侧形成的隔离层120的高度相对于密集区Y相邻鳍部之间隔离层120的高度较大。
综上,稀疏区X边缘的鳍部两侧的隔离层120的高度之差(a-b)较大,密集区Y边缘的鳍部两侧的隔离层120的高度之差(c-d)较大。第一栅极结构横跨的鳍部两侧侧壁的高度差别较大,第二栅极结构横跨的鳍部两侧侧壁的高度差别较大,第一栅极结构和第二栅极结构对鳍部中两侧沟道的控制差别较大,导致晶体管中的漏电现象严重。
在此基础上,本发明提供一种半导体器件的形成方法,在半导体衬底上形成第一鳍部组、第二鳍部组和伪鳍部,第一鳍部组和第二鳍部组分别对应位于半导体衬底稀疏区上和半导体衬底密集区上,第一鳍部组和第二鳍部组均包括若干本征鳍部,密集区本征鳍部的排列密度大于稀疏区本征鳍部的排列密度,伪鳍部分别位于第一鳍部组两侧、第二鳍部组两侧及稀疏区相邻的本征鳍部之间;在半导体衬底上形成覆盖伪鳍部的部分侧壁和本征鳍部的部分侧壁的第一隔离层;去除伪鳍部,在第一隔离层中形成第一槽;在第一槽中形成第二隔离层。所述方法提高了半导体器件的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图4至图15是本发明一实施例中半导体器件形成过程的结构示意图。
参考图4,提供半导体衬底200,半导体衬底200包括密集区A和稀疏区B。
所述半导体衬底200可以是单晶硅、多晶硅或非晶硅。半导体衬底200也可以是硅、锗、锗化硅等半导体材料。本实施例中,半导体衬底200的材料为单晶硅。
本实施例中,半导体衬底200包括稀疏区A和密集区B。后续密集区B上本征鳍部的排列密度大于稀疏区A上本征鳍部的排列密度。
接着,在所述半导体衬底200上形成第一鳍部组、第二鳍部组和伪鳍部,第一鳍部组位于半导体衬底200稀疏区A上,第二鳍部组位于半导体衬底200密集区B上,第一鳍部组和第二鳍部组均包括若干本征鳍部,密集区本征鳍部的排列密度大于稀疏区本征鳍部的排列密度,所述伪鳍部分别位于第一鳍部组两侧、第二鳍部组两侧、以及稀疏区相邻的本征鳍部之间。
本实施例中,还包括:在所述半导体衬底200上形成附加鳍部。所述本征鳍部和伪鳍部均为初始鳍部;附加鳍部和初始鳍部构成若干分立的鳍部环,在各个鳍部环中,初始鳍部相对排布,附加鳍部相对排布,附加鳍部的两端分别与相邻的初始鳍部连接;初始鳍部的排列方向垂直于初始鳍部的延伸方向,附加鳍部的排列方向平行于附加鳍部的延伸方向。
下面具体介绍形成所述第一鳍部组、第二鳍部组、伪鳍部和附加鳍部的方法。
结合参考图5和图6,图5为在图4基础上的示意图,图6为沿图5中切割线M-M1的剖面图,在半导体衬底200密集区B和稀疏区A上形成若干分立的鳍部环,各个鳍部环包括相对的初始鳍部和相对的附加鳍部212,在各个鳍部环中,附加鳍部212的两端分别与相邻的初始鳍部连接,初始鳍部的排列方向垂直于初始鳍部的延伸方向,附加鳍部212的排列方向平行于附加鳍部212的延伸方向。
所述初始鳍部的材料为单晶硅或单晶锗硅。在其它实施例中,初始鳍部的材料为还可以为其它半导体材料。
在一个实施例中,所述初始鳍部等距排列。
本实施例中,形成所述若干鳍部环的工艺包括双重图形化工艺。具体的,形成所述若干鳍部环的方法包括:在所述半导体衬底200密集区B和稀疏区A上形成鳍部材料层(未图示);在密集区B和稀疏区A的鳍部材料层上形成多个分立的牺牲层(未图示);在所述牺牲层的两侧侧壁形成第一侧墙,在形成第一侧墙的过程中,在牺牲层的两侧侧壁形成第二侧墙,第二侧墙的两端分别与相邻的第一侧墙连接,第二侧墙和第一侧墙呈环状结构;形成第一侧墙和第二侧墙后,去除牺牲层;去除牺牲层后,以第一侧墙和第二侧墙为掩膜刻蚀鳍部材料层,在半导体衬底200密集区B和稀疏区A上形成若干鳍部环;以第一侧墙和第二侧墙为掩膜刻蚀鳍部材料层后,去除第一侧墙和第二侧墙。
所述牺牲层的材料为多晶硅或无定型碳。所述第一侧墙和第二侧墙的材料为氧化硅;或者,所述第一侧墙和第二侧墙的材料为氮化硅。
在一个实施例中,牺牲层的形状呈长方体,第一侧墙和第二侧墙呈矩形环状结构。在另一个实施例中,牺牲层的形状呈正方体,第一侧墙和第二侧墙呈方形环状结构。
若干数量的初始鳍部为本征鳍部220;若干数量的初始鳍部为伪鳍部230。
具体的,稀疏区A若干数量的初始鳍部为稀疏区A的本征鳍部220并组成第一鳍部组;密集区B若干数量的初始鳍部为密集区B的本征鳍部220并组成第二鳍部组;稀疏区A和密集区B若干数量的初始鳍部为伪鳍部230。
所述密集区B本征鳍部220的排列密度大于稀疏区A本征鳍部220的排列密度,所述伪鳍部230位于第一鳍部组两侧、第二鳍部组两侧、以及稀疏区A相邻的本征鳍部220之间。
所述稀疏区A相邻的本征鳍部220之间伪鳍部230的数量为一个或多个。本实施中,密集区B相邻的本征鳍部220之间没有伪鳍部230。
本实施例中,所述伪鳍部230分别位于第一鳍部组两侧、第二鳍部组两侧、以及稀疏区A相邻的本征鳍部220之间。
结合参考图7和图8,图7为在图5基础上的示意图,图8为在图6基础上的示意图,且图8为沿图7中切割线M-M1的剖面图,在半导体衬底200上形成第一隔离层240,第一隔离层240覆盖伪鳍部230的部分侧壁和本征鳍部220的部分侧壁。
所述第一隔离层240的材料包括氧化硅。
形成所述第一隔离层240的方法包括:在所述半导体衬底200、伪鳍部230、第一鳍部组和第二鳍部组上形成第一隔离材料层(未图示);回刻蚀部分第一隔离材料膜,使第一隔离材料层形成所述第一隔离层240。
具体的,第一隔离材料层还位于附加鳍部上;形成第一隔离层240后,第一隔离层240还覆盖附加鳍部212的部分侧壁。
本实施例中,还包括:在所述本征鳍部220表面和第一隔离层240的顶部表面形成掩膜保护层,且所述掩膜保护层暴露出伪鳍部230表面。
所述伪鳍部分别位于第一鳍部组两侧、第二鳍部组两侧以及稀疏区相邻的本征鳍部之间,因此使稀疏区相邻的本征鳍部和伪鳍部之间的距离、密集区相邻的本征鳍部之间的距离、以及密集区相邻本征鳍部和伪鳍部之间的距离差别较小。进而使得形成第一隔离层材料的源气体,在稀疏区相邻的本征鳍部和伪鳍部之间、密集区相邻的本征鳍部之间、以及密集区相邻本征鳍部和伪鳍部之间的分别较为均匀,形成第一隔离层后,稀疏区相邻的本征鳍部和伪鳍部之间的第一隔离层、密集区相邻的本征鳍部之间的第一隔离层、密集区相邻本征鳍部和伪鳍部之间的第一隔离层的高度较为一致。因此密集区和稀疏区各个本征鳍部两侧的第一隔离层的高度之差较小,满足工艺设计的要求。
需要说明的是,第一隔离层240的高度指的是在垂直于半导体衬底200表面方向上的尺寸。
其次,稀疏区相邻的本征鳍部和伪鳍部之间的距离、密集区相邻的本征鳍部之间的距离、以及密集区相邻本征鳍部和伪鳍部之间的距离较为一致。为了方便说明,将刻蚀鳍部材料层形成本征鳍部和伪鳍部的工艺称为鳍部刻蚀工艺。在稀疏区相邻的本征鳍部和伪鳍部之间刻蚀气体的消耗,与密集区相邻的本征鳍部之间、以及密集区相邻本征鳍部和伪鳍部之间刻蚀气体的消耗程度较为一致,稀疏区相邻的本征鳍部和伪鳍部之间、密集区相邻的本征鳍部之间、以及密集区相邻本征鳍部和伪鳍部之间的负载效应的程度较为一致。因此使得稀疏区和密集区的本征鳍部的宽度差异性较小。
需要说明的是,尽管第一鳍部组和第二鳍部组的两侧的伪鳍部的宽度与本征鳍部的宽度差异较大,但是后续伪鳍部被去除,仅保留本征鳍部,本征鳍部为工艺中有效的鳍部。
接着,去除伪鳍部230,在第一隔离层240中形成第一槽。
本实施例中,还包括:在去除所述伪鳍部230的过程中去除所述附加鳍部212,在第一隔离层240中形成第二槽。
本实施例中,还包括:在去除所述伪鳍部230之前,在所述本征鳍部220表面和第一隔离层240的顶部表面形成掩膜保护层,且所述掩膜保护层暴露出伪鳍部230表面;以所述掩膜保护层为掩膜刻蚀去除伪鳍部230,在第一隔离层240中形成第一槽。
参考图9,图9为在图8基础上的示意图,在所述本征鳍部220表面、伪鳍部230表面和第一隔离层240的顶部表面形成掩膜保护材料层250;在所述掩膜保护材料层250上形成平坦层260,所述平坦层260的整个顶部表面高于本征鳍部220顶部表面的掩膜保护材料层250、以及伪鳍部230顶部表面的掩膜保护材料层250;在所述平坦层260表面形成底部抗反射层270;在所述底部抗反射层270表面形成图形化的光刻胶层280。
所述掩膜保护材料层250还位于附加鳍部212表面。所述平坦层260的顶部表面还高于附加鳍部212顶部表面的掩膜保护材料层250。
本实施例中,所述掩膜保护材料层250为单层结构,所述掩膜保护材料层250的材料为SiN、SiCN、SiBN、TiN或TaN。
在其它实施例中,掩膜保护材料层为叠层结构,相应的,掩膜保护材料层包括第一保护材料层和位于第一保护材料层表面的第二保护材料层。第一保护材料层位于本征鳍部表面、伪鳍部表面、附加鳍部表面和第一隔离层的顶部表面。第一保护材料层的材料包括氧化硅;第二保护材料层的材料为SiN、SiCN、SiBN、TiN或TaN。
形成所述掩膜保护材料层250的工艺为沉积工艺。
形成第一保护材料层的工艺还包括氧化工艺。
若直接在本征鳍部220表面、伪鳍部230表面和第一隔离层240的顶部表面形成第二保护材料层,第二保护材料层对本征鳍部220的应力较大,且第二保护材料层与本征鳍部220之间的粘附性较差。第一保护材料层用于缓冲第二保护材料层对本征鳍部220的应力,且提高第二保护材料层和本征鳍部220之间的结合力。
本实施例中,形成所述掩膜保护材料层250的工艺为原子层沉积工艺。好处包括:使掩膜保护材料层250的厚度均匀性较好,避免本征鳍部220侧壁表面的掩膜保护材料层250厚度小于本征鳍部220顶部表面的掩膜保护材料层250厚度,提高掩膜保护材料层250对本征鳍部220侧壁表面的保护能力。
所述平坦层260的材料包括含碳有机聚合物。
所述图形化的光刻胶层280用于定义出第一槽和第二槽的位置。
参考图10,以所述光刻胶层280为掩膜刻蚀底部抗反射层270和平坦层260,形成贯穿所述底部抗反射层270和平坦层260的第一开口261和第二开口,第一开口261暴露出伪鳍部230表面的掩膜保护材料层250,第二开口暴露出附加鳍部212表面的掩膜保护材料层250。
参考图11,去除第一开口261底部的掩膜保护材料层250,使所述第一开口261暴露出伪鳍部230表面,在去除第一开口261底部的掩膜保护材料层250的过程中,去除第二开口底部的掩膜保护材料层250,使第二开口暴露出附加鳍部212表面,且使掩膜保护材料层250形成掩膜保护层251。
所述掩膜保护层251的厚度为2nm~10nm。若掩膜保护层251的厚度过小,导致掩膜保护层251的掩膜作用较差;若掩膜保护层251的厚度过大,导致本征鳍部220侧壁的掩膜保护层251和伪鳍部230侧壁的掩膜保护层251之间的距离较小,较难刻蚀去除伪鳍部230侧壁底部的掩膜保护材料层250。
本实施例中,所述掩膜保护层251为单层结构;所述掩膜保护层251的材料为SiN、SiCN、SiBN、TiN或TaN。
在其它实施例中,所述掩膜保护层为叠层结构,所述掩膜保护层包括第一保护层和位于第一保护层表面的第二保护层,第一保护层位于所述本征鳍部表面和第一隔离层的顶部表面,且第一保护层暴露出伪鳍部表面。第一保护层对应第一保护材料层,第二保护层对应第二保护材料层。
所述第一保护层的材料包括氧化硅;所述第二保护层的材料为SiN、SiCN、SiBN、TiN或TaN。
参考图12,去除第一开口261和第二开口底部的掩膜保护材料层250后,去除所述光刻胶层280、底部抗反射层270和平坦层260。
参考图13,去除所述光刻胶层280、底部抗反射层270和平坦层260后,以所述掩膜保护层251为掩膜刻蚀去除伪鳍部230,在第一隔离层240中形成第一槽291。
在去除伪鳍部230的过程中,以所述掩膜保护层251为掩膜刻蚀去除附加鳍部212,在第一隔离层240中形成第二槽。
由于以掩膜保护层251为掩膜刻蚀去除伪鳍部230和附加鳍部212,而掩膜保护层251为硬掩膜层,因此使得在刻蚀去除伪鳍部230和附加鳍部212的过程中,对伪鳍部230的刻蚀速率相对于对掩膜保护层251的刻蚀速率之比值较大,对附加鳍部212的刻蚀速率相对于对掩膜保护层251的刻蚀速率之比值较大,相应的,对掩膜保护层251的损耗较小,这样掩膜保护层251能够较好的保护本征鳍部220两侧附近的第一隔离层240顶部表面。具体的,本实施例中,在刻蚀去除伪鳍部230和附加鳍部212的过程中,对伪鳍部230的刻蚀速率相对于对掩膜保护层251的刻蚀速率之比值为100:1~1000:1,对附加鳍部212的刻蚀速率相对于对掩膜保护层251的刻蚀速率之比值为100:1~1000:1。
在其它实施例中,不形成掩膜保护层。具体的,在本征鳍部、伪鳍部、附加鳍部和第一隔离层上形成平坦层,平坦层的整个顶部表面高于本征鳍部顶部表面、伪鳍部顶部表面和附加鳍部顶部表面;在所述平坦层表面形成底部抗反射层;在所述底部抗反射层表面形成图形化的光刻胶层;以光刻胶层为掩膜刻蚀底部抗反射层和平坦层,形成贯穿底部抗反射层和平坦层的第一开口和第二开口,第一开口暴露出伪鳍部表面,第二开口暴露出附加鳍部表面;以光刻胶层、底部抗反射层和平坦层为掩膜,刻蚀去除伪鳍部,在第一隔离层中形成第一槽,刻蚀去除附加鳍部,在第一隔离层中形成第二槽。
参考图14,在所述第一槽291中形成第二隔离层300。
所述第二隔离层300的材料包括氧化硅。
具体的,在第一槽291和第二槽中形成第二隔离层300。
形成第二隔离层300的方法包括:在所述第一槽291中、第二槽中、以及掩膜保护层251上形成第二隔离材料层;平坦化第二隔离材料层直至暴露出本征鳍部220顶部表面的掩膜保护层251,使第二隔离材料层形成第二隔离过度层;以所述掩膜保护层251为掩膜,回刻蚀部分第二隔离过渡层以形成所述第二隔离层300。
形成所述第二隔离材料层的工艺为沉积工艺,如流体化学气相沉积工艺,好处包括:填充性较好。
本实施例中,采用流体化学气相沉积工艺形成第二隔离材料层,在形成第二隔离材料层的过程中,掩膜保护层251保护本征鳍部220表面,避免流体化学气相沉积工艺中的氧化过程消耗本征鳍部220,因此避免流体化学气相沉积工艺减小本征鳍部220的宽度。
平坦化所述第二隔离材料层的工艺为化学机械研磨工艺或回刻蚀工艺。平坦化所述第二隔离材料层的工艺以本征鳍部220顶部表面的掩膜保护层251为停止层。且掩膜保护层251能够在回刻蚀部分第二隔离过渡层的过程中保护第一隔离层240,避免第一隔离层240受到刻蚀损伤,避免改变第一隔离层240的高度。
参考图15,形成所述第二隔离层300后,去除所述掩膜保护层251。
去除掩膜保护层251的工艺为干刻工艺或湿刻工艺。
本实施例中,还包括:在第一隔离层240和第二隔离层300上形成第一栅极结构,第一栅极结构横跨所述稀疏区A的本征鳍部220,且覆盖稀疏区A本征鳍部220的部分顶部表面和部分侧壁表面;在第一隔离层240和第二隔离层300上形成第二栅极结构,第二栅极结构横跨所述密集区B的本征鳍部220,且覆盖密集区B本征鳍部220的部分顶部表面和部分侧壁表面。
由于稀疏区A各个本征鳍部220两侧的第一隔离层240的高度之差较小,因此第一栅极结构横跨的本征鳍部220两侧侧壁的高度较为一致,第一栅极结构对本征鳍部220中两侧沟道的控制较为一致,降低稀疏区A对应晶体管中的漏电。由于密集区B各个本征鳍部220两侧的第一隔离层240的高度之差较小,因此第二栅极结构横跨的本征鳍部220两侧侧壁的高度较为一致,第二栅极结构对本征鳍部220中两侧沟道的控制较为一致,降低密集区B对应晶体管中的漏电。
相应的,本实施例还提供一种采用上述方法形成的半导体器件。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (17)
1.一种半导体器件的形成方法,其特征在于,包括:
提供半导体衬底,半导体衬底包括密集区和稀疏区;
在所述半导体衬底上形成第一鳍部组、第二鳍部组和伪鳍部,第一鳍部组位于半导体衬底稀疏区上,第二鳍部组位于半导体衬底密集区上,第一鳍部组和第二鳍部组均包括若干本征鳍部,密集区本征鳍部的排列密度大于稀疏区本征鳍部的排列密度,所述伪鳍部分别位于第一鳍部组两侧、第二鳍部组两侧、以及稀疏区相邻的本征鳍部之间;
在半导体衬底上形成第一隔离层,第一隔离层覆盖伪鳍部的部分侧壁和本征鳍部的部分侧壁;
去除伪鳍部,在第一隔离层中形成第一槽;
在所述第一槽中形成第二隔离层;
在第一隔离层和第二隔离层上形成第一栅极结构,第一栅极结构横跨所述稀疏区的本征鳍部,且覆盖稀疏区本征鳍部的部分顶部表面和部分侧壁表面;在第一隔离层和第二隔离层上形成第二栅极结构,第二栅极结构横跨所述密集区的本征鳍部,且覆盖密集区本征鳍部的部分顶部表面和部分侧壁表面。
2.根据权利要求1所述的半导体器件的形成方法,其特征在于,还包括:在形成所述第一隔离层之前,在所述半导体衬底上形成附加鳍部;所述本征鳍部和伪鳍部均为初始鳍部;附加鳍部和初始鳍部构成若干分立的鳍部环,在各个鳍部环中,初始鳍部相对排布,附加鳍部相对排布,附加鳍部的两端分别与相邻的初始鳍部连接;初始鳍部的排列方向垂直于初始鳍部的延伸方向,附加鳍部的排列方向平行于附加鳍部的延伸方向;
所述半导体器件的形成方法还包括:形成所述第一隔离层之后,第一隔离层还覆盖附加鳍部的部分侧壁;在去除所述伪鳍部的过程中去除所述附加鳍部,在第一隔离层中形成第二槽;形成第二隔离层后,第二隔离层还位于第二槽中。
3.根据权利要求2所述的半导体器件的形成方法,其特征在于,所述初始鳍部等距排列。
4.根据权利要求2所述的半导体器件的形成方法,其特征在于,形成所述若干鳍部环的方法包括:在所述半导体衬底密集区和稀疏区上形成鳍部材料层;在密集区和稀疏区的鳍部材料层上形成多个分立的牺牲层;在所述牺牲层的两侧侧壁形成第一侧墙,在形成第一侧墙的过程中,在牺牲层的两侧侧壁形成第二侧墙,第二侧墙的两端分别与相邻的第一侧墙连接,第二侧墙和第一侧墙呈环状结构;形成第一侧墙和第二侧墙后,去除牺牲层;去除牺牲层后,以第一侧墙和第二侧墙为掩膜刻蚀鳍部材料层,在半导体衬底密集区和稀疏区上形成若干鳍部环;以第一侧墙和第二侧墙为掩膜刻蚀鳍部材料层后,去除第一侧墙和第二侧墙。
5.根据权利要求1所述的半导体器件的形成方法,其特征在于,形成所述第一隔离层的方法包括:在所述半导体衬底、伪鳍部、第一鳍部组和第二鳍部组上形成第一隔离材料层;回刻蚀部分第一隔离材料膜,使第一隔离材料层形成所述第一隔离层。
6.根据权利要求1所述的半导体器件的形成方法,其特征在于,还包括:在去除所述伪鳍部之前,在所述本征鳍部表面和第一隔离层的顶部表面形成掩膜保护层,且所述掩膜保护层暴露出伪鳍部表面;以所述掩膜保护层为掩膜刻蚀去除伪鳍部,在第一隔离层中形成第一槽;形成所述第二隔离层后,去除所述掩膜保护层。
7.根据权利要求6所述的半导体器件的形成方法,其特征在于,在刻蚀去除伪鳍部的工艺中,对伪鳍部的刻蚀速率相对于对掩膜保护层的刻蚀速率之比值为100:1~1000:1。
8.根据权利要求6所述的半导体器件的形成方法,其特征在于,所述掩膜保护层为单层结构;所述掩膜保护层的材料为SiN、SiCN、SiBN、TiN或TaN。
9.根据权利要求6所述的半导体器件的形成方法,其特征在于,所述掩膜保护层为叠层结构;所述掩膜保护层包括第一保护层和位于第一保护层表面的第二保护层,第一保护层位于所述本征鳍部表面和第一隔离层的顶部表面,且第一保护层暴露出伪鳍部表面。
10.根据权利要求9所述的半导体器件的形成方法,其特征在于,所述第一保护层的材料包括氧化硅;所述第二保护层的材料为SiN、SiCN、SiBN、TiN或TaN。
11.根据权利要求6所述的半导体器件的形成方法,其特征在于,还包括:在形成所述掩膜保护层之前,在本征鳍部表面、伪鳍部表面和第一隔离层的顶部表面形成掩膜保护材料层;在掩膜保护材料层上形成平坦层,所述平坦层的整个顶部表面高于本征鳍部顶部表面的掩膜保护材料层、以及伪鳍部顶部表面的掩膜保护材料层;在平坦层表面形成底部抗反射层;在底部抗反射层表面形成图形化的光刻胶层;以所述光刻胶层为掩膜刻蚀底部抗反射层和平坦层,形成贯穿底部抗反射层和平坦层的第一开口,所述第一开口暴露出伪鳍部表面的掩膜保护材料层;去除所述第一开口底部的掩膜保护材料层,使所述第一开口暴露出伪鳍部表面,且使掩膜保护材料层形成掩膜保护层;去除第一开口底部的掩膜保护材料层后,去除光刻胶层、底部抗反射层和平坦层;去除光刻胶层、底部抗反射层和平坦层后,以掩膜保护层为掩膜刻蚀去除伪鳍部。
12.根据权利要求11所述的半导体器件的形成方法,其特征在于,形成所述掩膜保护材料层的工艺包括原子层沉积工艺。
13.根据权利要求6所述的半导体器件的形成方法,其特征在于,在所述第一槽中形成第二隔离层的方法包括:在所述第一槽中、以及掩膜保护层上形成第二隔离材料层;平坦化第二隔离材料层直至暴露出本征鳍部顶部表面的掩膜保护层,使第二隔离材料层形成第二隔离过度层;以所述掩膜保护层为掩膜,回刻蚀部分第二隔离过渡层以形成所述第二隔离层。
14.根据权利要求13所述的半导体器件的形成方法,其特征在于,平坦化所述第二隔离材料层的工艺为化学机械研磨工艺或回刻蚀工艺。
15.根据权利要求13所述的半导体器件的形成方法,其特征在于,形成所述第二隔离材料层的工艺包括流体化学气相沉积工艺。
16.根据权利要求1所述的半导体器件的形成方法,其特征在于,所述第一隔离层的材料包括氧化硅;所述第二隔离层的材料包括氧化硅。
17.种根据权利要求1至16任意一项方法形成的半导体器件。
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