TWI699885B - 半導體結構與其製作方法 - Google Patents

半導體結構與其製作方法 Download PDF

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TWI699885B
TWI699885B TW105108724A TW105108724A TWI699885B TW I699885 B TWI699885 B TW I699885B TW 105108724 A TW105108724 A TW 105108724A TW 105108724 A TW105108724 A TW 105108724A TW I699885 B TWI699885 B TW I699885B
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semiconductor layer
semiconductor
fin
region
layer
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TW105108724A
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TW201735352A (zh
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童宇誠
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聯華電子股份有限公司
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Priority to US15/152,570 priority patent/US20170278928A1/en
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Priority to US16/022,737 priority patent/US10580864B2/en
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Abstract

本發明提供一種半導體結構，包含一基底、一第一半導體層、複數個第一次溝渠、複數個絕緣結構以及一第一上半導體層。基底，具有一第一區域，第一區域介於一淺溝渠隔離之間。第一半導體層，設置在第一區域中，複數個第一次溝渠設置在第一半導體層中。絕緣結構設置在第一半導體層上。第一上半導體結構形成複數個第一鰭狀結構，埋入在第一次溝渠中，第一鰭狀結構與該等絕緣結構交錯排列，且第一鰭狀結構突出於該絕緣結構上。

Description

半導體結構與其製作方法
本發明是關於一種半導體結構與其製作方法，特別來說，是關於一種具有晶格結構良好之鰭狀結構的半導體結構與其製作方法。
近年來，隨著各種消費性電子產品不斷的朝小型化發展，半導體元件設計的尺寸亦不斷縮小，以符合高積集度、高效能和低耗電之潮流以及產品需求。
然而，隨著電子產品的小型化發展，現有的平面電晶體(planar transistor)已經無法滿足產品的需求。因此，目前發展出一種非平面電晶體(non-planar)之鰭狀電晶體(Fin-FET)技術，其係具有立體的閘極通道(channel)結構。鰭狀場效電晶體元件的製程能與傳統的邏輯元件製程整合，因此具有相當的製程相容性，且由於鰭狀結構之立體形狀增加了閘極與矽的接觸面積，因此可增加閘極對於通道區域電荷的控制，以降低小尺寸元件帶來的汲極引發的能帶降低(Drain Induced Barrier Lowering,DIBL)效應以及短通道效應(short channel effect)。現有的鰭狀電晶體也持續改良，以朝更小尺寸的方向邁進。
本發明於是提供了一種半導體結構，具有較佳晶格結構之鰭狀結構。
根據本發明一種實施例，本發明是提供一種半導體結構，包含一基底、一第一半導體層、複數個第一次溝渠、複數個絕緣結構以及一第一上半導體層。基底，具有一第一區域，第一區域介於一淺溝渠隔離之間。第一半導體層，設置在第一區域中，複數個第一次溝渠設置在第一半導體層中。絕緣結構設置在第一半導體層上。第一上半導體層形成複數個第一鰭狀結構，其埋入(embedded)在第一次溝渠中，第一鰭狀結構與該等絕緣結構交錯排列，且第一鰭狀結構突出於該絕緣結構上。
根據本發明另外一種實施例，本發明提供一種製作半導體結構的方法，首先提供一基底，該基底具有一第一區域介於一淺溝渠隔離之間；移除該第一區域中之該基底，以形成一第一溝渠；形成一第一半導體層於該第一溝渠中。接著形成一圖案化遮罩層於該第一半導體層上，以該圖案化遮罩層作為遮罩，圖案化該第一半導體層，以在該第一半導體層中形成複數個第一次溝渠。 後續，在該等第一次溝渠中形成複數個第一鰭狀結構。最後移除該圖案化遮罩層至一預定高度，使該圖案化遮罩層形成複數個絕緣結構，該複數個絕緣結構與該等第一鰭狀結構交替排列。
本發明提供之一種半導體結構以及形成半導體結構的方法，其特徵在於具有第一半導體層作為緩衝層，所形成之鰭狀結構可以具有較佳的晶格結構，且不需要額外的鰭切步驟。
300:基底
302:淺溝渠隔離
304:遮罩層
304’:圖案化遮罩層
304”:絕緣結構
306:中柱層
308:側壁子
310:虛置鰭狀結構
312:層間介電層
314:凹槽
400:第一區域
402:第一凹槽
408:第一上半導體層
408’:第一鰭狀結構
410:第一中半導體層
412:第一閘極介電層
414:第一金屬閘極
500:第二區域
502:第二凹槽
504:第二半導體層
506:第二次溝渠
508:第二上半導體層
508’:第二鰭狀結構
510:第二中半導體層
404:第一半導體層
406:第一次溝渠
512:第二閘極介電層
514:第二金屬閘極
第1A圖、第1B圖、第2圖、第3圖、第4A圖、第4B圖、第5A圖、第5B圖、第6A圖、第6B圖、第7A圖、第7B圖、第8A圖、第8B圖、第9A圖、第9B圖、第10A圖、第10B圖、第11A圖與第11B圖，所繪示為本發明一種製作半導體結構的步驟示意圖。
第12圖所繪示為本發明另一實施例中半導體結構的示意圖。
第13圖所繪示為本發明一個實施例中半導體結構進行金屬閘極置換製程之步驟示意圖。
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之數個較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。
請參考第1A圖、第1B圖、第2圖、第3A圖、第3B圖、第4A圖、第4B圖、第5A圖、第5B圖、第6A圖、第6B圖、第7A圖、第7B圖、第8A圖、第8B圖、第9A圖、第9B圖、第10A圖、第10B圖、第11A圖與第11B圖，所繪示為本發明一種製作半導體結構的步驟示意圖，其中第1A圖、第3A圖、第4A圖、第5A圖、第6A圖、第7A圖、第8A圖、第9A圖、第10A圖與第11A圖是剖面圖，而第1B圖、第3B圖、第4B圖、第5B圖、第6B圖、第7B圖、第8B圖、第9B圖、第10B圖與第11B圖是平面圖。
首先請參考第1A圖與第1B圖，第1A圖係根據第1B圖之切線AA’所繪 製，提供一基底300，其係用來在其上形成所需之元件或電路，較佳具有含矽材質，例如是矽、單晶矽(single crystal silicon)、單晶矽鍺(single crystal silicon germanium)、非晶矽(amorphous silicon)或是上述的組合。於另一實施例中，基底300也可以包含其他半導體材質，例如是鍺或III/V族的複合半導體材料，如鍺砷等。於另一實施例中，基底300也可以包含其他介電材料，例如是矽覆絕緣基底(silicon on insulator,SOI)。基底300上具有一淺溝渠隔離(shallow trench isolation,STI)302，淺溝渠隔離302所包圍的地方可以定義出不同的主動區(active region)。 在本實施例中，如第1A圖與第1B圖所示，淺溝渠隔離302各自包圍一第一區域400以及一第二區域500。在本實施例中，第一區域400與第二區域500為兩直接相鄰之主動區，但在其他實施例中，第一區域400與第二區域500也可以不直接相鄰，而可以具有其他的主動區域或被動區域。於一實施例中，第一區域400為一N型電晶體區域，第二區域500為一P型電晶體區域。而在其他實施例中，第一區域400與第二區域500的導電型也可以相同。
如第2圖之剖面圖所示，將第一區域400以及第二區域500中分別形成一第一溝渠402與一第二溝渠502。於本發明較佳實施例中，第一溝渠402之輪廓完全對應第一區域400，第二溝渠502之輪廓完全對應第二區域500，即第一溝渠402與第二溝渠502之側壁即為淺溝渠隔離302。第一溝渠402與第二溝渠502之深度不大於淺溝渠隔離302之深度。於一實施例中，第一溝渠402與第二溝渠502的深度相同，但於其他實施例中，視後續形成磊晶材料之電性設計，第一溝渠402與第二溝渠502的深度也可以不同。
如第3圖所示，在第一溝渠402中形成一第一半導體層404，在第二溝渠502中形成一第二半導體層504。第一半導體層404與第二半導體層504較佳完 全填滿第一溝渠402以及第二溝渠502。於一實施例中，第一半導體層404與第二半導體層504是以選擇性磊晶成長(selective epitaxial growth,SEG)製程形成，其可以透過同一道磊晶製程或是分開不同的磊晶製程形成，第一半導體層404與第二半導體層504可以具有相同材質也可以具有不同材質。在形成第一半導體層404與第二半導體層504後，還可選擇型地進行一平坦化製程，使第一半導體層404與第二半導體層504之頂面與淺溝渠隔離302之頂面齊平。
如第4A圖與第4B圖所示，在基底300依序形成一遮罩層304以及複數個中柱層306。遮罩層304全面地形成在基底300上，其材料可以包含任何適合作為後續蝕刻製程的遮罩材料，且較佳是具有電性隔離功能的介電層，例如是氮化矽(SiN)、氮氧化矽(SiON)、碳化矽(SiC)或由應用材料公司提供之進階圖案化薄膜(advanced pattern film,APF)，但並不以此為限。中柱層306材料例如是多晶矽(poly-silicon)或非晶矽(amorphous silicon)，如第4B圖之平面圖所示，中柱層306例如是長條狀圖案，彼此平行且沿著同一方向S延伸。於一較佳實施例中，第一區域400會被至少一個中柱層306跨越，第二區域500會被至少一個中柱層306跨越，且較佳者中柱層306上下突出於第一區域400。此外，且在第一區域400以及第二區域500之間的淺溝渠隔離302區域中至少會設置有一個中柱層306。
如第5A圖與第5B圖所示，在每個中柱層306的側壁上形成一側壁子308。形成側壁子308的方法例如先在基底300上全面形成一側壁子材料層(圖未示)，側壁子材料層會共形地(conformally)形成在中柱層306側壁與頂壁。進行一非等向性蝕刻製程，暴露出中柱層306的頂面後，使側壁子308僅形成在中柱層306的側壁。側壁子306的材料較佳和遮罩層304具有蝕刻選擇比，於一實施例中，側壁子306的材料例如是氧化矽、氮化矽、高溫氧化矽層(high temperature oxide,HTO)或包含六氯二矽烷(hexachlorodisilane,Si2Cl6)形成的氮化矽(HCD-SiN)，但並不以此為限。如第5B圖的上視圖，側壁子308包圍並環繞中柱層306，值得注意的是，在第一區域400與第二區域600中間，側壁子308會恰好覆蓋第一區域400的邊界與第二區域500的邊界。
接著如第6A圖與第6B圖所示，移除中柱層306，暴露出下方的遮罩層304。於一實施例中，若中柱層306包含多晶矽，則此移除步驟可以是一乾蝕刻步驟及/或溼蝕刻步驟。乾蝕刻步驟例如是使用一含包含溴化氫(HBr)、氮氣(N2)與三氟化氮(NF3)的蝕刻氣體，或三氯化硼(BCl3)氣體，溼蝕刻步驟例如是使用氫氧化四甲基銨(tetramethyl ammonium hydroxide,TMAH)溶液。
如第7A圖與第7B圖所示，以側壁子306為遮罩層，圖案化下方的遮罩層304，將側壁子308的圖案轉移到形成的一圖案化遮罩層304’中，圖案化遮罩層304’也具有長環的圖案。前述第4A圖到第7A圖的實施例是以側壁圖案轉移(sidewall image transfer,SIT)來形成圖案化遮罩層304’，而本領域具有通常知識者也可了解，圖案化遮罩層304’亦可以以其他方式形成，例如直接以具有長條狀之光阻來蝕刻而形成。
如第8A圖與第8B圖所示，以圖案化遮罩層306’為遮罩，圖案化第一半導體層404以及第二半導體層504，以分明在第一半導體層404中形成複數個第一次溝渠406以及在第二半導體層504中形成複數個第二次溝渠506。於本發明較佳實施例中，藉由調整中柱層306之位置與寬度、側壁子308之寬度，可以形成大小相同之第一次溝渠406或第二次溝渠506。請再次參考第6A圖與第6B圖，由於側壁子308會形成在第一區域400與第二區域500的邊界上，故圖案化製程中輪 廓不會被淺溝渠隔離302所影響，以保持第一次溝渠406與第二次溝渠506的輪廓可以完成且大小一致。於本發明另一實施例中，亦可能使第一區域400中的第一次溝渠406與第二區域500中的第二次溝渠506不同的寬度或深度不同。如第8A圖所示，第二次溝渠506的深度大於第一次溝渠406的深度。
如第9A圖與第9B圖所示，進行至少一選擇性磊晶成長(selective epitaxial growth,SEG)製程，以在第一半導體層404上形成一第一上半導體層408，以及在第二半導體層504上形成一第二上半導體層508。第一上半導體層408完全填滿第一次溝渠406，第二上半導體層508完全填滿第二次溝渠506，兩者較佳向上超出基底300，更進一步會突出圖案化遮罩層304’的頂面上。於一實施例中，第一上半導體層408與第二上半導體層508可以透過相同或不同的磊晶製程形成，故兩者的材料可以相同也可以不同。
如第10A圖與第10B圖所示，進行一平坦化製程，以將第一上半導體層408以及該第二上半導體層508的頂面與該圖案化遮罩層304’的頂面齊平。於一實施例中，在平坦化製程前，可選擇性的將一介電材料層例如二氧化矽填入沒有磊晶成長之處，藉以增加平坦化製程的可靠性，例如填入在第一區域400與第二區域500之間，而在淺溝渠隔離302上形成一虛置鰭狀結構310。
如第11A圖與第11B圖所示，進行一回蝕刻製程，移除部分的圖案化遮罩層304’至一預定高度，使該圖案化遮罩層304’形成複數個絕緣結構304”，而第一上半導體層408形成複數個第一鰭狀結構408’，第二上半導體層508形成複數個第二鰭狀結構508’。如此一來，即可完成本發明所述之半導體結構。如第11A圖與第11B圖所示，本發明之半導體結構，若以第一區域400來看，具有一基底 300、一淺溝渠隔離302、一第一半導體層408、複數個第一次溝渠406及複數個第一鰭狀結構408’。第一半導體層408被淺溝渠隔離302包圍，且其頂面與淺溝渠隔離302的頂面齊平。第一次溝渠406設置在第一半導體層中404，絕緣結構304設置在第一半導體層404上，第一上半導體層408形成之第一鰭狀結構408’埋入在第一次溝渠406，與絕緣結構302交替設置，且會突出於絕緣結構302之上。第二區域500具有類似於第一區域500的元件，於一實施例中，第二半導體層508的材料與第一半導體層408可以不同。於一實施例中，第二鰭狀結構508’的材料、寬度、與深度可以和第一鰭狀結構508亦可以不同。於一實施例中，虛置鰭狀結構310與第一鰭狀結構508等高；於另一實施例中，當虛置鰭狀結構310之材料與圖案化遮罩層304’之材料蝕刻選擇比較小時，進行第11A圖與第11B圖之回蝕刻製程時，也會移除部分的虛置鰭狀結構310，使虛置鰭狀結構310略低於第一鰭狀結構408’。
本發明其中一個優點在於，在第11B圖之剖面圖中，第一鰭狀結構408可以自動對準地設置在第一區域400之第一次溝渠406中，而不會位在第一區域400以外之處，因此不需要習知使用側壁圖案轉移製程需要把長環切開(fin cut)的額外步驟，而又可以具有側壁圖案轉移製程關鍵尺寸較小的優點。
由於本發明是使用磊晶成長製程來形成第一半導體層404與第二半導體層504，以及第一上半導體層408(即後來的第一鰭狀結構408’)與第二上半導體層508(即後來的第二鰭狀結構508’)，第一半導體層404與第二半導體層504可作為晶格成長的緩衝層，其中可能具有為數不多的差排(dislocation)產生，但可使第一鰭狀結構408’與第二鰭狀結構508’可以具有較好的晶形，而沒有差排。因此在一實施例中，第一半導體層404與第一上半導體層408之第一鰭狀結構408’ 可具有不同的晶格係數(lattice mismatch)；於另一實施例中，第一半導體層404、第一上半導體層408之第一鰭狀結構408’與基底300，三者具有不同的晶格係數。 於一實施例中，若第一區域400為N形半導體區域，第一半導體層404、第二半導體層504、第一鰭狀結構408’與第二鰭狀結構508’的材質可以是矽、矽鍺、鍺或鍺砷等IV族元素，且為了增加其鰭狀結構通道(channel)的應力，第一半導體層404或第二半導體層504可以摻入不同原子大小的IV族元素，例如摻入碳(C)或錫(Sn)等，且其濃度可以視產品不同而具有之梯度。請參考第12圖，所繪示為本發明另一實施例中半導體結構的示意圖。本實施例的半導體結構還可進一步具有一第一中半導體層410設置在第一半導體層404與絕緣結構304”之間，一第二中半導體層510設置在第二半導體504與絕緣結構304”之間，且第一中半導體層410的頂面、第二中半導體層510的頂面與淺溝渠隔離302齊平。第一中半導體層410與第二中半導體層510可以在第一半導體層404與第二半導體層504形成後(如第4A圖與第4B圖)，移除上部分的第一半導體層404與第二半導體層504，後續再以磊晶成長方式製成。透過增加的第一中半導體層410與第二中半導體層510，可以進一步增加第一鰭狀結構408’與第二鰭狀結構508’的晶格完整性。
本發明方法所形成之半導體結構，具有第一鰭狀結構與第二鰭狀結構，後續可以進行其他製程，例如在鰭狀結構上形成閘極介電層(圖未示)以及閘極(圖未示)，並形成汲極/源極以形成電晶體(transistor)。或者配合其他電晶體製程，例如金屬閘極置換製程(metal gate replacement)。請參考第13圖，所繪示為本發明一個實施例中半導體結構進行金屬閘極置換製程之步驟示意圖。如第13圖所示，在形成層間介電層312，移除虛擬閘極後，會形成的凹槽414與凹槽514。 所述的凹槽414與凹槽514的側面會設置在淺溝渠隔離302之虛擬鰭狀結構310上。後續，在第一鰭狀結構408’與第二鰭狀結構508’上分別形成第一閘極介電層 412與第二閘極介電層512，並在填入第一金屬閘極414與第二金屬閘極512。由於凹槽414與凹槽514側壁對應在淺溝渠隔離302之虛擬鰭狀結構310上，填入的金屬閘極可以具有較大的空間餘裕。
綜上所述，本發明提供了一種半導體結構以及形成半導體結構的方法，其特徵在於具有第一半導體層作為緩衝層，所形成之鰭狀結構可以具有較佳的晶格結構，且不需要額外的鰭切步驟。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
300:基底
302:淺溝渠隔離
304”:絕緣結構
310:虛置鰭狀結構
400:第一區域
404:第一半導體層
408’:第一鰭狀結構
500:第二區域
504:第二半導體層

Claims (17)

  1. 一種半導體結構，包含：一基底，具有一第一區域，該第一區域介於一淺溝渠隔離之間；一第一半導體層，設置在該第一區域中；複數個第一次溝渠，設置在該第一半導體層中；複數個絕緣結構，設置在該第一半導體層上；一第一中半導體層，設置在該第一半導體層與該絕緣結構之間；以及一第一上半導體層形成複數個第一鰭狀結構，埋入(embedded)在該等第一次溝渠中，該等第一鰭狀結構與該等絕緣結構交錯排列，且該等第一鰭狀結構突出於該絕緣結構上，其中該第一半導體層與該第一上半導體層具有不同的晶格係數(lattice mismatch)，其中該第一中半導體層與該第一半導體層的邊界，高於該第一鰭狀結構的底面。
  2. 如申請專利範圍第1項所述之半導體結構，其中該第一半導體層的深度大於該第一次溝渠的深度。
  3. 如申請專利範圍第1項所述之半導體結構，其中該第一半導體層的頂面齊平於該淺溝渠隔離的頂面。
  4. 如申請專利範圍第1項所述之半導體結構，還包含至少一虛置鰭狀結構，設置於該淺溝渠隔離上。
  5. 如申請專利範圍第4項所述之半導體結構，其中該虛置鰭狀結構包含介電材料。
  6. 如申請專利範圍第4項所述之半導體結構，其中該虛置鰭狀結構的頂面齊高於該第一鰭狀結構的頂面。
  7. 如申請專利範圍第1項所述之半導體結構，其中該第一中半導體層的頂面與該淺溝渠隔離的頂面齊平。
  8. 如申請專利範圍第1項所述之半導體結構，其中該基底還具有一第二區域，該第二區域被該淺溝渠隔離包圍且與該第一區域分隔。
  9. 如申請專利範圍第8項所述之半導體結構，還包含：一第二半導體層，設置在該第一區域中；複數個第二次溝渠，設置在該第二半導體層中；該等絕緣結構，設置在該第二半導體層上；以及複數個第二鰭狀結構，埋入在該等第二次溝渠中，該等第二鰭狀結構與該等絕緣結構交錯排列，且該等第二鰭狀結構突出於該絕緣結構上。
  10. 如申請專利範圍第9項所述之半導體結構，其中該等第二次溝渠的深度不同於該等第一次溝渠的深度。
  11. 如申請專利範圍第9項所述之半導體結構，其中該等第二次溝渠的寬度不同於該等第一次溝渠的寬度。
  12. 如申請專利範圍第1項所述之半導體結構，其中該第一半導體層中具 有差排(dislocation)。
  13. 如申請專利範圍第1項所述之半導體結構，其中該第一半導體層、該第一上半導體層與該基底具有不同的晶格係數。
  14. 一種製作半導體結構的方法，包含：提供一基底，該基底具有一第一區域，且具有一第一溝渠位在該第一區域中，該第一溝渠介於一淺溝渠隔離之間；形成一第一半導體層於該第一溝渠中；形成一第一中半導體層於該第一半導體層上；形成一圖案化遮罩層於該第一半導體層上；以該圖案化遮罩層作為遮罩，圖案化該第一半導體層，以在該第一半導體層中形成複數個第一次溝渠；在該等第一次溝渠中形成複數個第一鰭狀結構，其中該第一中半導體層與該第一半導體層的邊界，高於該第一鰭狀結構的底面；以及移除該圖案化遮罩層至一預定高度，使該圖案化遮罩層形成複數個絕緣結構，該複數個絕緣結構與該等第一鰭狀結構交替排列。
  15. 如申請專利範圍第14項所述之製作半導體結構的方法，其中該圖案化遮罩層覆蓋該第一區域與該淺溝渠隔離的至少一邊界。
  16. 如申請專利範圍第14項所述之製作半導體結構的方法，其中形成該第一半導體層包含一選擇性磊晶成長(selective epitaxial growth,SEG)製程。
  17. 如申請專利範圍第14項所述之製作半導體結構的方法，其中形成該第一鰭狀結構包含一選擇性磊晶成長製程。
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