US20170278928A1 - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- US20170278928A1 US20170278928A1 US15/152,570 US201615152570A US2017278928A1 US 20170278928 A1 US20170278928 A1 US 20170278928A1 US 201615152570 A US201615152570 A US 201615152570A US 2017278928 A1 US2017278928 A1 US 2017278928A1
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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Definitions
- the present invention relates to a semiconductor device and method of forming the same, and more particularly, relates to FinFET semiconductor device with fine lattice structure and method of forming the same.
- Fin-FET Fin-shaped FETs
- the manufacturing processes of Fin-FET devices can be integrated into traditional logic device processes, and thus are more compatible.
- the three-dimensional structure of the Fin-FET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect.
- DIBL drain-induced barrier lowering
- the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased. In current years, the development of the Fin-FETS is still aiming to devices with smaller scales.
- the present invention therefore provides a FinFET semiconductor device with fine lattice structure and method of forming the same.
- the present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer.
- the substrate has a first region disposed between two STIs.
- the first semiconductor layer is disposed in the first region.
- the first sub recesses are disposed in the first semiconductor layer.
- the insulation structures are disposed on the first semiconductor layer.
- the first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.
- the present invention provides a method of forming a semiconductor device.
- a substrate including a first region is provided, wherein the first region is disposed between two shallow trench isolations (STI).
- a first semiconductor layer is formed in the first region.
- a patterned mask layer is formed on the first semiconductor layer, following by using the patterned mask layer as a mask to pattern the first semiconductor layer, thereby forming a plurality of first sub recesses.
- a plurality of first fin structures are formed in the first sub recesses, and the patterned mask layer is removed to a predetermined height so the patterned mask layer becomes a plurality of insulation structures, wherein the insulation structures are arranged alternatively with the first fin structures.
- the formed fin structures can have good lattice structure and no fin cut process is required.
- FIG. 1A , FIG. 1B , FIG. 2 , FIG. 3 , FIG. 4A , FIG. 4B , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 10A , FIG. 10B , FIG. 11A and FIG. 11B are schematic diagrams of the method of forming a semiconductor device according to one embodiment of the present invention.
- FIG. 12 is a schematic diagram of the semiconductor device according to another embodiment of the present invention.
- FIG. 13 is a schematic diagram of the semiconductor device according to another embodiment of the present invention.
- FIG. 14 is a schematic diagram of the method including a semiconductor metal gate displacement process.
- FIG. 9A , FIG. 10A and FIG. 11A are cross sectional view and FIG. 1B , FIG. 3B , FIG. 4B , FIG. 5B , FIG. 6B , FIG. 7B , FIG. 8B , FIG. 9B , FIG. 10B and FIG. 11B are top view.
- a semiconductor substrate 300 is provided to serve as a base for forming devices, components, or circuits.
- the substrate 300 is preferably composed of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layered materials thereof.
- the semiconductor substrate 300 may also be composed of other semiconductor materials, such as germanium, and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs.
- the semiconductor substrate 300 is depicted as a bulk semiconductor substrate, the arrangement of a semiconductor on an insulator substrate, such as silicon-on-insulator (SOI) substrates, is also suitable for the semiconductor substrate 300 .
- a shallow trench isolation (STI) 302 is disposed on the substrate 300 and different areas surrounded by the STI 302 can be defined as different active regions.
- a first region 400 and a second region 500 are both surrounded by the STI 302 , wherein the first region 400 is directly adjacent to the second region 500 .
- there can be other active regions disposed between the first region 400 and the second region 500 so the first region 400 can be not directly adjacent to the second region 500 .
- the first region 400 is an N-type transistor region and the second region 500 is a P-type transistor region.
- the conductivity types of the first region 400 and the second region 500 can be the same.
- a first trench 402 and a second trench 502 are formed respectively in the first region 400 and the second region 500 .
- the first trench 402 corresponds exactly to the first region 400 and the second trench 502 corresponds exactly to the second region 500 , meaning that the sidewalls of the first trench 402 and the second trench 502 are the sidewalls of the shallow trench isolation 302 .
- the depth of the first trench 402 and the depth of the second trench 502 are not greater than the depth of the shallow trench isolation 302 .
- the depth of the first trench 402 is substantially equal to the depth of the second trench 502 .
- the depth of the first trench 402 may be different from that of the second trench 502 .
- a first semiconductor layer 404 is formed in the first trench 402 and a second semiconductor layer 504 is formed in the second trench 502 .
- the first semiconductor layer 404 and the second semiconductor layer 504 completely fill the first trench 402 and the second trench 502 .
- the step of forming the first semiconductor layer 404 and the second semiconductor layer 504 includes a selective epitaxial growth (SEG) process, wherein the first semiconductor layer 404 and the second semiconductor layer 504 can be formed by different SEG processes or the same SEG process.
- the first semiconductor layer 404 and the second semiconductor layer 504 can have the same material or different materials.
- an optional planarization process can be performed to make the top surface of the first semiconductor layer 404 and the second semiconductor layer 504 level with the top surface of the shallow trench isolation 302 .
- a mask layer 304 and a plurality of mandrels 306 are formed sequentially on the substrate 300 .
- the mask layer 304 is formed comprehensively on the substrate 300 and the material thereof may include any material suitable as a mask in the subsequent etching process.
- the mask layer 304 includes a dielectric layer with electrical isolation capability, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC) or advanced pattern film (APF) provided by Applied Materials Co., but is not limited thereto.
- the mandrels 306 can be made of poly-silicon or amorphous silicon. As shown in the top view of FIG.
- the mandrels 306 are stipe patterns, which are paralleled with each other and stretching along the same direction S.
- there is at least one mandrel 306 straddling across the first region 400 and there is at least one mandrel 306 straddling across the second region 500 .
- the mandrel 306 protrudes upwardly and downwardly over the first region 400 and/or the second region 500 .
- a spacer 308 is formed on the sidewalls of each mandrel 306 .
- the method of forming the spacer 308 includes, for example, forming a spacer material layer (not shown) comprehensively on the substrate 300 to conformally cover the top surface and the sidewalls of the mandrel 306 , and then performing an anisotropic etching process to expose the top surface of the mandrels 306 so the spacer 308 is formed only on the sidewalls of the mandrel 306 .
- the spacer 308 includes materials having etching selectivity with respect to the mask layer 306 , for example, silicon oxide, silicon nitride, high temperature oxide (HTO) or silicon nitride with precursors including hexachlorodisilane (Si 2 Cl 6 ) (HCD-SiN), but is not limited thereto.
- the spacer 308 surrounds the sidewalls of the mandrel 306 , and it is noted that in the area between the first region 400 and the second 500 , the spacer 308 would cover a border of the first region 400 and a border of the second region 500 .
- the mandrels 306 are removed to expose the under mask layer 304 .
- the removing step may be a dry etching step and/or a wet etching step, wherein the dry etching step includes using a gas mixture containing hydrogen bromide (HBr), nitrogen (N 2 ) and nitrogen trifluoride (NF 3 ), or containing boron trichloride (BCl 3 ), and the wet etching step includes using etchant containing tetramethyl ammonium hydroxide (TMAH).
- HBr hydrogen bromide
- N 2 nitrogen
- NF 3 nitrogen trifluoride
- BCl 3 boron trichloride
- TMAH tetramethyl ammonium hydroxide
- the mask layer 304 is patterned by using the spacer 308 as a mask to transfer the patterns thereof to the formed patterned mask layer 304 ′, which may also include strip patterns.
- the embodiment shown in FIG. 4A , FIG. 5A , FIG. 6A and FIG. 7A are exemplary embodiment of the sidewall image transfer (SIT) process for forming the patterned mask layer 304 ′, and one skilled in the arts would understand that the patterned mask layer 304 ′can also be formed in other ways. For example, it can be formed by directly performing a lithography and patterning process for the mask layer 304 with forming appropriate stripe photo resist layers (not shown) thereon.
- the first semiconductor layer 404 and the second semiconductor layer 504 are patterned by using the patterned mask layer 304 ′ as a mask, to form a plurality of first sub recesses 406 in the first semiconductor layer 404 and a plurality of second sub recesses 506 in the second semiconductor layer 504 .
- the position and/or width of the mandrels 306 , and/or the width of the spacer 308 same size of the first sub recesses 406 or second sub recesses 506 can be obtained. Please again refer to FIG. 6A and FIG.
- the first sub recesses 406 and the second sub recesses 506 can have different depths or different widths, as shown in FIG. 8A , the depth of the second sub recesses 506 are greater than the depth of the first sub recesses 406 .
- At least one selective epitaxial growth (SEG) process is performed to form a first top semiconductor layer 408 on the first semiconductor layer 404 and a second top semiconductor layer 508 on the second semiconductor layer 504 .
- the first top semiconductor layer 408 completely fills the first sub recesses 406
- the second top semiconductor layer 508 completely fills the second sub recesses 506 .
- both of which protrude upwardly over the substrate 300 and more preferably, protrude over top surface of the patterned mask layer 304 ′.
- the first top semiconductor layer 408 and the second top semiconductor layer 508 may be formed by the same or different epitaxial processes, so the materials thereof may be the same or different.
- a planarization process is carried out to make the top surface of the first top semiconductor layer 408 and the top surface of the second top semiconductor layer 508 level with the top surface of the patterned mask layer 304 ′.
- a dielectric material such as silicon dioxide can be filled into the area not filled with epitaxial material, so as to increase the reliability of the planarization process.
- a silicon oxide layer is filled into the area between the first region 400 and the second region 500 , thereby forming a dummy fin structure 310 on the shallow trench isolation 302 .
- the semiconductor device of the present invention in the first region 400 includes a substrate 300 having a shallow trench isolation 302 , a first semiconductor layer 404 , a plurality of first sub recesses 406 and a plurality of first fin structures 408 ′.
- the first semiconductor layer 404 is surrounded by the shallow trench isolation 302 , and the top surface of the first semiconductor layer 404 is leveled with the top surface of the shallow trench isolation 302 .
- the first sub recesses 406 are disposed in the first semiconductor layer 404 , and the insulation structures 304 ′′ are disposed on the first semiconductor layer 404 .
- the first fin structures 408 ′ which are formed from the first top semiconductor layer 408 , are embedded in the first sub recesses 406 , wherein the first fin structures 408 ′ are arranged alternatively with and protrude from the insulation structures 304 ′′.
- the components are similar to those in the first region 400 .
- the second semiconductor layer 504 has a material different from that of the first semiconductor layer 408 .
- the width and/or the depth and/or the material of the second fin structures 508 ′ can be different from that of the first fin structures 408 .
- the dummy fin structure 310 has a height substantially equal to that of the first fin structure 508 .
- the etching back process shown in FIG. 11A and FIG. 11B may therefore remove a small portion of the dummy fin structure 310 , so the top surface of the dummy fin structure 310 is slightly lower than the top surface of the first fin structures 408 ′.
- the present invention is advantageous in that, as shown in the cross sectional view of FIG. 11B , the first fin structures 408 can be automatically aligned and formed in the first sub recesses 406 in the first region 400 and are not formed outsides the first region 400 . Accordingly, no additional fin cut process in conventional sidewall transfer image process is required and a fine sidewall pattern with smaller critical dimension can still be obtained.
- the first semiconductor layer 404 and the second semiconductor layer 504 can serve as a buffer layer for lattice growth, which may have a small number of dislocations, but making the first fin structures 408 ′ and the second fin structures 508 ′ exhibit good lattice property without dislocations.
- the first semiconductor layer 404 and the first fin structures 408 ′ formed from the first top semiconductor layer 408 have different lattice coefficients (lattice mismatch).
- the first semiconductor layer 404 , the first fin structures 408 ′ and the substrate 300 have different lattice coefficients (lattice mismatch).
- the first semiconductor layer 404 , the second semiconductor layer 504 , the first fin structures 408 ′ and the second fin structures 508 ′ may include silicon, silicon germanium, germanium, arsenic, or other IV elements.
- the first semiconductor layer 404 or the second semiconductor layer 504 may be doped with IV elements with different atomic sizes, such as carbon (C) or tin (Sn), and its concentration may have gradient depending on the designs of the products.
- FIG. 12 shows a schematic diagram of the semiconductor device according to another embodiment of the present invention.
- the semiconductor device of the present embodiment further includes a first middle semiconductor layer 410 disposed between the first semiconductor layer 404 and insulation structures 304 ′′, and a second middle semiconductor layer 510 disposed between the second semiconductor layer 504 and the insulation structures 304 ′′.
- the top surface of the first middle semiconductor layer 410 and the top surface of the second middle semiconductor layer 510 are leveled with the top surface of the shallow trench isolation 302 .
- the first middle semiconductor layer 410 and the second middle semiconductor layer 510 may be formed after formation of the first semiconductor layer 404 and the second semiconductor layer 504 (as shown in FIG. 4A and FIG.
- FIG. 13 shows a schematic diagram of the semiconductor device according to another embodiment of the present invention. Comparing to the embodiment shown in FIG. 12 that first fin structures 408 ′ contact the first semiconductor layer 404 , the first fin structures 408 ′ in the present embodiment are embedded only in the first middle semiconductor layer 410 and do not contact the first semiconductor layer 404 , as illustrated in FIG. 13 . Similarly, the second fin structures 508 ′ are embedded only in the second middle semiconductor layer 510 and do not contact the second semiconductor layer 504 .
- the semiconductor device with the first fin structures 408 ′ and the second fin structures 508 ′ formed by the method of the present invention can be subjected to other semiconductor processes, for instance, forming a gate dielectric layer (not shown) and a gate layer (not) on the fin structures and then forming a source/drain region, thereby forming a transistor.
- the method can be in conjugation with other transistor formation process, such as a metal replacement gate process.
- FIG. 14 shows a schematic diagram of the method including a semiconductor metal gate displacement process. As shown in FIG. 14 , after forming an interlayer dielectric layer 312 and removing the dummy gate, a trench 413 and a trench 513 are formed.
- the sidewalls of the trench 413 and the sidewalls of the trench 513 are located above the dummy fin structure 310 on the shallow trench isolation 302 .
- a first gate dielectric layer 412 and a second gate dielectric layer 512 are formed on the first fin structures 408 ′ and the second fin structures 508 ′, following by filling a first metal gate 414 and a second metal gate 514 respectively in the recess 413 and the recess 513 . Since the sidewalls of the recess 413 and the recess 513 correspond to the dummy fin structure 310 , there is a larger space margin to form the first metal gate 414 and the second metal gate 514 .
- the formed fin structures can have fin lattice structure and no fin cut process is required.
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Also Published As
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TWI699885B (zh) | 2020-07-21 |
US10580864B2 (en) | 2020-03-03 |
US20180308933A1 (en) | 2018-10-25 |
TW201735352A (zh) | 2017-10-01 |
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