US20170278928A1 - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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US20170278928A1
US20170278928A1 US15/152,570 US201615152570A US2017278928A1 US 20170278928 A1 US20170278928 A1 US 20170278928A1 US 201615152570 A US201615152570 A US 201615152570A US 2017278928 A1 US2017278928 A1 US 2017278928A1
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semiconductor layer
region
semiconductor
disposed
semiconductor device
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US15/152,570
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Yu-Cheng Tung
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United Microelectronics Corp
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United Microelectronics Corp
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Publication of US20170278928A1 publication Critical patent/US20170278928A1/en
Priority to US16/022,737 priority Critical patent/US10580864B2/en
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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    • H01L21/8232—Field-effect technology
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    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
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    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
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Definitions

  • the present invention relates to a semiconductor device and method of forming the same, and more particularly, relates to FinFET semiconductor device with fine lattice structure and method of forming the same.
  • Fin-FET Fin-shaped FETs
  • the manufacturing processes of Fin-FET devices can be integrated into traditional logic device processes, and thus are more compatible.
  • the three-dimensional structure of the Fin-FET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect.
  • DIBL drain-induced barrier lowering
  • the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased. In current years, the development of the Fin-FETS is still aiming to devices with smaller scales.
  • the present invention therefore provides a FinFET semiconductor device with fine lattice structure and method of forming the same.
  • the present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer.
  • the substrate has a first region disposed between two STIs.
  • the first semiconductor layer is disposed in the first region.
  • the first sub recesses are disposed in the first semiconductor layer.
  • the insulation structures are disposed on the first semiconductor layer.
  • the first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.
  • the present invention provides a method of forming a semiconductor device.
  • a substrate including a first region is provided, wherein the first region is disposed between two shallow trench isolations (STI).
  • a first semiconductor layer is formed in the first region.
  • a patterned mask layer is formed on the first semiconductor layer, following by using the patterned mask layer as a mask to pattern the first semiconductor layer, thereby forming a plurality of first sub recesses.
  • a plurality of first fin structures are formed in the first sub recesses, and the patterned mask layer is removed to a predetermined height so the patterned mask layer becomes a plurality of insulation structures, wherein the insulation structures are arranged alternatively with the first fin structures.
  • the formed fin structures can have good lattice structure and no fin cut process is required.
  • FIG. 1A , FIG. 1B , FIG. 2 , FIG. 3 , FIG. 4A , FIG. 4B , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 10A , FIG. 10B , FIG. 11A and FIG. 11B are schematic diagrams of the method of forming a semiconductor device according to one embodiment of the present invention.
  • FIG. 12 is a schematic diagram of the semiconductor device according to another embodiment of the present invention.
  • FIG. 13 is a schematic diagram of the semiconductor device according to another embodiment of the present invention.
  • FIG. 14 is a schematic diagram of the method including a semiconductor metal gate displacement process.
  • FIG. 9A , FIG. 10A and FIG. 11A are cross sectional view and FIG. 1B , FIG. 3B , FIG. 4B , FIG. 5B , FIG. 6B , FIG. 7B , FIG. 8B , FIG. 9B , FIG. 10B and FIG. 11B are top view.
  • a semiconductor substrate 300 is provided to serve as a base for forming devices, components, or circuits.
  • the substrate 300 is preferably composed of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layered materials thereof.
  • the semiconductor substrate 300 may also be composed of other semiconductor materials, such as germanium, and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs.
  • the semiconductor substrate 300 is depicted as a bulk semiconductor substrate, the arrangement of a semiconductor on an insulator substrate, such as silicon-on-insulator (SOI) substrates, is also suitable for the semiconductor substrate 300 .
  • a shallow trench isolation (STI) 302 is disposed on the substrate 300 and different areas surrounded by the STI 302 can be defined as different active regions.
  • a first region 400 and a second region 500 are both surrounded by the STI 302 , wherein the first region 400 is directly adjacent to the second region 500 .
  • there can be other active regions disposed between the first region 400 and the second region 500 so the first region 400 can be not directly adjacent to the second region 500 .
  • the first region 400 is an N-type transistor region and the second region 500 is a P-type transistor region.
  • the conductivity types of the first region 400 and the second region 500 can be the same.
  • a first trench 402 and a second trench 502 are formed respectively in the first region 400 and the second region 500 .
  • the first trench 402 corresponds exactly to the first region 400 and the second trench 502 corresponds exactly to the second region 500 , meaning that the sidewalls of the first trench 402 and the second trench 502 are the sidewalls of the shallow trench isolation 302 .
  • the depth of the first trench 402 and the depth of the second trench 502 are not greater than the depth of the shallow trench isolation 302 .
  • the depth of the first trench 402 is substantially equal to the depth of the second trench 502 .
  • the depth of the first trench 402 may be different from that of the second trench 502 .
  • a first semiconductor layer 404 is formed in the first trench 402 and a second semiconductor layer 504 is formed in the second trench 502 .
  • the first semiconductor layer 404 and the second semiconductor layer 504 completely fill the first trench 402 and the second trench 502 .
  • the step of forming the first semiconductor layer 404 and the second semiconductor layer 504 includes a selective epitaxial growth (SEG) process, wherein the first semiconductor layer 404 and the second semiconductor layer 504 can be formed by different SEG processes or the same SEG process.
  • the first semiconductor layer 404 and the second semiconductor layer 504 can have the same material or different materials.
  • an optional planarization process can be performed to make the top surface of the first semiconductor layer 404 and the second semiconductor layer 504 level with the top surface of the shallow trench isolation 302 .
  • a mask layer 304 and a plurality of mandrels 306 are formed sequentially on the substrate 300 .
  • the mask layer 304 is formed comprehensively on the substrate 300 and the material thereof may include any material suitable as a mask in the subsequent etching process.
  • the mask layer 304 includes a dielectric layer with electrical isolation capability, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC) or advanced pattern film (APF) provided by Applied Materials Co., but is not limited thereto.
  • the mandrels 306 can be made of poly-silicon or amorphous silicon. As shown in the top view of FIG.
  • the mandrels 306 are stipe patterns, which are paralleled with each other and stretching along the same direction S.
  • there is at least one mandrel 306 straddling across the first region 400 and there is at least one mandrel 306 straddling across the second region 500 .
  • the mandrel 306 protrudes upwardly and downwardly over the first region 400 and/or the second region 500 .
  • a spacer 308 is formed on the sidewalls of each mandrel 306 .
  • the method of forming the spacer 308 includes, for example, forming a spacer material layer (not shown) comprehensively on the substrate 300 to conformally cover the top surface and the sidewalls of the mandrel 306 , and then performing an anisotropic etching process to expose the top surface of the mandrels 306 so the spacer 308 is formed only on the sidewalls of the mandrel 306 .
  • the spacer 308 includes materials having etching selectivity with respect to the mask layer 306 , for example, silicon oxide, silicon nitride, high temperature oxide (HTO) or silicon nitride with precursors including hexachlorodisilane (Si 2 Cl 6 ) (HCD-SiN), but is not limited thereto.
  • the spacer 308 surrounds the sidewalls of the mandrel 306 , and it is noted that in the area between the first region 400 and the second 500 , the spacer 308 would cover a border of the first region 400 and a border of the second region 500 .
  • the mandrels 306 are removed to expose the under mask layer 304 .
  • the removing step may be a dry etching step and/or a wet etching step, wherein the dry etching step includes using a gas mixture containing hydrogen bromide (HBr), nitrogen (N 2 ) and nitrogen trifluoride (NF 3 ), or containing boron trichloride (BCl 3 ), and the wet etching step includes using etchant containing tetramethyl ammonium hydroxide (TMAH).
  • HBr hydrogen bromide
  • N 2 nitrogen
  • NF 3 nitrogen trifluoride
  • BCl 3 boron trichloride
  • TMAH tetramethyl ammonium hydroxide
  • the mask layer 304 is patterned by using the spacer 308 as a mask to transfer the patterns thereof to the formed patterned mask layer 304 ′, which may also include strip patterns.
  • the embodiment shown in FIG. 4A , FIG. 5A , FIG. 6A and FIG. 7A are exemplary embodiment of the sidewall image transfer (SIT) process for forming the patterned mask layer 304 ′, and one skilled in the arts would understand that the patterned mask layer 304 ′can also be formed in other ways. For example, it can be formed by directly performing a lithography and patterning process for the mask layer 304 with forming appropriate stripe photo resist layers (not shown) thereon.
  • the first semiconductor layer 404 and the second semiconductor layer 504 are patterned by using the patterned mask layer 304 ′ as a mask, to form a plurality of first sub recesses 406 in the first semiconductor layer 404 and a plurality of second sub recesses 506 in the second semiconductor layer 504 .
  • the position and/or width of the mandrels 306 , and/or the width of the spacer 308 same size of the first sub recesses 406 or second sub recesses 506 can be obtained. Please again refer to FIG. 6A and FIG.
  • the first sub recesses 406 and the second sub recesses 506 can have different depths or different widths, as shown in FIG. 8A , the depth of the second sub recesses 506 are greater than the depth of the first sub recesses 406 .
  • At least one selective epitaxial growth (SEG) process is performed to form a first top semiconductor layer 408 on the first semiconductor layer 404 and a second top semiconductor layer 508 on the second semiconductor layer 504 .
  • the first top semiconductor layer 408 completely fills the first sub recesses 406
  • the second top semiconductor layer 508 completely fills the second sub recesses 506 .
  • both of which protrude upwardly over the substrate 300 and more preferably, protrude over top surface of the patterned mask layer 304 ′.
  • the first top semiconductor layer 408 and the second top semiconductor layer 508 may be formed by the same or different epitaxial processes, so the materials thereof may be the same or different.
  • a planarization process is carried out to make the top surface of the first top semiconductor layer 408 and the top surface of the second top semiconductor layer 508 level with the top surface of the patterned mask layer 304 ′.
  • a dielectric material such as silicon dioxide can be filled into the area not filled with epitaxial material, so as to increase the reliability of the planarization process.
  • a silicon oxide layer is filled into the area between the first region 400 and the second region 500 , thereby forming a dummy fin structure 310 on the shallow trench isolation 302 .
  • the semiconductor device of the present invention in the first region 400 includes a substrate 300 having a shallow trench isolation 302 , a first semiconductor layer 404 , a plurality of first sub recesses 406 and a plurality of first fin structures 408 ′.
  • the first semiconductor layer 404 is surrounded by the shallow trench isolation 302 , and the top surface of the first semiconductor layer 404 is leveled with the top surface of the shallow trench isolation 302 .
  • the first sub recesses 406 are disposed in the first semiconductor layer 404 , and the insulation structures 304 ′′ are disposed on the first semiconductor layer 404 .
  • the first fin structures 408 ′ which are formed from the first top semiconductor layer 408 , are embedded in the first sub recesses 406 , wherein the first fin structures 408 ′ are arranged alternatively with and protrude from the insulation structures 304 ′′.
  • the components are similar to those in the first region 400 .
  • the second semiconductor layer 504 has a material different from that of the first semiconductor layer 408 .
  • the width and/or the depth and/or the material of the second fin structures 508 ′ can be different from that of the first fin structures 408 .
  • the dummy fin structure 310 has a height substantially equal to that of the first fin structure 508 .
  • the etching back process shown in FIG. 11A and FIG. 11B may therefore remove a small portion of the dummy fin structure 310 , so the top surface of the dummy fin structure 310 is slightly lower than the top surface of the first fin structures 408 ′.
  • the present invention is advantageous in that, as shown in the cross sectional view of FIG. 11B , the first fin structures 408 can be automatically aligned and formed in the first sub recesses 406 in the first region 400 and are not formed outsides the first region 400 . Accordingly, no additional fin cut process in conventional sidewall transfer image process is required and a fine sidewall pattern with smaller critical dimension can still be obtained.
  • the first semiconductor layer 404 and the second semiconductor layer 504 can serve as a buffer layer for lattice growth, which may have a small number of dislocations, but making the first fin structures 408 ′ and the second fin structures 508 ′ exhibit good lattice property without dislocations.
  • the first semiconductor layer 404 and the first fin structures 408 ′ formed from the first top semiconductor layer 408 have different lattice coefficients (lattice mismatch).
  • the first semiconductor layer 404 , the first fin structures 408 ′ and the substrate 300 have different lattice coefficients (lattice mismatch).
  • the first semiconductor layer 404 , the second semiconductor layer 504 , the first fin structures 408 ′ and the second fin structures 508 ′ may include silicon, silicon germanium, germanium, arsenic, or other IV elements.
  • the first semiconductor layer 404 or the second semiconductor layer 504 may be doped with IV elements with different atomic sizes, such as carbon (C) or tin (Sn), and its concentration may have gradient depending on the designs of the products.
  • FIG. 12 shows a schematic diagram of the semiconductor device according to another embodiment of the present invention.
  • the semiconductor device of the present embodiment further includes a first middle semiconductor layer 410 disposed between the first semiconductor layer 404 and insulation structures 304 ′′, and a second middle semiconductor layer 510 disposed between the second semiconductor layer 504 and the insulation structures 304 ′′.
  • the top surface of the first middle semiconductor layer 410 and the top surface of the second middle semiconductor layer 510 are leveled with the top surface of the shallow trench isolation 302 .
  • the first middle semiconductor layer 410 and the second middle semiconductor layer 510 may be formed after formation of the first semiconductor layer 404 and the second semiconductor layer 504 (as shown in FIG. 4A and FIG.
  • FIG. 13 shows a schematic diagram of the semiconductor device according to another embodiment of the present invention. Comparing to the embodiment shown in FIG. 12 that first fin structures 408 ′ contact the first semiconductor layer 404 , the first fin structures 408 ′ in the present embodiment are embedded only in the first middle semiconductor layer 410 and do not contact the first semiconductor layer 404 , as illustrated in FIG. 13 . Similarly, the second fin structures 508 ′ are embedded only in the second middle semiconductor layer 510 and do not contact the second semiconductor layer 504 .
  • the semiconductor device with the first fin structures 408 ′ and the second fin structures 508 ′ formed by the method of the present invention can be subjected to other semiconductor processes, for instance, forming a gate dielectric layer (not shown) and a gate layer (not) on the fin structures and then forming a source/drain region, thereby forming a transistor.
  • the method can be in conjugation with other transistor formation process, such as a metal replacement gate process.
  • FIG. 14 shows a schematic diagram of the method including a semiconductor metal gate displacement process. As shown in FIG. 14 , after forming an interlayer dielectric layer 312 and removing the dummy gate, a trench 413 and a trench 513 are formed.
  • the sidewalls of the trench 413 and the sidewalls of the trench 513 are located above the dummy fin structure 310 on the shallow trench isolation 302 .
  • a first gate dielectric layer 412 and a second gate dielectric layer 512 are formed on the first fin structures 408 ′ and the second fin structures 508 ′, following by filling a first metal gate 414 and a second metal gate 514 respectively in the recess 413 and the recess 513 . Since the sidewalls of the recess 413 and the recess 513 correspond to the dummy fin structure 310 , there is a larger space margin to form the first metal gate 414 and the second metal gate 514 .
  • the formed fin structures can have fin lattice structure and no fin cut process is required.

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Abstract

The present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed within an STI. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device and method of forming the same, and more particularly, relates to FinFET semiconductor device with fine lattice structure and method of forming the same.
  • 2. Description of the Prior Art
  • In recent years, as various kinds of consumer electronic products are being constantly modified towards increased miniaturization, the size of semiconductor components are modified to be reduced accordingly, in order to meet high integration, high performance, low power consumption, and the demands of products.
  • However, with the increasing miniaturization of electronic products, current planar FETs no longer meet the requirements of the products. Thus, non-planar FETs such as Fin-shaped FETs (Fin-FET) have been developed, which includes a three-dimensional channel structure. The manufacturing processes of Fin-FET devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the Fin-FET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased. In current years, the development of the Fin-FETS is still aiming to devices with smaller scales.
    • SUMMARY OF THE INVENTION
  • The present invention therefore provides a FinFET semiconductor device with fine lattice structure and method of forming the same.
  • According to one embodiment, the present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed between two STIs. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.
  • According to another embodiment, the present invention provides a method of forming a semiconductor device. First, a substrate including a first region is provided, wherein the first region is disposed between two shallow trench isolations (STI). A first semiconductor layer is formed in the first region. Next, a patterned mask layer is formed on the first semiconductor layer, following by using the patterned mask layer as a mask to pattern the first semiconductor layer, thereby forming a plurality of first sub recesses. Then, a plurality of first fin structures are formed in the first sub recesses, and the patterned mask layer is removed to a predetermined height so the patterned mask layer becomes a plurality of insulation structures, wherein the insulation structures are arranged alternatively with the first fin structures.
  • Based on the semiconductor device and the method set forth in the present invention, which is characterized by using the semiconductor layer as a buffer layer, the formed fin structures can have good lattice structure and no fin cut process is required.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A, FIG. 1B, FIG. 2, FIG. 3, FIG. 4A, FIG. 4B, FIG. 5A, FIG. 5B, FIG. 6A, FIG. 6B, FIG. 7A, FIG. 7B, FIG. 8A, FIG. 8B, FIG. 9A, FIG. 9B, FIG. 10A, FIG. 10B, FIG. 11A and FIG. 11B are schematic diagrams of the method of forming a semiconductor device according to one embodiment of the present invention.
  • FIG. 12 is a schematic diagram of the semiconductor device according to another embodiment of the present invention.
  • FIG. 13 is a schematic diagram of the semiconductor device according to another embodiment of the present invention.
  • FIG. 14 is a schematic diagram of the method including a semiconductor metal gate displacement process.
    •  DETAILED DESCRIPTION
  • To provide a better understanding of the presented invention, preferred embodiments will be made in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.
  • Please refer to FIG. 1A, FIG. 1B, FIG. 2, FIG. 3, FIG. 4A, FIG. 4B, FIG. 5A, FIG. 5B, FIG. 6A, FIG. 6B, FIG. 7A, FIG. 7B, FIG. 8A, FIG. 8B, FIG. 9A, FIG. 9B, FIG. 10A, FIG. 10B, FIG. 11A and FIG. 11B, which are schematic diagrams of the method of forming a semiconductor device according to one embodiment of the present invention, wherein FIG. 1A, FIG. 3, FIG. 4A, FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A and FIG. 11A are cross sectional view and FIG. 1B, FIG. 3B, FIG. 4B, FIG. 5B, FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, FIG. 10B and FIG. 11B are top view.
  • Please first see FIG. 1A and FIG. 1B, wherein FIG. 1A is illustrated by taking along line AA′ of FIG. 1B. A semiconductor substrate 300 is provided to serve as a base for forming devices, components, or circuits. The substrate 300 is preferably composed of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layered materials thereof. The semiconductor substrate 300 may also be composed of other semiconductor materials, such as germanium, and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs. Although the semiconductor substrate 300 is depicted as a bulk semiconductor substrate, the arrangement of a semiconductor on an insulator substrate, such as silicon-on-insulator (SOI) substrates, is also suitable for the semiconductor substrate 300. A shallow trench isolation (STI) 302 is disposed on the substrate 300 and different areas surrounded by the STI 302 can be defined as different active regions. In the present embodiment, as shown in FIG. 1A and FIG. 1B, a first region 400 and a second region 500 are both surrounded by the STI 302, wherein the first region 400 is directly adjacent to the second region 500. In another embodiment, there can be other active regions disposed between the first region 400 and the second region 500, so the first region 400 can be not directly adjacent to the second region 500. In one embodiment, the first region 400 is an N-type transistor region and the second region 500 is a P-type transistor region. In another embodiment, the conductivity types of the first region 400 and the second region 500 can be the same.
  • As shown in the cross sectional view in FIG. 2, a first trench 402 and a second trench 502 are formed respectively in the first region 400 and the second region 500. In one preferred embodiment, the first trench 402 corresponds exactly to the first region 400 and the second trench 502 corresponds exactly to the second region 500, meaning that the sidewalls of the first trench 402 and the second trench 502 are the sidewalls of the shallow trench isolation 302. The depth of the first trench 402 and the depth of the second trench 502 are not greater than the depth of the shallow trench isolation 302. In one embodiment, the depth of the first trench 402 is substantially equal to the depth of the second trench 502. In another embodiment, depending on the design of the subsequently formed epitaxial material, the depth of the first trench 402 may be different from that of the second trench 502.
  • As shown in FIG. 3, a first semiconductor layer 404 is formed in the first trench 402 and a second semiconductor layer 504 is formed in the second trench 502. Preferably, the first semiconductor layer 404 and the second semiconductor layer 504 completely fill the first trench 402 and the second trench 502. In one embodiment, the step of forming the first semiconductor layer 404 and the second semiconductor layer 504 includes a selective epitaxial growth (SEG) process, wherein the first semiconductor layer 404 and the second semiconductor layer 504 can be formed by different SEG processes or the same SEG process. Thus, the first semiconductor layer 404 and the second semiconductor layer 504 can have the same material or different materials. After the formation of the first semiconductor layer 404 and the second semiconductor layer 504, an optional planarization process can be performed to make the top surface of the first semiconductor layer 404 and the second semiconductor layer 504 level with the top surface of the shallow trench isolation 302.
  • As shown in FIG. 4A and FIG. 4B, a mask layer 304 and a plurality of mandrels 306 are formed sequentially on the substrate 300. The mask layer 304 is formed comprehensively on the substrate 300 and the material thereof may include any material suitable as a mask in the subsequent etching process. Preferably, the mask layer 304 includes a dielectric layer with electrical isolation capability, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC) or advanced pattern film (APF) provided by Applied Materials Co., but is not limited thereto. The mandrels 306 can be made of poly-silicon or amorphous silicon. As shown in the top view of FIG. 4B, the mandrels 306 are stipe patterns, which are paralleled with each other and stretching along the same direction S. In one preferred embodiment, there is at least one mandrel 306 straddling across the first region 400, and there is at least one mandrel 306 straddling across the second region 500. Preferably, the mandrel 306 protrudes upwardly and downwardly over the first region 400 and/or the second region 500. In addition, there is at least one mandrel 306 disposed on the STI 302 which is between the first area 400 and the second region 500.
  • As shown in FIG. 5A and 5B, a spacer 308 is formed on the sidewalls of each mandrel 306. The method of forming the spacer 308 includes, for example, forming a spacer material layer (not shown) comprehensively on the substrate 300 to conformally cover the top surface and the sidewalls of the mandrel 306, and then performing an anisotropic etching process to expose the top surface of the mandrels 306 so the spacer 308 is formed only on the sidewalls of the mandrel 306. Preferably, the spacer 308 includes materials having etching selectivity with respect to the mask layer 306, for example, silicon oxide, silicon nitride, high temperature oxide (HTO) or silicon nitride with precursors including hexachlorodisilane (Si2Cl6) (HCD-SiN), but is not limited thereto. As shown in the top view of FIG. 5B, the spacer 308 surrounds the sidewalls of the mandrel 306, and it is noted that in the area between the first region 400 and the second 500, the spacer 308 would cover a border of the first region 400 and a border of the second region 500.
  • Next, as shown in FIG. 6A and FIG. 6B, the mandrels 306 are removed to expose the under mask layer 304. In one embodiment, when mandrels 306 includes poly-silicon, the removing step may be a dry etching step and/or a wet etching step, wherein the dry etching step includes using a gas mixture containing hydrogen bromide (HBr), nitrogen (N2) and nitrogen trifluoride (NF3), or containing boron trichloride (BCl3), and the wet etching step includes using etchant containing tetramethyl ammonium hydroxide (TMAH).
  • As shown in FIG. 7A and FIG. 7B, the mask layer 304 is patterned by using the spacer 308 as a mask to transfer the patterns thereof to the formed patterned mask layer 304′, which may also include strip patterns. It is noted that the embodiment shown in FIG. 4A, FIG. 5A, FIG. 6A and FIG. 7A are exemplary embodiment of the sidewall image transfer (SIT) process for forming the patterned mask layer 304′, and one skilled in the arts would understand that the patterned mask layer 304′can also be formed in other ways. For example, it can be formed by directly performing a lithography and patterning process for the mask layer 304 with forming appropriate stripe photo resist layers (not shown) thereon.
  • As shown in FIG. 8A and in FIG. 8B, the first semiconductor layer 404 and the second semiconductor layer 504 are patterned by using the patterned mask layer 304′ as a mask, to form a plurality of first sub recesses 406 in the first semiconductor layer 404 and a plurality of second sub recesses 506 in the second semiconductor layer 504. In one preferred embodiment of the present invention, by adjusting the position and/or width of the mandrels 306, and/or the width of the spacer 308, same size of the first sub recesses 406 or second sub recesses 506 can be obtained. Please again refer to FIG. 6A and FIG. 6B, since the spacer 308 are formed above one boundary of the first region 400 and one boundary of the second region 500, the pattern thereof is not affected by the shallow trench isolation 302 during the patterning process so the contours of the first sub recesses 406 and the second sub recesses 506 can be of the same size. In another embodiment of the present invention, the first sub recesses 406 and the second sub recesses 506 can have different depths or different widths, as shown in FIG. 8A, the depth of the second sub recesses 506 are greater than the depth of the first sub recesses 406.
  • As shown in FIG. 9A and FIG. 9B, at least one selective epitaxial growth (SEG) process is performed to form a first top semiconductor layer 408 on the first semiconductor layer 404 and a second top semiconductor layer 508 on the second semiconductor layer 504. The first top semiconductor layer 408 completely fills the first sub recesses 406, and the second top semiconductor layer 508 completely fills the second sub recesses 506. Preferably, both of which protrude upwardly over the substrate 300, and more preferably, protrude over top surface of the patterned mask layer 304′. The first top semiconductor layer 408 and the second top semiconductor layer 508 may be formed by the same or different epitaxial processes, so the materials thereof may be the same or different.
  • As shown in FIG. 10A and FIG. 10B, a planarization process is carried out to make the top surface of the first top semiconductor layer 408 and the top surface of the second top semiconductor layer 508 level with the top surface of the patterned mask layer 304′. In one embodiment, before the planarization process, a dielectric material such as silicon dioxide can be filled into the area not filled with epitaxial material, so as to increase the reliability of the planarization process. For example, a silicon oxide layer is filled into the area between the first region 400 and the second region 500, thereby forming a dummy fin structure 310 on the shallow trench isolation 302.
  • As shown in FIG. 11A and FIG. 11B, an etching back process is performed to remove a portion of the patterned mask layer 304′ to a predetermined height so that it becomes a plurality of insulation structures 304″ and the first top semiconductor layer 408 becomes a plurality of first fin structures 408′, the second top semiconductor layer 508 becomes a plurality of second fin structures 508′. By doing this, the semiconductor device of the present invention is therefore obtained. As shown in FIG. 11A and FIG. 11B, the semiconductor device of the present invention in the first region 400 includes a substrate 300 having a shallow trench isolation 302, a first semiconductor layer 404, a plurality of first sub recesses 406 and a plurality of first fin structures 408′. The first semiconductor layer 404 is surrounded by the shallow trench isolation 302, and the top surface of the first semiconductor layer 404 is leveled with the top surface of the shallow trench isolation 302. The first sub recesses 406 are disposed in the first semiconductor layer 404, and the insulation structures 304″ are disposed on the first semiconductor layer 404. The first fin structures 408′, which are formed from the first top semiconductor layer 408, are embedded in the first sub recesses 406, wherein the first fin structures 408′ are arranged alternatively with and protrude from the insulation structures 304″. In the second region 500, the components are similar to those in the first region 400. In one embodiment, the second semiconductor layer 504 has a material different from that of the first semiconductor layer 408. In one embodiment, the width and/or the depth and/or the material of the second fin structures 508′ can be different from that of the first fin structures 408. In one embodiment, the dummy fin structure 310 has a height substantially equal to that of the first fin structure 508. In another embodiment, when the dummy fin structure 310 has a material with a relatively small etching selection relatively with respect to the patterned mask layer 304′, the etching back process shown in FIG. 11A and FIG. 11B may therefore remove a small portion of the dummy fin structure 310, so the top surface of the dummy fin structure 310 is slightly lower than the top surface of the first fin structures 408′.
  • The present invention is advantageous in that, as shown in the cross sectional view of FIG. 11B, the first fin structures 408 can be automatically aligned and formed in the first sub recesses 406 in the first region 400 and are not formed outsides the first region 400. Accordingly, no additional fin cut process in conventional sidewall transfer image process is required and a fine sidewall pattern with smaller critical dimension can still be obtained.
  • Since the present invention uses epitaxial growth process to form the first semiconductor layer 404, the second semiconductor layer 504, the first top semiconductor layer 408 (later becomes the first fin structure 408′) and the second top semiconductor layer 508 (later becomes the second fin structure 508′), the first semiconductor layer 404 and the second semiconductor layer 504 can serve as a buffer layer for lattice growth, which may have a small number of dislocations, but making the first fin structures 408′ and the second fin structures 508′ exhibit good lattice property without dislocations. In one embodiment, the first semiconductor layer 404 and the first fin structures 408′ formed from the first top semiconductor layer 408 have different lattice coefficients (lattice mismatch). In another embodiment, the first semiconductor layer 404, the first fin structures 408′ and the substrate 300 have different lattice coefficients (lattice mismatch). In one embodiment, if the first region 400 is an N type region, the first semiconductor layer 404, the second semiconductor layer 504, the first fin structures 408′ and the second fin structures 508′ may include silicon, silicon germanium, germanium, arsenic, or other IV elements. Preferably, in order to increase the channel stress of the fin structures, the first semiconductor layer 404 or the second semiconductor layer 504 may be doped with IV elements with different atomic sizes, such as carbon (C) or tin (Sn), and its concentration may have gradient depending on the designs of the products.
  • Please refer to FIG. 12, which shows a schematic diagram of the semiconductor device according to another embodiment of the present invention. The semiconductor device of the present embodiment further includes a first middle semiconductor layer 410 disposed between the first semiconductor layer 404 and insulation structures 304″, and a second middle semiconductor layer 510 disposed between the second semiconductor layer 504 and the insulation structures 304″. In one embodiment, the top surface of the first middle semiconductor layer 410 and the top surface of the second middle semiconductor layer 510 are leveled with the top surface of the shallow trench isolation 302. The first middle semiconductor layer 410 and the second middle semiconductor layer 510 may be formed after formation of the first semiconductor layer 404 and the second semiconductor layer 504 (as shown in FIG. 4A and FIG. 4B), removing top portions of the first semiconductor layer 404 and the second semiconductor layer 504, and formed by an epitaxial growth process, for example. By the formation of the first middle semiconductor layer 410 and the second middle semiconductor layer 510, the lattice property of the first fin structures 408′ and the second fin structures 508′ can further be upgraded. Please refer to FIG. 13, which shows a schematic diagram of the semiconductor device according to another embodiment of the present invention. Comparing to the embodiment shown in FIG. 12 that first fin structures 408′ contact the first semiconductor layer 404, the first fin structures 408′ in the present embodiment are embedded only in the first middle semiconductor layer 410 and do not contact the first semiconductor layer 404, as illustrated in FIG. 13. Similarly, the second fin structures 508′ are embedded only in the second middle semiconductor layer 510 and do not contact the second semiconductor layer 504.
  • The semiconductor device with the first fin structures 408′ and the second fin structures 508′ formed by the method of the present invention can be subjected to other semiconductor processes, for instance, forming a gate dielectric layer (not shown) and a gate layer (not) on the fin structures and then forming a source/drain region, thereby forming a transistor. Alternatively, the method can be in conjugation with other transistor formation process, such as a metal replacement gate process. Please refer to FIG. 14, which shows a schematic diagram of the method including a semiconductor metal gate displacement process. As shown in FIG. 14, after forming an interlayer dielectric layer 312 and removing the dummy gate, a trench 413 and a trench 513 are formed. In one embodiment, the sidewalls of the trench 413 and the sidewalls of the trench 513 are located above the dummy fin structure 310 on the shallow trench isolation 302. Subsequently, a first gate dielectric layer 412 and a second gate dielectric layer 512 are formed on the first fin structures 408′ and the second fin structures 508′, following by filling a first metal gate 414 and a second metal gate 514 respectively in the recess 413 and the recess 513. Since the sidewalls of the recess 413 and the recess 513 correspond to the dummy fin structure 310, there is a larger space margin to form the first metal gate 414 and the second metal gate 514.
  • In summary, according to the semiconductor device and the method set forth in the present invention, which is characterized by using the semiconductor layer as a buffer layer, the formed fin structures can have fin lattice structure and no fin cut process is required.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (21)

1. A semiconductor device, comprising:
a substrate, having a first region, wherein the first region is disposed between two shallow trench isolations (STI);
a first semiconductor layer, disposed in the first region, wherein a depth of the first semiconductor layer is less than depths of the STIs;
a plurality of first sub recesses, disposed in the first semiconductor layer;
a plurality of insulation structures, disposed on the first semiconductor layer; and
a first top semiconductor layer, comprising a plurality of first fin structures, which are embedded in the first sub recesses and arranged alternatively with the insulation structures, wherein the first fin structures protrude from the insulation structures.
2. The semiconductor device according to claim 1, wherein a depth of the first semiconductor layer is greater than a depth of the first sub recess.
3. The semiconductor device according to claim 1, wherein a top surface of the first semiconductor layer is leveled with a top surface of the STI.
4. The semiconductor device according to claim 1, further comprising at least one dielectric dummy fin structure disposed on the STI.
5. (canceled)
6. The semiconductor device according to claim 4, further comprising a metal gate disposed on the first fin structures and partially overlapping with the dielectric dummy fin structure.
7. The semiconductor device according to claim 1, further comprising a first middle semiconductor layer disposed between the first semiconductor layer and the insulation structures.
8. The semiconductor device according to claim 7, wherein a top surface of the first middle semiconductor layer is leveled with a top surface of the STI.
9. The semiconductor device according to claim 7, wherein a boundary between the first middle semiconductor layer and the first semiconductor layer is higher than a top surface of the first fin structure.
10. The semiconductor device according to claim 1, wherein the substrate further comprises a second region, which is surrounded by the STI and separated from the first region.
11. The semiconductor device according to claim 10, further comprising:
a second semiconductor layer, disposed in the second region;
a plurality of second sub recesses, disposed in the second semiconductor layer;
the insulation structures, disposed on the second semiconductor layer; and
a second top semiconductor layer, forming a plurality of second fin structures, which are embedded in the second sub recesses and arranged alternatively with the insulation structures, wherein the second fin structures protrude from the insulation structures.
12. The semiconductor device according to claim 11, wherein a depth of the second sub recess is different from a depth of the first sub recess.
13. The semiconductor device according to claim 11, wherein a width of the second sub recess is different from a width of the first sub recess.
14. The semiconductor device according to claim 11, wherein the first semiconductor layer has dislocation.
15. The semiconductor device according to claim 1, wherein there are lattice mismatch between the first semiconductor layer and the first top semiconductor layer.
16. The semiconductor device according to claim 1, wherein there are lattice mismatch between the first semiconductor layer, the first top semiconductor layer and the substrate.
17. A method of forming a semiconductor structure, comprising:
providing a substrate including a first region, wherein the first region is disposed between two shallow trench isolations (STI);
forming a first semiconductor layer in the first region, wherein a depth of the first semiconductor layer is less than depths of the STIs;
forming a patterned mask layer on the first semiconductor layer;
patterning the first semiconductor layer by using the patterned mask layer as a mask, thereby forming a plurality of first sub recesses in the first semiconductor layer;
forming a plurality of first fin structures in the first sub recesses; and
removing the patterned mask layer to a predetermined height so the patterned mask layer becomes a plurality of insulation structures, wherein the insulation structures are arranged alternatively with the first fin structures.
18. The method of forming a semiconductor structure according to claim 17, wherein the patterned mask layer covers at least one boundary between the first region and the STI.
19. The method of forming a semiconductor structure according to claim 17, wherein the step of forming the first semiconductor layer comprises a selective epitaxial growth (SEG) process.
20. The method of forming a semiconductor structure according to claim 17, wherein the step of forming the first fin structures comprises a selective epitaxial growth (SEG) process.
21. A semiconductor device, comprising:
a substrate, having a first region, wherein the first region is disposed between two shallow trench isolations (STI);
a first semiconductor layer, disposed in the first region, wherein the first semiconductor layer is an epitaxial layer ;
a plurality of first sub recesses, disposed in the first semiconductor layer;
a plurality of insulation structures, disposed on the first semiconductor layer; and
a first top semiconductor layer, comprising a plurality of first fin structures, which are embedded in the first sub recesses and arranged alternatively with the insulation structures, wherein the first fin structures protrude from the insulation structures.
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10121706B2 (en) * 2016-11-28 2018-11-06 Globalfoundries Inc. Semiconductor structure including two-dimensional and three-dimensional bonding materials
US20190067116A1 (en) * 2017-08-31 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage reduction methods and structures thereof
US20190067120A1 (en) * 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned structure for semiconductor devices
US20190157443A1 (en) * 2017-11-23 2019-05-23 United Microelectronics Corp. Method for fabricating semiconductor device
US20200152519A1 (en) * 2018-11-09 2020-05-14 Applied Materials, Inc. Fin damage reduction during punch through implantation of finfet device
US10686033B2 (en) 2018-11-09 2020-06-16 Applied Materials, Inc. Fin damage reduction during punch through implantation of FinFET device
US11120997B2 (en) * 2018-08-31 2021-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Surface treatment for etch tuning
US11211293B2 (en) * 2018-07-31 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and methods of forming the same
US11264380B2 (en) * 2018-08-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
US20220115530A1 (en) * 2020-10-13 2022-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric Fin Structure
US20220231024A1 (en) * 2021-01-15 2022-07-21 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure and fabrication method thereof
US11495501B2 (en) * 2018-09-28 2022-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor devices and methods of forming the same
US11532733B1 (en) * 2021-06-25 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric isolation structure for multi-gate transistors

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102521379B1 (en) * 2016-04-11 2023-04-14 삼성전자주식회사 Semiconductor device and method for manufacturing the same
US10504898B2 (en) * 2017-08-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field-effect transistor structure and method for forming the same
CN111194482A (en) * 2017-11-30 2020-05-22 英特尔公司 Fin patterning for advanced integrated circuit structure fabrication
US11682665B2 (en) 2019-06-19 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor layout with different row heights
US11217586B2 (en) 2020-01-31 2022-01-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having dummy fin physically separating the first and second gate stacks
TWI760947B (en) * 2020-01-31 2022-04-11 台灣積體電路製造股份有限公司 Semiconductor device and method for forming the same
KR20210155868A (en) * 2020-06-16 2021-12-24 삼성전자주식회사 Semiconductor device
US11948840B2 (en) 2021-08-31 2024-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Protective layer over FinFET and method of forming same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100163926A1 (en) * 2008-12-29 2010-07-01 Hudait Mantu K Modulation-doped multi-gate devices
US20120319211A1 (en) * 2011-06-16 2012-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel field effect transistor
US20130043506A1 (en) * 2011-08-17 2013-02-21 Chen-Hua Tsai Fin-FET and Method of Forming the Same
US20140141582A1 (en) * 2012-05-16 2014-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Cmos device and method of forming the same
US8765546B1 (en) * 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
US20150123166A1 (en) * 2013-11-01 2015-05-07 Globalfoundries Inc. Methods of forming finfet devices with alternative channel materials
US20160225906A1 (en) * 2015-02-04 2016-08-04 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device structure and method for forming the same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100555518B1 (en) * 2003-09-16 2006-03-03 삼성전자주식회사 Double gate field effect transistor and manufacturing method for the same
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
KR100720232B1 (en) 2005-12-30 2007-05-23 주식회사 하이닉스반도체 Method for forming semiconductor device having fin structure
KR101604566B1 (en) * 2007-12-28 2016-03-17 가부시키가이샤 브리지스톤 Hydroxyaryl functionalized polymers
JP5336890B2 (en) 2009-03-10 2013-11-06 キヤノン株式会社 Measuring apparatus, exposure apparatus, and device manufacturing method
US8633470B2 (en) 2009-12-23 2014-01-21 Intel Corporation Techniques and configurations to impart strain to integrated circuit devices
US9171929B2 (en) 2012-04-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of semiconductor device and method of making the strained structure
EP2741320B1 (en) 2012-12-05 2020-06-17 IMEC vzw Manufacturing method of a finfet device with dual-strained channels
US8912609B2 (en) * 2013-05-08 2014-12-16 International Business Machines Corporation Low extension resistance III-V compound fin field effect transistor
US9147766B2 (en) 2013-11-14 2015-09-29 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device having fin-type channel and method for forming the same
US9391141B2 (en) * 2014-02-24 2016-07-12 Imec Vzw Method for producing fin structures of a semiconductor device in a substrate
US9209179B2 (en) * 2014-04-15 2015-12-08 Samsung Electronics Co., Ltd. FinFET-based semiconductor device with dummy gates
US9224605B2 (en) 2014-05-01 2015-12-29 Globalfoundries Inc. Forming alternative material fins with reduced defect density by performing an implantation/anneal defect generation process
US9142418B1 (en) 2014-05-19 2015-09-22 Globalfoundries Inc. Double/multiple fin structure for FinFET devices
US9171752B1 (en) 2014-08-12 2015-10-27 Globalfoundries Inc. Product comprised of FinFET devices with single diffusion break isolation structures, and methods of making such a product
US9209279B1 (en) * 2014-09-12 2015-12-08 Applied Materials, Inc. Self aligned replacement fin formation
US20160104673A1 (en) * 2014-10-09 2016-04-14 United Microelectronics Corp. Fin-shaped field-effect transistor with a germanium epitaxial cap and a method for fabricating the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100163926A1 (en) * 2008-12-29 2010-07-01 Hudait Mantu K Modulation-doped multi-gate devices
US20120319211A1 (en) * 2011-06-16 2012-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel field effect transistor
US20130043506A1 (en) * 2011-08-17 2013-02-21 Chen-Hua Tsai Fin-FET and Method of Forming the Same
US20140141582A1 (en) * 2012-05-16 2014-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Cmos device and method of forming the same
US8765546B1 (en) * 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
US20150123166A1 (en) * 2013-11-01 2015-05-07 Globalfoundries Inc. Methods of forming finfet devices with alternative channel materials
US20160225906A1 (en) * 2015-02-04 2016-08-04 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device structure and method for forming the same

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10121706B2 (en) * 2016-11-28 2018-11-06 Globalfoundries Inc. Semiconductor structure including two-dimensional and three-dimensional bonding materials
US11837504B2 (en) 2017-08-30 2023-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned structure for semiconductor devices
US10943830B2 (en) * 2017-08-30 2021-03-09 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned structure for semiconductor devices
US20190067120A1 (en) * 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned structure for semiconductor devices
US10276445B2 (en) * 2017-08-31 2019-04-30 Taiwan Semiconductor Manfacturing Co., Ltd. Leakage reduction methods and structures thereof
US11742244B2 (en) 2017-08-31 2023-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage reduction methods and structures thereof
US10832958B2 (en) 2017-08-31 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage reduction methods and structures thereof
US20190067116A1 (en) * 2017-08-31 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage reduction methods and structures thereof
US10483395B2 (en) * 2017-11-23 2019-11-19 United Microelectronics Corp. Method for fabricating semiconductor device
US20190157443A1 (en) * 2017-11-23 2019-05-23 United Microelectronics Corp. Method for fabricating semiconductor device
US11211293B2 (en) * 2018-07-31 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and methods of forming the same
US11264380B2 (en) * 2018-08-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
US11120997B2 (en) * 2018-08-31 2021-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Surface treatment for etch tuning
US11495501B2 (en) * 2018-09-28 2022-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor devices and methods of forming the same
US10692775B2 (en) * 2018-11-09 2020-06-23 Applied Materials, Inc. Fin damage reduction during punch through implantation of FinFET device
US10686033B2 (en) 2018-11-09 2020-06-16 Applied Materials, Inc. Fin damage reduction during punch through implantation of FinFET device
US20200152519A1 (en) * 2018-11-09 2020-05-14 Applied Materials, Inc. Fin damage reduction during punch through implantation of finfet device
US20220115530A1 (en) * 2020-10-13 2022-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric Fin Structure
US11404576B2 (en) * 2020-10-13 2022-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric fin structure
US20220344502A1 (en) * 2020-10-13 2022-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric Fin Structure
US11735665B2 (en) * 2020-10-13 2023-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric fin structure
US20220231024A1 (en) * 2021-01-15 2022-07-21 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure and fabrication method thereof
US11908865B2 (en) * 2021-01-15 2024-02-20 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure and fabrication method thereof
US11532733B1 (en) * 2021-06-25 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric isolation structure for multi-gate transistors
US20220416058A1 (en) * 2021-06-25 2022-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric isolation structure for multi-gate transistors
US11888049B2 (en) 2021-06-25 2024-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric isolation structure for multi-gate transistors

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