TWI713642B - 鰭式場效電晶體及其製造方法 - Google Patents

鰭式場效電晶體及其製造方法 Download PDF

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TWI713642B
TWI713642B TW105139817A TW105139817A TWI713642B TW I713642 B TWI713642 B TW I713642B TW 105139817 A TW105139817 A TW 105139817A TW 105139817 A TW105139817 A TW 105139817A TW I713642 B TWI713642 B TW I713642B
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吳政達
王廷君
王永裕
蔡佳縈
詹詠翔
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例描述一種鰭式場效電晶體，其包括：基底、至少一個閘極結構、間隔物以及應變源極區及汲極區。所述至少一個閘極結構配置於所述基底上方及所述隔離結構上。所述間隔物配置於所述至少一個閘極結構的側壁上。第一阻隔材料層配置於所述間隔物上。所述應變源極區及汲極區配置於所述至少一個閘極結構的兩個相對側處。第二阻隔材料層配置於所述應變源極區及汲極區上。所述第一阻隔材料層及第二阻隔材料層包括富氧氧化物材料。

Description

鰭式場效電晶體及其製造方法
本發明實施例是關於一種半導體裝置與其製造方法，特別是關於一種鰭式場效電晶體與其製造方法。
隨著平面MOSFET按照比例縮小之發展過程，已經遭遇到諸多問題，包括汲極引致能障壁下降（drain induced barrier lowering；DIBL）、元件特性波動以及漏電等問題，正在開發例如鰭式場效電晶體（fin-type field effect transistor；FinFET）的三維立體多閘極結構作為替代方案。
在本發明的一些實施例中，描述一種鰭式場效電晶體。所述鰭式場效電晶體包括：基底，其具有隔離結構及在隔離結構之間的鰭片；至少一個閘極結構；間隔物；第一阻隔材料層及第二阻隔材料層；以及應變源極區及汲極區。至少一個閘極結構配置於基底上方及隔離結構上。間隔物配置於至少一個閘極結構的側壁上。第一阻隔材料層配置於間隔物上。應變源極區及汲極區配置於至少一個閘極結構的兩個相對側處。第二阻隔材料層配置於應變源極區及汲極區上。第一阻隔材料層及第二阻隔材料層包括富氧氧化物材料。
以下揭露內容提供用於實施所提供標的物的不同特徵的許多不同實施例或實例。下文描述組件及配置的特定實例以簡化本發明。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵及第二特徵可不直接接觸的實施例。另外，本發明可在各種實例中重複參考數字及/或字母。此重複係出於簡化及清楚的目的，且本身並不指示所論述各種實施例及/或組態之間的關係。
另外，為易於描述，可使用例如「在……之下」、「在……下方」、「下部」、「在……上方」、「上部」以及其類似者的空間相對術語以描述如諸圖中所說明的一個部件或特徵相對於另一部件或特徵的關係。除諸圖中所描繪的定向以外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞同樣可相應地進行解釋。
本發明的實施例描述FinFET的例示性製造製程及根據所述製造製程所製造得到的FinFET。FinFET裝置可形成於單晶半導體基底上，例如在本發明的某些實施例中的塊狀矽（bulk silicon）基底。在一些實施例中，作為替代方案，FinFET可形成於絕緣層上有矽（silicon-on-insulator；SOI）基底或絕緣層上有鍺（germanium-on-insulator；GOI）基底上。又，根據實施例，矽基底可包含其他導電層、摻雜區或其他半導體元件，例如電晶體、二極體或其類似物。實施例乃用於說明可能應用用途，但並不意欲限制本發明的範疇。
圖1繪示根據本發明的一些實施例的例示性FinFET的剖面圖。圖2A至圖2G繪示根據本發明的一些實施例之形成FinFET的製造方法的各種階段所製得的FinFET。在圖1中，FinFET 20包括形成於基底100上的至少一個閘極結構120、間隔物112以及形成於閘極結構120的相對側壁上的第一阻隔材料層114a，以及在閘極結構120下方的通道區102。FinFET 20包括應變源極區及汲極區130，其形成於基底100內及形成於隔離結構103之間。FinFET 20包括形成於應變源極區及汲極區130的表面上的第二阻隔材料層114b。在一些實施例中，隔離結構103為溝渠隔離結構。在某些實施例中，溝渠隔離結構呈條帶形狀且彼此平行地配置。應變源極區及汲極區130位於閘極結構120的兩個相對側處。在一些實施例中，FinFET 20為P通道FinFET。在一些實施例中，FinFET 20為n通道FinFET。
在圖2A中，提供基底100。舉例而言，基底100為單晶半導體基底或SOI基底。在一些實施例中，基底100為矽基底。基底100包含用於電性隔離的隔離結構103（圖1）及位於隔離結構103之間的鰭片102。在一實施例中，透過向下蝕刻至基底100之中以形成凹陷溝渠以及形成鰭片102。在一實施例中，使用如氧化矽或旋塗材料之介電材料填充於基底的溝渠中來形成隔離結構103。
參看圖2A，堆疊結構110形成於基底100及隔離結構103上，且橫跨鰭片102。在一些實施例中，堆疊結構110為彼此平行地配置的條帶形結構，且堆疊結構110的延伸方向垂直於鰭片102的延伸方向。在圖2A中，繪示出兩個堆疊結構110，但堆疊結構110的數目用於說明性目的，並不意欲限制本發明的結構。在某些實施例中，堆疊結構110包括多晶矽條帶106及位於多晶矽條帶106上的硬式罩幕條帶108。在一些實施例中，堆疊結構110藉由以下步驟形成：沈積多晶矽層（圖中未示）、多晶矽層上方的硬式罩幕層（圖中未示），且接著圖案化硬式罩幕層及多晶矽層以形成多晶矽條帶106及硬式罩幕條帶108。視情況，在形成多晶矽層之前形成氧化物層104以保護鰭片102。在一些實施例中，硬式罩幕層的材料包含藉由如低壓化學氣相沈積（low pressure chemical vapor deposition；LPCVD）或電漿增強式化學氣相沈積（plasma enhanced chemical vapor deposition；PECVD）所形成的氮化矽。
在圖2B中，在一些實施例中，間隔物112形成於堆疊結構110的側壁110b上。亦即，間隔物112形成於硬式罩幕條帶108及多晶矽條帶106的側壁上。在一實施例中，藉由以下步驟來形成間隔物112：沈積共形介電層（圖中未示）且接著回蝕介電層以僅在堆疊結構110的側壁110b上形成間隔物112。在一些實施例中，間隔物112由介電材料形成，而介電材料為例如氧化矽、氮化矽、矽碳氮氧化物（SiCON）或其組合。間隔物112可為單層或多層結構。
在圖2C中，在一些實施例中，使用堆疊結構110及間隔物112作為蝕刻罩幕，在預期形成源極區及汲極區的位置處移除基底100的一部分，而在堆疊結構110及間隔物112之側於基底100內形成凹陷105。使用包含非等向性蝕刻、等向性蝕刻或其組合之一或多個蝕刻製程來形成凹陷105。在一些實施例中，凹陷105形成於基底100內之後，在凹陷105內沈積應變材料以填充凹陷105來形成應變源極區及汲極區130，如圖2C中所繪示。在一些實施例中，應變源極區及汲極區130中的一些部分突出於基底100及隔離結構103之上。由於應變源極區及汲極區130位於通道區102的相對側，且應變材料的晶格常數不同於基底100的材料之晶格常數，因此通道區102承受應變或受壓而增加元件的載子遷移率並且增強元件效能。此外，應變源極區及汲極區130視情況可形成有頂蓋層（圖中未示），且頂蓋層的材料包括例如輕微摻雜或未經摻雜的含矽材料。
在某些實施例中，應變材料包含矽鍺（SiGe）、磷化矽（SiP）或碳化矽（SiC）。沈積於凹陷105（源極區及汲極區）內的應變材料為應力誘發性材料，其引起通道區的單軸壓縮應變（uniaxial compressive strain）。應變材料例如SiGe可用於增強P通道FinFET的電洞遷移率。為改良較高節點開發（例如節點-28（node-28）或更小）下的P通道FinFET的載子遷移率，可將Ge在SiGe中的含量調整為在特定範圍內。類似地，應變材料例如SiP可用於增強n通道FinFET的電子遷移率。在一些實施例中，應變源極區及汲極區130可透過磊晶生長製程來形成。在一些實施例中，磊晶生長製程方法可包括LPCVD、原子層化學氣相沈積（ALCVD）、超高真空化學氣相沈積（UHVCVD）、減壓化學氣相沈積（RPCVD）、分子束磊晶法（molecular beam epitaxy；MBE）、金屬有機氣相磊晶法（metalorganic vapor phase epitaxy；MOVPE）或其組合。或者，磊晶生長技術可利用循環沈積蝕刻（cyclic deposition-etch；CDE）磊晶製程或選擇性磊晶生長（selective epitaxial growth；SEG）製程來形成具有高晶體性質的應變材料。
圖2D為FinFET 20在製造方法的不同階段中之一處的立體圖，且圖2E為沿著圖2D的線I-I'截取的FinFET 20的剖面圖。如圖2D及圖2E中所繪示，第一阻隔材料層114a形成於間隔物112的表面112b上，且第二阻隔材料層114b形成於應變源極區及汲極區130的頂表面130a上。舉例而言，第一阻隔材料層114a或第二阻隔材料層114b的厚度的範圍為約1奈米至約50奈米。在某一實施例中，第一阻隔材料層114a的厚度的範圍為2奈米至5奈米。在某些實施例中，第二阻隔材料層114b的厚度的範圍為2奈米至5奈米。在一些實施例中，第一阻隔材料層114a及第二阻隔材料層114b同時形成。在某些實施例中，經由對間隔物112及應變源極區及汲極區130進行氧化處理來形成第一阻隔材料層114a及第二阻隔材料層114b。在一實施例中，氧化處理為在範圍為25℃至600℃的操作溫度下進行的低溫自由基氧化處理（low temperature radical oxidation treatment）。舉例而言，氧化處理製程包含使用含有氧（O）的至少一種氣體之電漿處理步驟。在氧化處理製程中，藉由包含於電漿處理中的中性自由基、離子、電子或其組合來氧化間隔物112及/或應變源極區及汲極區130的表面。在一些實施例中，第一阻隔材料層114a及第二阻隔材料層114b包含富氧氧化物材料（oxygen-rich oxide materials）。在一些實施例中，藉由進行包含應用電漿處理的氧化處理來形成第一阻隔材料層114a及第二阻隔材料層114b，且用於電漿處理的參數包含：在500瓦特至4000瓦特的功率、25℃至600℃的操作溫度以及0.5托至200托的操作壓力下，其中氧氣流動速率為約0.1 slm（標準狀態下公升/每分鐘）至約30 slm，且氫氣流動速率為約0.05 slm至約10 slm。在替代實施例中，藉由進行包含應用電漿處理的氧化處理來形成第一阻隔材料層114a及第二阻隔材料層114b，且用於電漿處理的操作參數包含：以約0.1 slm至約30 slm的氧氣流動速率及約0.05 slm至約10 slm的氫氣流動速率供應氧氣及氫氣；在500瓦特至4000瓦特的功率下；在300℃至400℃的操作溫度下以及1托至20托的操作壓力。
在一些實施例中，第一阻隔材料層114a的材料包含氧化物，且第二阻隔材料層114b的材料包含氧化物。在一些實施例中，第一阻隔材料層114a的氧含量大於間隔物112的氧含量。在一些實施例中，第二阻隔材料層114b的氧含量大於應變源極區及汲極區130的氧含量。在某些實施例中，第一阻隔材料層114a的材料包含例如富氧氧化物材料，例如:富氧氧化矽（oxygen-rich silicon oxide）、富氧SiON、富氧氮化矽（oxygen-rich silicon nitride）、富氧矽碳氮氧化物（oxygen-rich silicon carbon oxynitride）或其組合。在一實施例中，間隔物112的材料包含矽碳氮氧化物（SiCON），且第一阻隔材料層114a的材料包含富氧SiCON。在一實施例中，富氧SiCON的氧含量為8%至40%。在一實施例中，間隔物112的材料包含氮化矽，且第一阻隔材料層114a的材料包含富氧氮化矽或富氧SiON。在一實施例中，富氧SiON的氧含量為8%至40%。在替代性實施例中，間隔物112的材料包含氧化矽，且第一阻隔材料層114a的材料包含富氧氧化矽。在某些實施例中，第二阻隔材料層114b的材料包含富氧氧化物材料，例如富氧氧化矽、富氧氧化矽鍺（oxygen-rich silicon germanium oxide）或其組合。在一些實施例中，富氧半導體材料氧化物由MOx表示，其中M為Si或Ge，且2.1£x£2.5。在一實施例中，第二阻隔材料層114b的材料為富氧氧化矽SiOx，且2.1£x£2.5。
在替代實施例中，第一阻隔材料層114a及第二阻隔材料層114b包含帶負電荷層（negative-charged layer）。在一實施例中，富氧氧化物材料帶負電荷。在一實施例中，第一阻隔材料層114a包含帶負電荷SiCON層或帶負電荷氧化矽層。在一實施例中，第二阻隔材料層114b包含帶負電荷氧化矽層。在一些實施例中，帶負電荷層的表面電荷含量的範圍為約-20´1010 /cm2 至約-150´1010 /cm2 。相較於藉由熱氧化處理所形成的正常或中性氧化矽，可觀測到帶負電荷氧化矽具有較低結合能。
透過在間隔物112上形成第一阻隔材料層114a及形成第二阻隔材料層114b覆蓋住應變源極區及汲極區130的表面130a，可減少電子或電洞陷阱且減輕漏電現象。在一些實施例中，由於在間隔物112的表面112b上形成第一阻隔材料層114a（富氧SiCON層），因此間隔物112及其上的第一阻隔材料層114a所構成的複合結構可提供低介電常數（4.5至5.0），從而減小寄生電容且改良元件的操作速度。在一些實施例中，形成於應變源極區及汲極區130的表面130a上的第二阻隔材料層114b（富氧氧化矽）覆蓋住雜質及/或錯位，故電子或電洞陷阱減少。
圖2F為FinFET 20在製造方法的不同階段之一處的立體圖，且圖2G為沿著圖2F的線I-I'截取的FinFET 20的剖面圖。如圖2F及圖2G中所繪示，在一些實施例中，在移除堆疊結構110之後形成閘極結構120。在一實施例中，在移除位於間隔物112與第一阻隔材料層114a之間的多晶矽條帶106及位於多晶矽條帶106上的硬式罩幕條帶108之後，在間隔物112與第一阻隔材料層114a之間的凹陷內順序地形成閘極介電層122及閘極電極層124。如圖2F及圖2G中所繪示，閘極電極層124及閘極介電層122覆蓋鰭片102的部分，且所覆蓋部分充當通道區（亦標記為102）。在一些實施例中，閘極介電層122的材料包括氧化矽、氮化矽或其組合。在一些實施例中，閘極介電層122包括高介電常數（high-k）介電材料，且高介電常數介電材料具有大於約7.0的k值，且包含金屬氧化物，或Hf、Al、Zr、La、Mg、Ba、Ti、Pb及其組合的矽酸鹽。在一些實施例中，以例如原子層沈積（atomic layer deposition；ALD）、分子束沈積（molecular beam deposition；MBD）、物理氣相沈積（physical vapor deposition；PVD）或熱氧化製程來形成閘極介電層122。在一些實施例中，閘極電極層124包括含金屬的材料，例如Al、Cu、W、Co、Ti、Ta、Ru、TiN、TiAl、TiAlN、TaN、TaC、NiSi、CoSi或其組合。取決於FinFET 20為p型FinFET或n型FinFET，而來選擇閘極介電層122及/或閘極電極層124的材料。視情況，可進行化學機械拋光（chemical mechanical polishing；CMP）製程以移除閘極介電層122及閘極電極層124的多餘部分。間隔物112及第一阻隔材料層114a位於閘極介電層122及閘極電極層124的側壁上。也就是說，堆疊結構110被置換而後續替換形成的閘極結構120兩側處具有間隔物112及第一阻隔材料層114a。在本文中所描述的一些實施例中，閘極結構120為置換式閘極結構，但所述閘極結構或其製造製程並不應受上述實施例所限制。
如圖2F及圖2G所示，在一些實施例中，閘極結構120位於隔離結構103上及基底100上方，且間隔物112及第一阻隔材料層114a位於閘極結構120的相對側壁上。在某些實施例中，應變源極區及汲極區130位於閘極結構120的兩個相對側處並且位於隔離結構103之間，且第二阻隔材料層114b位於應變源極區及汲極區130的頂表面130a上。
因此，由於應變源極區及汲極區130被第二阻隔材料層114b所覆蓋，由高質量富氧氧化物所形成的第二阻隔材料層114b減輕電子或電洞陷阱且減少漏電。歸因於配置於間隔物112上的第一阻隔材料層114a而能夠得到具有低介電常數的間隔物，因此降低寄生電容。FinFET元件的效能並進一步得到提昇。
圖3為繪示根據本發明的一些實施例的用於形成FinFET的製造方法的製程步驟中的一些的例示性流程圖。
儘管方法的步驟經說明且描述為一系列動作或事件，但應瞭解，不應以限制性意義來解譯此等動作或事件的所說明排序。另外，並不需要所有的所說明製程或步驟來實施本發明的一或多個實施例。
在步驟300中，提供具有隔離結構及位於隔離結構之間的鰭片之基底。在步驟302中，在隔離結構上及基底上方形成至少一個堆疊結構。基底可為矽基底或絕緣層上有矽（SOI）基底。在步驟304中，在堆疊結構的側壁上形成側壁間隔物。在步驟306中，在基底中以及在堆疊結構的兩個相對側處形成應變源極區及汲極區。在步驟308中，藉由進行氧化處理，在側壁間隔物上形成第一阻隔材料層，且在應變源極區及汲極區上形成第二阻隔材料層。在步驟310中，在移除堆疊結構之後，在隔離結構上及在基底上方形成至少一個閘極結構。
在上述實施例中，經由氧化處理，導致形成於側壁間隔物上的第一阻隔材料層與形成於應變源極區及汲極區上的第二阻隔材料層包含帶負電荷的高質量富氧氧化物材料。經由氧化處理產生的第一與/或第二阻隔材料層可協助減少電子或電洞陷阱並且具有低介電常數，因此減小結構寄生電容且提高元件操作速度。對於具有第一或第二阻隔材料層的元件，元件的電效能得到提昇。
在本發明的一些實施例中，描述一種鰭式場效電晶體。所述鰭式場效電晶體包括：基底，其具有隔離結構及在隔離結構之間的鰭片；至少一個閘極結構；間隔物；第一阻隔材料層及第二阻隔材料層；以及應變源極區及汲極區。至少一個閘極結構配置於基底上方及隔離結構上。間隔物配置於至少一個閘極結構的側壁上。第一阻隔材料層配置於間隔物上。應變源極區及汲極區配置於至少一個閘極結構的兩個相對側處。第二阻隔材料層配置於應變源極區及汲極區上。第一阻隔材料層及第二阻隔材料層包括富氧氧化物材料。
在本發明的一些實施例中，描述一種鰭式場效電晶體。所述鰭式場效電晶體包括：基底，其具有隔離結構及在隔離結構之間的鰭片；至少一個閘極結構；間隔物；第一阻隔材料層及第二阻隔材料層；以及應變源極區及汲極區。至少一個閘極結構配置於鰭片上方及隔離結構上。間隔物配置於至少一個閘極結構的側壁上。第一阻隔材料層配置於間隔物的表面上。第一阻隔材料層包括帶負電荷層。應變源極區及汲極區配置於至少一個閘極結構的相對側處。第二阻隔材料層配置於應變源極區及汲極區的表面上。第二阻隔材料層包括帶負電荷氧化矽層。
根據本發明一些實施例，所述第一阻隔材料層的氧含量大於所述間隔物的氧含量。根據本發明一些實施例，所述間隔物的材料包括矽碳氮氧化物，且所述第一阻隔材料層的材料包括富氧矽碳氮氧化物。根據本發明一些實施例，所述間隔物的材料包括氧化矽，且所述第一阻隔材料層的材料包括富氧氧化矽。根據本發明一些實施例，其中所述第二阻隔材料層的氧含量大於所述應變源極區及汲極區的氧含量。根據本發明一些實施例，其中所述應變源極區及汲極區的材料包括矽鍺或磷化矽，且所述第二阻隔材料層的材料包括富氧氧化矽。根據本發明一些實施例，其中所述富氧氧化矽由SiOx表示且2.1£x£2.5。
在本發明的一些實施例中，描述一種用於形成鰭式場效電晶體的方法。提供具有隔離結構及位於隔離結構之間的鰭片的基底。在隔離結構上、鰭片上方及基底上方形成至少一個堆疊結構。在至少一個堆疊結構的側壁上形成側壁間隔物。在基底中及在至少一個堆疊結構的兩個相對側處形成應變源極區及汲極區。進行氧化處理，在側壁間隔物上形成第一阻隔材料層，且在應變源極區及汲極區上形成第二阻隔材料層。在移除堆疊結構之後，在隔離結構上、鰭片上方及基底上方形成至少一個閘極結構。
根據本發明一些實施例，其中進行所述氧化處理包括在範圍為25℃至600℃的操作溫度下進行低溫自由基氧化處理。根據本發明一些實施例，其中進行所述氧化處理包括使用含氧的至少一種氣體進行電漿處理。根據本發明一些實施例，其中在所述間隔物上形成所述第一阻隔材料層以及在所述應變源極區及汲極區上形成所述第二阻隔材料層包括以所述電漿處理來處理所述間隔物及所述應變源極區及汲極區的表面，而形成包含富氧氧化物材料的所述第一阻隔材料層以及所述第二阻隔材料層。根據本發明一些實施例，其中在所述間隔物上形成所述第一阻隔材料層以及在所述應變源極區及汲極區上形成所述第二阻隔材料層包括以所述電漿處理來處理所述間隔物及所述應變源極區及汲極區的表面，而形成包含帶負電荷層的所述第一阻隔材料層以及所述第二阻隔材料層。根據本發明一些實施例，其中在所述間隔物上形成所述第一阻隔材料層包括在所述間隔物上形成富氧矽碳氮氧化物層。根據本發明一些實施例，其中在所述應變源極區及汲極區上形成所述第二阻隔材料層包括在所述應變源極區及汲極區中形成富氧氧化矽層。
前文概述數個實施例的特徵，使得熟習此項技術者可較佳地理解本發明的態樣。熟習此項技術者應理解，其可易於使用本發明作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。熟習此項技術者亦應認識到，此類等效構造並不脫離本發明的精神及範疇，且其可在不脫離本發明的精神及範疇的情況下在本文中進行各種改變、替代以及更改。
20‧‧‧FinFET100‧‧‧基底102‧‧‧通道區/鰭片103‧‧‧隔離結構104‧‧‧氧化物層105‧‧‧凹陷106‧‧‧多晶矽條帶108‧‧‧硬式罩幕條帶110‧‧‧堆疊結構110b‧‧‧側壁112‧‧‧間隔物112b‧‧‧表面114a‧‧‧第一阻隔材料層114b‧‧‧第二阻隔材料層120‧‧‧閘極結構122‧‧‧閘極介電層124‧‧‧閘極電極層130‧‧‧應變源極區及汲極區130a‧‧‧頂表面
當結合附圖閱讀時，自以下實施方式最好地理解本發明的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，為論述清楚起見，可任意增大或減小各種特徵的尺寸。 圖1繪示根據本發明的一些實施例的例示性鰭式場效電晶體（FinFET）的立體圖。 圖2A至圖2G為繪示根據本發明的一些實施例之形成FinFET的製造方法的各種階段之FinFET的剖面圖及立體圖。 圖3為繪示根據本發明的一些實施例之形成FinFET的製造方法的製程步驟的例示性流程圖。
20‧‧‧鰭式場效電晶體
100‧‧‧基底
103‧‧‧隔離結構
112‧‧‧間隔物
114a‧‧‧第一阻隔材料層
114b‧‧‧第二阻隔材料層
120‧‧‧閘極結構
122‧‧‧閘極介電層
124‧‧‧閘極電極層
130‧‧‧應變源極區及汲極區

Claims (10)

  1. 一種鰭式場效電晶體，其包括：基底，所述基底具有隔離結構及在所述隔離結構之間的鰭片；至少一個閘極結構，其配置於所述基底上方及所述隔離結構上；間隔物，其配置於所述至少一個閘極結構的側壁上；第一阻隔材料層，其配置於所述間隔物上；應變源極區及汲極區，其配置於所述至少一個閘極結構的相對側處；以及第二阻隔材料層，其配置於所述應變源極區及汲極區上，其中所述第一阻隔材料層及所述第二所述包括富氧氧化物材料，其中所述第一與第二阻隔材料層的氧含量大於所述間隔物的氧含量，其中所述間隔物的材料包括矽碳氮氧化物且所述第一阻隔材料層的材料包括富氧矽碳氮氧化物，或者其中所述間隔物的材料包括氧化矽且所述第一阻隔材料層的材料包括富氧氧化矽。
  2. 如申請專利範圍第1項所述的電晶體，其中所述第二阻隔材料層的氧含量大於所述應變源極區及汲極區的氧含量。
  3. 如申請專利範圍第2項所述的電晶體，其中所述應變源極區及汲極區的材料包括矽鍺或磷化矽，且所述第二阻隔材料層的材料包括富氧氧化矽。
  4. 如申請專利範圍第3項所述的電晶體，其中所述富氧氧化矽由SiOx表示且2.1
    Figure 105139817-A0305-02-0018-1
    x
    Figure 105139817-A0305-02-0018-2
    2.5。
  5. 一種鰭式場效電晶體，其包括：基底，其具有隔離結構及在所述隔離結構之間的鰭片；至少一個閘極結構，其配置於所述鰭片上方及所述隔離結構上；間隔物，其配置於所述至少一個閘極結構的側壁上；第一阻隔材料層，其配置於所述間隔物的表面上，其中所述第一阻隔材料層包括帶負電荷層；應變源極區及汲極區，其配置於所述至少一個閘極結構的相對側處；以及第二阻隔材料層，其配置於所述應變源極區及汲極區的表面上，其中所述第二阻隔材料層包括帶負電荷氧化矽層，所述第二阻隔材料層的氧含量大於所述應變源極區及汲極區的氧含量。
  6. 如申請專利範圍第5項所述的電晶體，其中所述第一阻隔材料層的氧含量大於所述間隔物的氧含量。
  7. 如申請專利範圍第6項所述的電晶體，其中所述間隔物的材料包括矽碳氮氧化物，且所述帶負電荷層包括富氧矽碳氮氧化物。
  8. 如申請專利範圍第6項所述的電晶體，其中所述間隔物的材料包括氧化矽，且所述帶負電荷層包括富氧氧化矽。
  9. 如申請專利範圍第5項所述的電晶體，其中所述應變源極區及汲極區的材料包括矽鍺或磷化矽，且所述帶負電荷氧化矽層的材料由SiOx表示且2.1
    Figure 105139817-A0305-02-0019-3
    x
    Figure 105139817-A0305-02-0019-4
    2.5。
  10. 一種用於形成鰭式場效電晶體的方法，其包括：提供具有隔離結構及位於所述隔離結構之間的鰭片的基底； 在所述隔離結構上及所述鰭片上方形成至少一個堆疊結構；在所述至少一個堆疊結構的側壁上形成間隔物；在所述基底中及在所述至少一個堆疊結構的兩個相對側處形成應變源極區及汲極區；藉由對所述間隔物與所述應變源極區及汲極區的表面進行氧化處理，在所述間隔物上形成第一阻隔材料層而無覆蓋所述隔離結構，且在所述應變源極區及汲極區上形成第二阻隔材料層而無覆蓋所述隔離結構；以及在移除所述至少一個堆疊結構之後，在所述隔離結構上及所述鰭片上方形成至少一個閘極結構。
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