CN108807506A - 带沟槽栅结构的深槽超结mosfet器件及其加工工艺 - Google Patents
带沟槽栅结构的深槽超结mosfet器件及其加工工艺 Download PDFInfo
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Abstract
本发明涉及功率器件技术领域,尤其涉及一种带沟槽栅结构的深槽超结MOSFET器件,其结构包括N+型衬底、N‑型外延层、P型柱深槽结构、P型体区、P+有源区、N+有源区、栅极氧化层、多晶硅栅极、介质层、源极金属;本发明所述的带沟槽栅结构的深槽超结MOSFET器件采用沟槽栅结构,且沟槽栅位于P型柱深槽结构正上方,P型柱深槽结构位于N‑外延层内,该结构既保留了深槽超结MOSFET器件横向耗尽快,耐压高的特点,同时又具有沟槽栅屏蔽JFET电阻的特点,从而提高了超结MOSFET器件的功率密度。
Description
技术领域
本发明涉及功率器件技术领域,尤其涉及一种带沟槽栅结构的深槽超结MOSFET器件及其加工工艺。
背景技术
目前现有的普通VDMOS器件,其结构如图1所示,包括N+型衬底11、N-型外延层12、P型体区(即pbody)13、P+有源区14、N+有源区15、栅氧化层16、多晶硅栅极(即poly gate)17、介质层18和源极金属19,这种结构的VDMOS器件需要提高耐压值时,一般通过增加N-型外延层的电阻率和N-型外延层的厚度实现,但这种方法会导致导通电阻的增加,降低器件的性能。因此,在需要较高耐压的场合,普遍用平面栅深槽超结MOSFET器件代替普通的VDMOS器件。
目前现有的平面栅深槽超结MOSFET器件的结构如图2所示,包括N+型衬底21、N-型外延层22、P型柱深槽结构(即Ptype trench pillar)23、P型体区(pbody)24、P+有源区25、N+有源区26、平面栅氧化层27、多晶硅栅极(即poly gate)28、介质层29和源极金属20。平面栅深槽超结通过在器件内部引入P型柱深槽结构,P型柱深槽结构与N-型外延层之间的PN结反偏时,P型柱深槽结构可以加速N-型外延层耗尽速度,从而可以在更低电阻率的N-外延层中实现高耐压低导通的效果。但平面栅深槽超结的P型体区引入了JFET电阻,P型体区之间的距离越近,JFET电阻对导通电阻的影响越大,需要通过增加注入的方式来缓解导通电阻的升高。P型体区之间的JFET效应制约了P型柱深槽结构的间距减小,制约了N-外延电阻率的进一步减小,制约了同等耐压下导通电阻的进一步降低,制约了超结功率密度的提升。
发明内容
针对现有技术中的问题,本发明提供一种带沟槽栅结构的深槽超结MOSFET器件及其加工工艺。
为实现以上技术目的,本发明的技术方案是:
一种带沟槽栅结构的深槽超结MOSFET器件,包括N+型衬底;
所述N+型衬底上表面形成有N-型外延层;
所述N-型外延层内部中部形成有多个P型柱深槽结构,所述P型柱深槽结构包括柱形深槽结构和位于柱形深槽结构内的P型多晶硅,所述P型柱深槽结构的方向为自N-型外延层顶部向下,相邻的P型柱深槽结构之间相分离;
所述N-型外延层内部上部形成有多个沟槽栅结构,每个沟槽栅结构位于P形柱深槽结构的上方且相邻的沟槽栅结构之间相分离,所述沟槽栅结构包括沟槽结构和N型多晶硅栅极,所述沟槽结构的内表面形成有栅极氧化层,所述N型多晶硅栅极位于沟槽结构内;
所述N-型外延层内部上部形成有P型体区,所述P型体区位于相邻的沟槽栅结构之间,所述P型体区的结深不超过沟槽栅结构的底部,所述P型体区的顶部沿水平方向依次形成有N+有源区、P+有源区、N+有源区;
所述沟槽栅结构、N+有源区、P+有源区的上方形成有金属层,所述金属层与沟槽栅结构之间形成有介质层,所述金属层与N+有源区、P+有源区连接,形成源极金属。
一种带沟槽栅结构的深槽超结MOSFET器件的加工工艺,具体步骤包括:
步骤A:准备EPI衬底,EPI衬底包括N+型衬底及位于N+型衬底上表面的N-型外延层;
步骤B:对N-型外延层表面进行牺牲氧化,形成牺牲氧化层;
步骤C:去除上表面的牺牲氧化层;
步骤D:在N-型外延层上表面沉积薄膜;
步骤E:利用光刻工艺对沉积薄膜后的N-型外延层上表面的部分区域进行光刻处理,利用刻蚀工艺自上而下形成多个柱形深槽结构,柱形深槽结构之间相分离;
步骤F:将P型多晶硅填入柱形深槽结构并填平,形成P型柱深槽结构;
步骤G:填平后,在N-型外延层上表面和P型柱深槽结构的上表面沉积薄膜;
步骤H:利用光刻工艺对沉积薄膜后的N-型外延层上表面的部分区域进行光刻处理,刻蚀形成多个沟槽结构,每个沟槽结构位于一个P型柱深槽结构的上方,相邻的沟槽结构之间相分离;
步骤I:对沟槽结构的内表面进行热氧化处理,形成栅极氧化层;
步骤J:将N型多晶硅填入沟槽结构内且填平,形成多晶硅栅极,进而形成沟槽栅结构;
步骤K:在相邻沟槽结构之间的区域内通过注入P型杂质并推阱形成P型体区,P型体区的结深不超过沟槽结构底部,形成P型体区;
步骤L:在PB的上表面沿水平方向依次注入N型重掺杂、P型重掺杂、N型重掺杂,依次形成N+有源区、P+有源区和N+有源区;
步骤M:在多晶硅栅极、P+有源区和N+有源区的上表面沉积绝缘层,作为介质层;
步骤N:利用光刻工艺对介质层的部分区域进行光刻处理,刻蚀去除位于P+有源区和N+有源区的上表面的绝缘层,以形成金属接触孔区域;
步骤O:在介质层表面和金属接触孔区域表面沉积金属层,所述金属层通过金属接触孔区域与P+有源区和N+有源区连接形成源极金属;
步骤P:减薄背金,加工完成。
从以上描述可以看出,本发明具备以下优点:
本发明所述的带沟槽栅结构的深槽超结MOSFET器件采用沟槽栅结构,沟槽栅位于P型柱深槽结构正上方,P型柱深槽结构位于N-外延层内,该结构既保留了深槽超结MOSFET器件横向耗尽快、耐压高的特点,同时又具有沟槽栅屏蔽JFET电阻的特点,从而提高了超结MOSFET器件的功率密度。
附图说明
图1是现有的普通VDMOS器件的结构示意图;
图2是现有的平面栅深槽超结器件结构示意图;
图3是本发明的结构示意图;
附图标记:
图1中:11.N+型衬底、12.N-型外延层、13.P型体区、14.P+有源区、15.N+有源区、16.栅氧化层、17.多晶硅栅极、18.介质层、19.源极金属;
图2中:21.N+型衬底、22.N-型外延层、23.P型柱深槽结构、24.P型体区、25.P+有源区、26.N+有源区、27.平面栅氧化层、28.多晶硅栅极、29.介质层、20.源极金属;
图3中:31.N+型衬底、32.N-型外延层、33.P型柱深槽结构、34.P型体区、35.P+有源区、36.N+有源区、37.栅极氧化层、38.多晶硅栅极、39.介质层、30.源极金属。
具体实施方式
结合图3,详细说明本发明的一个具体实施例,但不对本发明的权利要求做任何限定。
如图3所示,一种带沟槽栅结构的深槽超结MOSFET器件,包括N+型衬底31,N+型衬底31上表面形成有N-型外延层32,N-型外延层32内部中部形成有多个P型柱深槽结构33,P型柱深槽结构33包括柱形深槽结构和位于柱形深槽结构内的P型多晶硅,P型柱深槽结构33的方向为自N-型外延层顶部向下,相邻的P型柱深槽结构33之间相分离,N-型外延层32内部上部形成有多个沟槽栅结构,每个沟槽栅结构位于P形柱深槽结构33的上方且相邻的沟槽栅结构之间相分离,沟槽栅结构包括沟槽结构和N型多晶硅栅极38,沟槽结构的内表面形成有栅极氧化层37,N型多晶硅栅极38位于沟槽结构内,N-型外延层内部上部形成有P型体区34,P型体区34位于相邻的沟槽栅结构之间,P型体区34的结深不超过沟槽栅结构的底部,P型体区34的顶部沿水平方向依次形成有N+有源区35、P+有源区36、N+有源区35,沟槽栅结构、N+有源区、P+有源区的上方形成有金属层,金属层与沟槽栅结构之间形成有介质层39,金属层与N+有源区、P+有源区连接,形成源极金属30。
上述带沟槽栅结构的深槽超结MOSFET器件的加工工艺为:
步骤A:准备EPI衬底,EPI衬底包括N+型衬底及位于N+型衬底上表面的N-型外延层;
步骤B:对N-型外延层表面进行牺牲氧化,形成牺牲氧化层;
步骤C:去除上表面的牺牲氧化层;
步骤D:在N-型外延层上表面沉积薄膜;
步骤E:利用光刻工艺对沉积薄膜后的N-型外延层上表面的部分区域进行光刻处理,利用刻蚀工艺自上而下形成多个柱形深槽结构,柱形深槽结构之间相分离,多个柱形深槽结构形成的布局可以为品字形、田字形、六边形、长条形等常用的半导体行业的布局设计;
步骤F:将P型多晶硅填入柱形深槽结构并填平,形成P型柱深槽结构;
步骤G:填平后,在N-型外延层上表面和P型柱深槽结构的上表面沉积薄膜;
步骤H:利用光刻工艺对沉积薄膜后的N-型外延层上表面的部分区域进行光刻处理,刻蚀形成多个沟槽结构,每个沟槽结构位于一个P型柱深槽结构的上方,相邻的沟槽结构之间相分离;
步骤I:对沟槽结构的内表面进行热氧化处理,形成栅极氧化层;
步骤J:将N型多晶硅填入沟槽结构内且填平,形成多晶硅栅极,进而形成沟槽栅结构;
步骤K:在相邻沟槽结构之间的区域内通过注入P型杂质并推阱形成P型体区,P型体区的结深不超过沟槽结构底部,形成P型体区;
步骤L:在PB的上表面沿水平方向依次注入N型重掺杂、P型重掺杂、N型重掺杂,依次形成N+有源区、P+有源区和N+有源区;
步骤M:在多晶硅栅极、P+有源区和N+有源区的上表面沉积绝缘层,作为介质层;
步骤N:利用光刻工艺对介质层的部分区域进行光刻处理,刻蚀去除位于P+有源区和N+有源区的上表面的绝缘层,以形成金属接触孔区域;
步骤O:在介质层表面和金属接触孔区域表面沉积金属层,所述金属层通过金属接触孔区域与P+有源区和N+有源区连接形成源极金属;
步骤P:减薄背金,加工完成。
本发明所述的带沟槽栅结构的深槽超结MOSFET器件采用沟槽栅结构,且沟槽栅位于P型柱深槽结构正上方,P型柱深槽结构位于N-外延层内,该结构既保留了深槽超结MOSFET器件横向耗尽快、耐压高的特点,同时又具有沟槽栅屏蔽JFET电阻的特点,从而提高了超结MOSFET器件的功率密度。
综上所述,本发明具有以下优点:
本发明所述的带沟槽栅结构的深槽超结MOSFET器件既具有深槽超结MOSFET器件横向耗尽快、耐压高的特点,又具有沟槽栅屏蔽JFET电阻的特点,进而提高了超结MOSFET器件的功率密度。
可以理解的是,以上关于本发明的具体描述,仅用于说明本发明而并非受限于本发明实施例所描述的技术方案。本领域的普通技术人员应当理解,仍然可以对本发明进行修改或等同替换,以达到相同的技术效果;只要满足使用需要,都在本发明的保护范围之内。
Claims (2)
1.一种带沟槽栅结构的深槽超结MOSFET器件,其特征在于:包括N+型衬底;
所述N+型衬底上表面形成有N-型外延层;
所述N-型外延层内部中部形成有多个P型柱深槽结构,所述P型柱深槽结构包括柱形深槽结构和位于柱形深槽结构内的P型多晶硅,所述P型柱深槽结构的方向为自N-型外延层顶部向下,相邻的P型柱深槽结构之间相分离;
所述N-型外延层内部上部形成有多个沟槽栅结构,每个沟槽栅结构位于P形柱深槽结构的上方且相邻的沟槽栅结构之间相分离,所述沟槽栅结构包括沟槽结构和N型多晶硅栅极,所述沟槽结构的内表面形成有栅极氧化层,所述N型多晶硅栅极位于沟槽结构内;
所述N-型外延层内部上部形成有P型体区,所述P型体区位于相邻的沟槽栅结构之间,所述P型体区的结深不超过沟槽栅结构的底部,所述P型体区的顶部沿水平方向依次形成有N+有源区、P+有源区、N+有源区;
所述沟槽栅结构、N+有源区、P+有源区的上方形成有金属层,所述金属层与沟槽栅结构之间形成有介质层,所述金属层与N+有源区、P+有源区连接,形成源极金属。
2.一种带沟槽栅结构的深槽超结MOSFET器件的加工工艺,具体步骤包括:
步骤A:准备EPI衬底,EPI衬底包括N+型衬底及位于N+型衬底上表面的N-型外延层;
步骤B:对N-型外延层表面进行牺牲氧化,形成牺牲氧化层;
步骤C:去除上表面的牺牲氧化层;
步骤D:在N-型外延层上表面沉积薄膜;
步骤E:利用光刻工艺对沉积薄膜后的N-型外延层上表面的部分区域进行光刻处理,利用刻蚀工艺自上而下形成多个柱形深槽结构,柱形深槽结构之间相分离;
步骤F:将P型多晶硅填入柱形深槽结构并填平,形成P型柱深槽结构;
步骤G:填平后,在N-型外延层上表面和P型柱深槽结构的上表面沉积薄膜;
步骤H:利用光刻工艺对沉积薄膜后的N-型外延层上表面的部分区域进行光刻处理,刻蚀形成多个沟槽结构,每个沟槽结构位于一个P型柱深槽结构的上方,相邻的沟槽结构之间相分离;
步骤I:对沟槽结构的内表面进行热氧化处理,形成栅极氧化层;
步骤J:将N型多晶硅填入沟槽结构内且填平,形成多晶硅栅极,进而形成沟槽栅结构;
步骤K:在相邻沟槽结构之间的区域内通过注入P型杂质并推阱形成P型体区,P型体区的结深不超过沟槽结构底部,形成P型体区;
步骤L:在PB的上表面沿水平方向依次注入N型重掺杂、P型重掺杂、N型重掺杂,依次形成N+有源区、P+有源区和N+有源区;
步骤M:在多晶硅栅极、P+有源区和N+有源区的上表面沉积绝缘层,作为介质层;
步骤N:利用光刻工艺对介质层的部分区域进行光刻处理,刻蚀去除位于P+有源区和N+有源区的上表面的绝缘层,以形成金属接触孔区域;
步骤O:在介质层表面和金属接触孔的区域表面沉积金属层,所述金属层通过金属接触孔区域与P+有源区和N+有源区连接形成源极金属;
步骤P:减薄背金,加工完成。
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