JP5583846B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5583846B2 JP5583846B2 JP2013508733A JP2013508733A JP5583846B2 JP 5583846 B2 JP5583846 B2 JP 5583846B2 JP 2013508733 A JP2013508733 A JP 2013508733A JP 2013508733 A JP2013508733 A JP 2013508733A JP 5583846 B2 JP5583846 B2 JP 5583846B2
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- 239000004065 semiconductor Substances 0.000 title claims description 122
- 239000012535 impurity Substances 0.000 claims description 124
- 239000010410 layer Substances 0.000 claims description 65
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 35
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 15
- 239000002344 surface layer Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 description 28
- 238000000034 method Methods 0.000 description 25
- 150000002500 ions Chemical class 0.000 description 18
- 230000005684 electric field Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 8
- 239000013078 crystal Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- 230000005465 channeling Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Description
また、2段階の傾斜構造を有するアライメントマークは、知られていた(例えば、特許文献6など)。
また、この発明は、イオン注入の工程およびフォトリソグラフィー工程の数を増加させないで、半導体装置の終端構造を容易に製造できる製造方法を提供することを目的とする。
まず、本発明の実施の形態1における半導体装置の構成を説明する。図1は、本発明の実施の形態1における半導体装置を示す断面模式図である。
アノード電極18の端部から所定の距離だけ離れた外側のドリフト層2の表層部には、リセス(掘り込み)部31が設けられており、アノード電極18の端部からリセス部31の底部にわたって不純物領域13が形成されている。
図2において、アノード電極18が形成された素子領域の周囲に終端構造と呼ばれる電界緩和構造が形成されている。不純物領域13は、アノード電極18の端部の下部、すなわち、リセス部31の内側(素子領域側)から、リセス部31の底部の中程までリング状に形成されている。また、アライメントマーク30は、リセス部31の外側に、孤立して形成されている。
さらに、絶縁膜17は、SiNやSiO2などの無機系絶縁膜であってもよいし、ポリイミドなどの有機系絶縁膜であってもよい。
エッチングは、反応性イオンエッチング(RIE)などのドライエッチング法で行えばよい。また、リセス部31およびアライメントマーク30となるリセス構造のエッチングの深さは、同じ深さで、アライメントマークとして読み取りが容易になるように0.1μm以上とする。
ここで、平坦化膜52の膜厚は、リセス部31以外の箇所でも平坦化膜52が塗布されるように、リセス部31の深さより大きくする。望ましくは、平坦化膜52の膜厚は、リセス構造のないところで、リセス構造の深さ程度の2倍以内などであればよく、例えば、0.1〜0.8μmなどであればよい。
また、ドリフト層2の材料である炭化珪素半導体と平坦化膜52との間にイオンの透過率に差があると、リセス部31と、リセス構造のない箇所で、イオンが到達する絶対深さに違いが生じ、第1不純物領域13aの底面と第2不純物領域13bの底面の深さが異なって形成される。例えば、平坦化膜52が結晶構造を持たず、ドリフト層2が結晶構造を持つ場合、リセス構造のない箇所の平坦化膜52が薄く、ドリフト層2の結晶面によっては注入イオンのチャネリングの影響により、第1不純物領域13aの底面の方が第2不純物領域13bの底面より深く形成される場合がある。
本発明の実施の形態2における半導体装置である炭化珪素ショットキ障壁ダイオードの構成を説明する。図6は、本発明の実施の形態2における炭化珪素ショットキ障壁ダイオードを示す断面模式図である。
本実施の形態の半導体装置においては、実施の形態1の半導体装置ではリセス部31およびアライメントマーク30のリセス構造の側面がドリフト層2の表面に対して垂直に形成されていたところをテーパー形状にしている。その他の部分については、実施の形態1で説明したものと同様であるので詳しい説明を省略する。
また、リセス構造のさらに外側のドリフト層2の表層部には、アライメントマーク30となる、側面がテーパー形状のリセス構造が設けられている。
本発明の実施の形態3における半導体装置である炭化珪素ショットキ障壁ダイオードの構成を説明する。図8は、本発明の実施の形態3における半導体装置を示す断面模式図である。
本実施の形態の半導体装置においては、実施の形態2の半導体装置では1段だったリセス構造を2段にしている。その他の部分については、実施の形態2で説明したものと同様であるので詳しい説明を省略する。
また、不純物面密度は、第3不純物領域13c、第4不純物領域13d、第5不純物領域13eの順に小さくなっている。
レジストマスク53には、不純物領域13に対応する箇所に開口を設けておく。
さらに、本実施の形態の半導体装置のように、リセス構造の側面をテーパー形状にすることにより、3段階の面密度の不純物領域の間に不純物面密度の遷移領域を形成できるので、より高い電界緩和構造を有する終端構造の半導体装置を得ることができる。
発明の実施の形態4における半導体装置の構成を説明する。図10は、本発明の実施の形態4における半導体装置を示す断面模式図である。
本実施の形態の半導体装置においては、実施の形態1乃至3ではショットキ障壁ダイオードであった半導体素子を金属・酸化膜・半導体電界効果トランジスタ(MOSFET:Metal Oxide Semiconductor Field Effect Transistor)としている。その他の部分については、実施の形態1および2で説明したものと同様であるので詳しい説明を省略する。
リセス部31の上部には層間絶縁膜7と同じ絶縁膜が形成されている。
炭化珪素半導体はイオン注入後の活性化アニール温度を高くする必要があり、アライメントマークをリセス構造にする必要性が高いので、本発明を炭化珪素半導体に適用すると、工程削減の効果が大きく、より大きな効果を奏する。また、炭化珪素半導体は、不純物が他の材料の半導体より拡散しにくいため、本発明を用いて不純物領域を形成すると、他の材料の半導体に適用した場合より、不純物領域の不純物濃度分布を意図的に形成する効果が顕著であり、電界緩和特性の改善の点において、より大きな効果を奏する。
Claims (12)
- 炭化珪素で形成された半導体基板の第1の主面上に形成された炭化珪素で形成された第1導電型のドリフト層と、
前記ドリフト層の表層部に形成された素子領域と、
前記素子領域から所定の間隔をおいて外側の前記ドリフト層にリング状に形成された、側壁がドリフト層表面に対してテーパー形状であるリセス部と、
前記リセス部の底部から前記リセス部の内側にわたって形成され、前記リセス部のある箇所の厚さが前記リセス部のない箇所の厚さより小さく、該領域の側面が前記ドリフト層表面に対して垂直である第2導電型の不純物領域と
を備えたことを特徴とする半導体装置。 - 半導体基板およびドリフト層が炭化珪素で形成され、リセス部の外側のドリフト層にリセス構造のアライメントマークが形成されたことを特徴とする請求項1に記載の半導体装置。
- リセス部とアライメントマークの深さが同じであることを特徴とする請求項2に記載の半導体装置。
- リセス部のある箇所より前記リセス部のない箇所で、不純物領域の底のドリフト層の表面からの深さが深いことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- リセス部のある箇所と前記リセス部のない箇所との不純物領域の底のドリフト層の表面からの深さが同じであることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- リセス部のある箇所より前記リセス部のない箇所で、不純物領域の底のドリフト層の表面からの深さが浅いことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- リセス部が2段のリセス構造を備えたことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- リセスの深さの大きい箇所よりリセスの深さの小さい箇所で、不純物領域の底のドリフト層の表面からの深さが深いことを特徴とする請求項7に記載の半導体装置。
- リセスの深さの大きい箇所と前記リセスの深さの小さい箇所とで不純物領域の底のドリフト層の表面からの深さが同じであることを特徴とする請求項7に記載の半導体装置。
- リセスの深さの大きい箇所よりリセスの深さの小さい箇所で、不純物領域の底のドリフト層の表面からの深さが浅いことを特徴とする請求項7に記載の半導体装置。
- 素子領域に形成された素子がショットキバリアダイオードであり、
ドリフト層の表面上に形成されたショットキ電極と、
半導体基板の第2の主面に接したオーミック電極と、
リセス構造の上部に形成された絶縁膜と
を備えたことを特徴とする請求項1乃至10のいずれか1項に記載の半導体装置。 - 素子領域に形成された素子がMOSFETであり、
ドリフト層の表層部に形成された複数の第2導電型のウェル領域と、
前記ウェル領域の表層の一部の形成された第1導電型のソース領域と、
前記ウェル領域の上部にゲート絶縁膜を間に介して形成されたゲート電極と、
前記ソース領域および前記ウェル領域と接続されたソース電極と、
半導体基板の第2の主面に接して形成されたオーミック電極と、
最も外側に位置する前記ウェル領域とつながった不純物領域と、
リセス構造の上部に形成された絶縁膜と
を備えたことを特徴とする請求項1乃至10のいずれか1項に記載の半導体装置。
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