JP5583846B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5583846B2 JP5583846B2 JP2013508733A JP2013508733A JP5583846B2 JP 5583846 B2 JP5583846 B2 JP 5583846B2 JP 2013508733 A JP2013508733 A JP 2013508733A JP 2013508733 A JP2013508733 A JP 2013508733A JP 5583846 B2 JP5583846 B2 JP 5583846B2
- Authority
- JP
- Japan
- Prior art keywords
- recess
- drift layer
- semiconductor device
- region
- impurity region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 122
- 239000012535 impurity Substances 0.000 claims description 124
- 239000010410 layer Substances 0.000 claims description 65
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 35
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 15
- 239000002344 surface layer Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 description 28
- 238000000034 method Methods 0.000 description 25
- 150000002500 ions Chemical class 0.000 description 18
- 230000005684 electric field Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 8
- 239000013078 crystal Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- 230000005465 channeling Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
また、2段階の傾斜構造を有するアライメントマークは、知られていた(例えば、特許文献6など)。
また、この発明は、イオン注入の工程およびフォトリソグラフィー工程の数を増加させないで、半導体装置の終端構造を容易に製造できる製造方法を提供することを目的とする。
まず、本発明の実施の形態1における半導体装置の構成を説明する。図1は、本発明の実施の形態1における半導体装置を示す断面模式図である。
アノード電極18の端部から所定の距離だけ離れた外側のドリフト層2の表層部には、リセス(掘り込み)部31が設けられており、アノード電極18の端部からリセス部31の底部にわたって不純物領域13が形成されている。
図2において、アノード電極18が形成された素子領域の周囲に終端構造と呼ばれる電界緩和構造が形成されている。不純物領域13は、アノード電極18の端部の下部、すなわち、リセス部31の内側(素子領域側)から、リセス部31の底部の中程までリング状に形成されている。また、アライメントマーク30は、リセス部31の外側に、孤立して形成されている。
さらに、絶縁膜17は、SiNやSiO2などの無機系絶縁膜であってもよいし、ポリイミドなどの有機系絶縁膜であってもよい。
エッチングは、反応性イオンエッチング(RIE)などのドライエッチング法で行えばよい。また、リセス部31およびアライメントマーク30となるリセス構造のエッチングの深さは、同じ深さで、アライメントマークとして読み取りが容易になるように0.1μm以上とする。
ここで、平坦化膜52の膜厚は、リセス部31以外の箇所でも平坦化膜52が塗布されるように、リセス部31の深さより大きくする。望ましくは、平坦化膜52の膜厚は、リセス構造のないところで、リセス構造の深さ程度の2倍以内などであればよく、例えば、0.1〜0.8μmなどであればよい。
また、ドリフト層2の材料である炭化珪素半導体と平坦化膜52との間にイオンの透過率に差があると、リセス部31と、リセス構造のない箇所で、イオンが到達する絶対深さに違いが生じ、第1不純物領域13aの底面と第2不純物領域13bの底面の深さが異なって形成される。例えば、平坦化膜52が結晶構造を持たず、ドリフト層2が結晶構造を持つ場合、リセス構造のない箇所の平坦化膜52が薄く、ドリフト層2の結晶面によっては注入イオンのチャネリングの影響により、第1不純物領域13aの底面の方が第2不純物領域13bの底面より深く形成される場合がある。
本発明の実施の形態2における半導体装置である炭化珪素ショットキ障壁ダイオードの構成を説明する。図6は、本発明の実施の形態2における炭化珪素ショットキ障壁ダイオードを示す断面模式図である。
本実施の形態の半導体装置においては、実施の形態1の半導体装置ではリセス部31およびアライメントマーク30のリセス構造の側面がドリフト層2の表面に対して垂直に形成されていたところをテーパー形状にしている。その他の部分については、実施の形態1で説明したものと同様であるので詳しい説明を省略する。
また、リセス構造のさらに外側のドリフト層2の表層部には、アライメントマーク30となる、側面がテーパー形状のリセス構造が設けられている。
本発明の実施の形態3における半導体装置である炭化珪素ショットキ障壁ダイオードの構成を説明する。図8は、本発明の実施の形態3における半導体装置を示す断面模式図である。
本実施の形態の半導体装置においては、実施の形態2の半導体装置では1段だったリセス構造を2段にしている。その他の部分については、実施の形態2で説明したものと同様であるので詳しい説明を省略する。
また、不純物面密度は、第3不純物領域13c、第4不純物領域13d、第5不純物領域13eの順に小さくなっている。
レジストマスク53には、不純物領域13に対応する箇所に開口を設けておく。
さらに、本実施の形態の半導体装置のように、リセス構造の側面をテーパー形状にすることにより、3段階の面密度の不純物領域の間に不純物面密度の遷移領域を形成できるので、より高い電界緩和構造を有する終端構造の半導体装置を得ることができる。
発明の実施の形態4における半導体装置の構成を説明する。図10は、本発明の実施の形態4における半導体装置を示す断面模式図である。
本実施の形態の半導体装置においては、実施の形態1乃至3ではショットキ障壁ダイオードであった半導体素子を金属・酸化膜・半導体電界効果トランジスタ(MOSFET:Metal Oxide Semiconductor Field Effect Transistor)としている。その他の部分については、実施の形態1および2で説明したものと同様であるので詳しい説明を省略する。
リセス部31の上部には層間絶縁膜7と同じ絶縁膜が形成されている。
炭化珪素半導体はイオン注入後の活性化アニール温度を高くする必要があり、アライメントマークをリセス構造にする必要性が高いので、本発明を炭化珪素半導体に適用すると、工程削減の効果が大きく、より大きな効果を奏する。また、炭化珪素半導体は、不純物が他の材料の半導体より拡散しにくいため、本発明を用いて不純物領域を形成すると、他の材料の半導体に適用した場合より、不純物領域の不純物濃度分布を意図的に形成する効果が顕著であり、電界緩和特性の改善の点において、より大きな効果を奏する。
Claims (12)
- 炭化珪素で形成された半導体基板の第1の主面上に形成された炭化珪素で形成された第1導電型のドリフト層と、
前記ドリフト層の表層部に形成された素子領域と、
前記素子領域から所定の間隔をおいて外側の前記ドリフト層にリング状に形成された、側壁がドリフト層表面に対してテーパー形状であるリセス部と、
前記リセス部の底部から前記リセス部の内側にわたって形成され、前記リセス部のある箇所の厚さが前記リセス部のない箇所の厚さより小さく、該領域の側面が前記ドリフト層表面に対して垂直である第2導電型の不純物領域と
を備えたことを特徴とする半導体装置。 - 半導体基板およびドリフト層が炭化珪素で形成され、リセス部の外側のドリフト層にリセス構造のアライメントマークが形成されたことを特徴とする請求項1に記載の半導体装置。
- リセス部とアライメントマークの深さが同じであることを特徴とする請求項2に記載の半導体装置。
- リセス部のある箇所より前記リセス部のない箇所で、不純物領域の底のドリフト層の表面からの深さが深いことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- リセス部のある箇所と前記リセス部のない箇所との不純物領域の底のドリフト層の表面からの深さが同じであることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- リセス部のある箇所より前記リセス部のない箇所で、不純物領域の底のドリフト層の表面からの深さが浅いことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- リセス部が2段のリセス構造を備えたことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- リセスの深さの大きい箇所よりリセスの深さの小さい箇所で、不純物領域の底のドリフト層の表面からの深さが深いことを特徴とする請求項7に記載の半導体装置。
- リセスの深さの大きい箇所と前記リセスの深さの小さい箇所とで不純物領域の底のドリフト層の表面からの深さが同じであることを特徴とする請求項7に記載の半導体装置。
- リセスの深さの大きい箇所よりリセスの深さの小さい箇所で、不純物領域の底のドリフト層の表面からの深さが浅いことを特徴とする請求項7に記載の半導体装置。
- 素子領域に形成された素子がショットキバリアダイオードであり、
ドリフト層の表面上に形成されたショットキ電極と、
半導体基板の第2の主面に接したオーミック電極と、
リセス構造の上部に形成された絶縁膜と
を備えたことを特徴とする請求項1乃至10のいずれか1項に記載の半導体装置。 - 素子領域に形成された素子がMOSFETであり、
ドリフト層の表層部に形成された複数の第2導電型のウェル領域と、
前記ウェル領域の表層の一部の形成された第1導電型のソース領域と、
前記ウェル領域の上部にゲート絶縁膜を間に介して形成されたゲート電極と、
前記ソース領域および前記ウェル領域と接続されたソース電極と、
半導体基板の第2の主面に接して形成されたオーミック電極と、
最も外側に位置する前記ウェル領域とつながった不純物領域と、
リセス構造の上部に形成された絶縁膜と
を備えたことを特徴とする請求項1乃至10のいずれか1項に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013508733A JP5583846B2 (ja) | 2011-04-05 | 2012-03-12 | 半導体装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011083725 | 2011-04-05 | ||
JP2011083725 | 2011-04-05 | ||
JP2013508733A JP5583846B2 (ja) | 2011-04-05 | 2012-03-12 | 半導体装置 |
PCT/JP2012/001677 WO2012137412A1 (ja) | 2011-04-05 | 2012-03-12 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2012137412A1 JPWO2012137412A1 (ja) | 2014-07-28 |
JP5583846B2 true JP5583846B2 (ja) | 2014-09-03 |
Family
ID=46968828
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013508733A Active JP5583846B2 (ja) | 2011-04-05 | 2012-03-12 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9153443B2 (ja) |
JP (1) | JP5583846B2 (ja) |
CN (1) | CN103460386B (ja) |
DE (1) | DE112012001587B4 (ja) |
WO (1) | WO2012137412A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140086688A (ko) * | 2012-12-28 | 2014-07-08 | 현대자동차주식회사 | 쇼트키 배리어 다이오드 및 그 제조 방법 |
JP2014138048A (ja) * | 2013-01-16 | 2014-07-28 | Sumitomo Electric Ind Ltd | 炭化珪素半導体装置 |
US9515136B2 (en) | 2014-06-18 | 2016-12-06 | Stmicroelectronics S.R.L. | Edge termination structure for a power integrated device and corresponding manufacturing process |
CN106783957A (zh) * | 2016-12-27 | 2017-05-31 | 西安电子科技大学 | 碳化硅多台阶沟槽结终端扩展终端结构及其制备方法 |
KR101943926B1 (ko) * | 2018-04-19 | 2019-01-31 | 주식회사 예스파워테크닉스 | SiC를 이용한 반도체에서의 마스크 정렬 방법 |
CN113314417B (zh) * | 2020-02-26 | 2023-05-05 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
JP6861914B1 (ja) * | 2020-07-08 | 2021-04-21 | 三菱電機株式会社 | 半導体装置及び半導体装置の製造方法 |
CN113053999B (zh) * | 2021-03-12 | 2023-02-21 | 深圳方正微电子有限公司 | 金属氧化物半导体晶体管及其制备方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002164541A (ja) * | 2000-11-29 | 2002-06-07 | Denso Corp | 半導体装置およびその製造方法 |
JP2005057142A (ja) * | 2003-08-06 | 2005-03-03 | Fuji Electric Holdings Co Ltd | 半導体基板の製造方法 |
JP2008124362A (ja) * | 2006-11-15 | 2008-05-29 | Mitsubishi Electric Corp | 半導体装置とその製造方法 |
JP2009094392A (ja) * | 2007-10-11 | 2009-04-30 | Mitsubishi Electric Corp | 炭化珪素半導体装置の製造方法 |
JP2010034381A (ja) * | 2008-07-30 | 2010-02-12 | Denso Corp | ワイドバンドギャップ半導体装置 |
JP2011204935A (ja) * | 2010-03-26 | 2011-10-13 | Mitsubishi Electric Corp | 半導体装置とその製造方法 |
JP2011238824A (ja) * | 2010-05-12 | 2011-11-24 | Renesas Electronics Corp | パワー系半導体装置 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1214805B (it) | 1984-08-21 | 1990-01-18 | Ates Componenti Elettron | Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown |
JPH07302896A (ja) * | 1994-04-28 | 1995-11-14 | Ngk Insulators Ltd | 半導体装置およびその製造方法 |
JP3432043B2 (ja) | 1995-05-26 | 2003-07-28 | 日本無線株式会社 | 半導体装置の製造方法 |
KR0154702B1 (ko) | 1995-06-09 | 1998-10-15 | 김광호 | 항복전압을 향상시킨 다이오드 제조 방법 |
US6573534B1 (en) * | 1995-09-06 | 2003-06-03 | Denso Corporation | Silicon carbide semiconductor device |
JP4075150B2 (ja) | 1998-03-20 | 2008-04-16 | 株式会社デンソー | 炭化珪素半導体装置及びその製造方法 |
SE9700156D0 (sv) * | 1997-01-21 | 1997-01-21 | Abb Research Ltd | Junction termination for Si C Schottky diode |
JP4077170B2 (ja) * | 2000-09-21 | 2008-04-16 | シャープ株式会社 | 半導体発光装置 |
DE10047152B4 (de) * | 2000-09-22 | 2006-07-06 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | Hochvolt-Diode und Verfahren zu deren Herstellung |
JP3873798B2 (ja) | 2002-04-11 | 2007-01-24 | 富士電機デバイステクノロジー株式会社 | 炭化けい素半導体素子およびその製造方法 |
DE102004040523B4 (de) * | 2004-08-20 | 2008-10-02 | Infineon Technologies Ag | Verfahren zur Herstellung von Feldringen |
JP4531713B2 (ja) | 2006-03-31 | 2010-08-25 | 三菱電機株式会社 | アライメントマーク及びその形成方法、半導体装置及びその製造方法 |
JP4924440B2 (ja) * | 2008-01-14 | 2012-04-25 | 株式会社デンソー | 炭化珪素半導体装置の製造方法 |
JP4743447B2 (ja) * | 2008-05-23 | 2011-08-10 | 三菱電機株式会社 | 半導体装置 |
JP5396953B2 (ja) | 2009-03-19 | 2014-01-22 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
JP5600411B2 (ja) | 2009-10-28 | 2014-10-01 | 三菱電機株式会社 | 炭化珪素半導体装置 |
-
2012
- 2012-03-12 US US14/009,685 patent/US9153443B2/en active Active
- 2012-03-12 DE DE112012001587.8T patent/DE112012001587B4/de active Active
- 2012-03-12 WO PCT/JP2012/001677 patent/WO2012137412A1/ja active Application Filing
- 2012-03-12 CN CN201280014798.4A patent/CN103460386B/zh active Active
- 2012-03-12 JP JP2013508733A patent/JP5583846B2/ja active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002164541A (ja) * | 2000-11-29 | 2002-06-07 | Denso Corp | 半導体装置およびその製造方法 |
JP2005057142A (ja) * | 2003-08-06 | 2005-03-03 | Fuji Electric Holdings Co Ltd | 半導体基板の製造方法 |
JP2008124362A (ja) * | 2006-11-15 | 2008-05-29 | Mitsubishi Electric Corp | 半導体装置とその製造方法 |
JP2009094392A (ja) * | 2007-10-11 | 2009-04-30 | Mitsubishi Electric Corp | 炭化珪素半導体装置の製造方法 |
JP2010034381A (ja) * | 2008-07-30 | 2010-02-12 | Denso Corp | ワイドバンドギャップ半導体装置 |
JP2011204935A (ja) * | 2010-03-26 | 2011-10-13 | Mitsubishi Electric Corp | 半導体装置とその製造方法 |
JP2011238824A (ja) * | 2010-05-12 | 2011-11-24 | Renesas Electronics Corp | パワー系半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US9153443B2 (en) | 2015-10-06 |
JPWO2012137412A1 (ja) | 2014-07-28 |
CN103460386B (zh) | 2016-06-22 |
CN103460386A (zh) | 2013-12-18 |
DE112012001587T5 (de) | 2014-02-13 |
DE112012001587B4 (de) | 2017-04-06 |
US20140021490A1 (en) | 2014-01-23 |
WO2012137412A1 (ja) | 2012-10-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5583846B2 (ja) | 半導体装置 | |
US6770539B2 (en) | Vertical type MOSFET and manufacturing method thereof | |
US8754422B2 (en) | Semiconductor device and process for production thereof | |
US8399921B2 (en) | Metal oxide semiconductor (MOS) structure and manufacturing method thereof | |
JP5298565B2 (ja) | 半導体装置およびその製造方法 | |
JP5102411B2 (ja) | 半導体装置およびその製造方法 | |
JP6485382B2 (ja) | 化合物半導体装置の製造方法および化合物半導体装置 | |
US9099321B2 (en) | Method for fabricating power semiconductor device | |
JP2015159271A (ja) | 半導体装置の製造方法 | |
JP2014135494A (ja) | 二重並列チャネル構造を持つ半導体素子及びその半導体素子の製造方法 | |
JP2016092257A (ja) | 炭化珪素半導体装置およびその製造方法 | |
KR101339265B1 (ko) | 반도체 소자의 제조 방법 | |
TWI633674B (zh) | 半導體裝置以及半導體裝置的製造方法 | |
CN106571394B (zh) | 功率器件及其制造方法 | |
JP2019003967A (ja) | 半導体装置および半導体装置の製造方法 | |
WO2017145548A1 (ja) | 化合物半導体装置およびその製造方法 | |
TW201320306A (zh) | 用於溝槽式裝置的整合式閘極佈設區及場植入部終止技術 | |
JP5558243B2 (ja) | 半導体装置 | |
US8492221B2 (en) | Method for fabricating power semiconductor device with super junction structure | |
KR102100863B1 (ko) | SiC MOSFET 전력 반도체 소자 | |
JP2008282859A (ja) | 半導体装置 | |
US10727105B2 (en) | Semiconductor device and manufacturing method therefor | |
KR102062050B1 (ko) | 결합된 게이트 트렌치 및 컨택 에칭 프로세스 및 그와 관련된 구조체 | |
JP2020035912A (ja) | 半導体装置 | |
US8968017B2 (en) | Semiconductor device and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140617 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140716 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5583846 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |