TW201419532A - 具有低米勒電容之金氧半場效電晶體元件及其製作方法 - Google Patents

具有低米勒電容之金氧半場效電晶體元件及其製作方法 Download PDF

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TW201419532A
TW201419532A TW101141608A TW101141608A TW201419532A TW 201419532 A TW201419532 A TW 201419532A TW 101141608 A TW101141608 A TW 101141608A TW 101141608 A TW101141608 A TW 101141608A TW 201419532 A TW201419532 A TW 201419532A
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gate trench
gate
semiconductor device
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layer
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Yung-Fa Lin
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Anpec Electronics Corp
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Priority to TW101141608A priority Critical patent/TW201419532A/zh
Priority to CN201210526150.7A priority patent/CN103811548A/zh
Priority to US13/719,190 priority patent/US20140124852A1/en
Priority to US14/051,451 priority patent/US20140124853A1/en
Publication of TW201419532A publication Critical patent/TW201419532A/zh

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Abstract

一種功率半導體元件，包含有一半導體基底，具有第一導電型；一磊晶層，位於該半導體基底上，且具有該第一導電型；一離子井，具有第二導電型，位於該磊晶層中，其中該離子井具有一接面深度；一閘極溝槽，位於該離子井中，且該閘極溝槽的深度小於該接面深度；一凹陷溝槽，位於該閘極溝槽的底部；一閘極氧化層，位於該閘極溝槽表面，並填滿該凹陷溝槽，如此構成一尖端凸出結構；一閘極，位於該閘極溝槽內；以及一汲極延伸區，具有該第一導電型，介於該閘極溝槽與該磊晶層之間，緊鄰該尖端凸出結構。

Description

具有低米勒電容之金氧半場效電晶體元件及其製作方法
本發明係有關於半導體元件技術領域，特別是有關於一種具有低米勒電容之金氧半場效電晶體(MOSFET)元件及其製作方法。
在傳統功率電晶體中，平面型功率元件(DMOS)因來自於通道區域(channel region)、聚集層(accumulation layer)以及接面場效電晶體(JFET)的貢獻，而使得導通電阻(on-resistance)上升。
為了降低上述區域之電阻，溝渠型功率元件(UMOS)於是被提出來，更因為UMOS結構不存在之JFET區域，因此可以縮小UMOS元件尺寸(cell size)以提高通道密度(channel density)，可以進一步降低導通電阻，但另一方面，UMOS元件也因其結構的關係導致閘汲間電容(米勒電容)上升而使得開關速度變慢。
因此，本發明之目的，即在提供一種功率半導體元件及其製作方法，以降低米勒電容。
根據本發明之較佳實施例，本發明提供一種功率半導體元件，包含有一半導體基底，具有第一導電型；一磊晶層，位於該半導體基底上，且具有該第一導電型；一離子井，具有第二導電型，位於該磊晶層中，其中該離子井具有一接面深度；一閘極溝槽，位於該離 子井中，且該閘極溝槽的深度小於該接面深度；一凹陷溝槽，位於該閘極溝槽的底部；一閘極氧化層，位於該閘極溝槽表面，並填滿該凹陷溝槽，如此構成一尖端凸出結構；一閘極，位於該閘極溝槽內；以及一汲極延伸區，具有該第一導電型，介於該閘極溝槽與該磊晶層之間，緊鄰該尖端凸出結構。
根據本發明之較佳實施例，本發明提供一種功率半導體元件，包含有一半導體基底，具有第一導電型；一磊晶層，位於該半導體基底上；一離子井，具有第二導電型，位於該磊晶層中，其中該離子井具有一接面深度；一閘極溝槽，位於該離子井中；一閘極氧化層，位於該閘極溝槽表面；一閘極，位於該閘極溝槽內；以及一尖端延伸摻雜區，具有該第一導電型，介於該閘極溝槽與該磊晶層之間。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
請參閱第1圖至第8圖，其為依據本發明一實施例所繪示的電晶體元件之製造方法示意圖。首先，如第1圖所示，提供一半導體基底10，例如N型重摻雜矽基底，可作為電晶體元件的汲極(drain)。接著，利用一磊晶製程於半導體基底10上形成一磊晶層11，例如N型磊晶矽層。於磊晶層11表面形成一墊氧化層12a之後，接著，進行一離子佈植製程，於磊晶層11中形成一離子井210，例如P型井，其中離子井210的接面深度為d1。
如第2圖所示，接著於磊晶層11上沈積一硬遮罩層12b，例如氮化矽層，然後，利用微影、蝕刻等製程，於硬遮罩層12b中形成開口112。接著利用乾蝕刻製程，經由硬遮罩層12b中的開口112，蝕刻離子井210至一預定深度d2，如此形成閘極溝槽122，其中閘極溝槽122的預定深度d2須小於離子井210的接面深度d1。
如第3圖所示，接下來氧化閘極溝槽122的側壁，形成犧牲氧化層14。在另一實施例中，犧牲氧化層14亦可以是由沈積及蝕刻形成的間隙壁代替。犧牲氧化層14的厚度不足以填滿閘極溝槽122，而留下一縫隙122a。接著，進行一尖端離子佈植製程，經由縫隙122a將N型摻質植入閘極溝槽122正下方的離子井210中，形成一尖端延伸摻雜區15。根據另一實施例，如第9圖所示，亦可以在形成犧牲氧化層14之後，進行一蝕刻製程，將犧牲氧化層14蝕刻成間隙壁14a，然後才進行上述的尖端離子佈植製程。
如第4圖所示，接著進行另一乾蝕刻製程，利用犧牲氧化層14作為蝕刻遮罩，繼續經由縫隙122a蝕刻離子井210約略至離子井210的接面深度為d1，顯露出部分的磊晶層11，如此在閘極溝槽122下方形成一凹陷溝槽123，將尖端延伸摻雜區15切開成左、右兩部分，作為汲極延伸區15a及15b。凹陷溝槽123的開口寬度大小，可以藉由犧牲氧化層14的厚度來控制。
如第5圖所示，接著去除墊氧化層12a、硬遮罩層12b以及犧牲氧化層14，顯露出離子井210表面及閘極溝槽122表面。然後進行一熱氧化製程，形成閘極氧化層18，使得凹陷溝槽123最後被閘極氧化層18填滿，而在閘極溝槽122正下方形成尖端凸出結構18a。 繼之，進行一化學氣相沈積(CVD)製程，沈積一多晶矽層，使多晶矽層填滿閘極溝槽122，再回蝕刻多晶矽層，如此於閘極溝槽122形成閘極20a。
如第6圖所示，接著利用微影製程，形成一圖案化光阻層(圖未示)，定義出源極區域，再以離子佈植製程將摻質，例如N型摻質，植入上述源極區域，於離子井210構成源極摻雜區22。之後，再將光阻層去除，並以施以熱驅入製程，活化這些被植入的摻質。
最後，如第7-8圖所示，進行接觸洞及金屬化製程，包括形成層間介電層30，於層間介電層30中形成接觸洞230，於接觸洞230底部以離子佈植製程形成接觸摻雜區250，沈積阻障層32及金屬層34，並使金屬層34填滿接觸洞230，構成接觸件34a。
請參閱第10圖至第15圖，其為依據本發明另一實施例所繪示的電晶體元件之製造方法示意圖。首先，如第10圖所示，提供一半導體基底10，例如N型重摻雜之矽基底，可作為電晶體元件的汲極。接著，利用一磊晶製程於半導體基底10上形成一磊晶層11，例如N型磊晶矽層。於磊晶層11表面形成一墊氧化層12a之後，接著，進行一離子佈植製程，於磊晶層11中形成一離子井210，例如P型井，其中離子井210的接面深度為d1。
如第11圖所示，接著於磊晶層11上沈積一硬遮罩層12b，例如氮化矽層，然後，利用微影、蝕刻等製程，於硬遮罩層12b中形成開口112。接著利用乾蝕刻製程，經由硬遮罩層12b中的開口112，蝕刻離子井210至一預定深度d2，如此形成閘極溝槽122，其中閘極溝槽122的預定深度d2須小於離子井210的接面深度d1。
如第12圖所示，接下來於閘極溝槽122的側壁及硬遮罩層12b表面，順應的沈積氧化層140。同樣的，氧化層14的厚度不足以填滿閘極溝槽122，而留下一縫隙122a。
接著，如第13圖所示，進行一蝕刻製程，將氧化層140蝕刻成間隙壁140a，並顯露出部分的閘極溝槽122底部。
繼之，如第14圖所示，進行一尖端離子佈植製程，經由縫隙122a將N型摻質植入閘極溝槽122正下方的離子井210中，形成一尖端延伸摻雜區15。此實施例中並不進行切開尖端延伸摻雜區15的蝕刻製程。
如第15圖所示，接著去除墊氧化層12a、硬遮罩層12b以及間隙壁140a，顯露出離子井210表面及閘極溝槽122表面。然後進行一熱氧化製程，形成閘極氧化層18，繼之，進行一化學氣相沈積製程，沈積一多晶矽層20，使多晶矽層20填滿閘極溝槽122。
後續步驟則同第6圖至第8圖，包括回蝕刻多晶矽層20，如此於閘極溝槽122形成閘極20a，接著利用微影製程，形成一圖案化光阻層，定義出源極區域，再以離子佈植製程將摻質，例如N型摻質，植入上述源極區域，於離子井210構成源極摻雜區22。進行接觸洞及金屬化製程，包括形成層間介電層30，於層間介電層30中形成接觸洞230，於接觸洞230底部以離子佈植製程形成接觸摻雜區250，沈積阻障層32及金屬層34，並使金屬層34填滿接觸洞230，構成接觸件34a。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧半導體基底
11‧‧‧磊晶層
12a‧‧‧墊氧化層
12b‧‧‧硬遮罩層
14‧‧‧犧牲氧化層
14a‧‧‧間隙壁
15‧‧‧尖端延伸摻雜區
15a‧‧‧汲極延伸區
15b‧‧‧汲極延伸區
18‧‧‧閘極氧化層
18a‧‧‧尖端凸出結構
20‧‧‧多晶矽層
20a‧‧‧閘極
22‧‧‧源極摻雜區
30‧‧‧層間介電層
32‧‧‧阻障層
34‧‧‧金屬層
34a‧‧‧接觸件
112‧‧‧開口
122‧‧‧閘極溝槽
123‧‧‧凹陷溝槽
140‧‧‧氧化層
140a‧‧‧間隙壁
210‧‧‧離子井
230‧‧‧接觸洞
250‧‧‧接觸摻雜區
第1圖至第8圖為依據本發明一實施例所繪示的電晶體元件之製造方法示意圖。
第9圖例示將犧牲氧化層蝕刻成間隙壁，再進行尖端離子佈植製程之作法。
第10圖至第15圖為依據本發明另一實施例所繪示的電晶體元件之製造方法示意圖。
10‧‧‧半導體基底
11‧‧‧磊晶層
15a‧‧‧汲極延伸區
15b‧‧‧汲極延伸區
18‧‧‧閘極氧化層
18a‧‧‧尖端凸出結構
20a‧‧‧閘極
22‧‧‧源極摻雜區
30‧‧‧層間介電層
32‧‧‧阻障層
34‧‧‧金屬層
34a‧‧‧接觸件
210‧‧‧離子井
250‧‧‧接觸摻雜區

Claims (12)

  1. 一種功率半導體元件，包含有：一半導體基底，具有第一導電型；一磊晶層，位於該半導體基底上；一離子井，具有第二導電型，位於該磊晶層中，其中該離子井具有一接面深度；一閘極溝槽，位於該離子井中；一凹陷溝槽，位於該閘極溝槽的底部；一閘極氧化層，位於該閘極溝槽表面，並填滿該凹陷溝槽，如此構成一尖端凸出結構；一閘極，位於該閘極溝槽內；以及一汲極延伸區，具有該第一導電型，介於該閘極溝槽與該磊晶層之間，緊鄰該尖端凸出結構。
  2. 如申請專利範圍第1項所述之功率半導體元件，其中另包含有一源極摻雜區，位於該離子井表面並緊鄰該閘極溝槽。
  3. 如申請專利範圍第2項所述之功率半導體元件，其中該源極摻雜區具有該第一導電型。
  4. 如申請專利範圍第1項所述之功率半導體元件，其中該第一導電型為N型，該第二導電型為P型。
  5. 如申請專利範圍第1項所述之功率半導體元件，其中該磊晶層具有該第一導電型。
  6. 如申請專利範圍第1項所述之功率半導體元件，其中該閘極溝槽的深度小於該接面深度。
  7. 一種功率半導體元件，包含有：一半導體基底，具有第一導電型；一磊晶層，位於該半導體基底上；一離子井，具有第二導電型，位於該磊晶層中，其中該離子井具有一接面深度；一閘極溝槽，位於該離子井中；一閘極氧化層，位於該閘極溝槽表面；一閘極，位於該閘極溝槽內；以及一尖端延伸摻雜區，具有該第一導電型，介於該閘極溝槽與該磊晶層之間。
  8. 如申請專利範圍第7項所述之功率半導體元件，其中另包含有一源極摻雜區，位於該離子井表面並緊鄰該閘極溝槽。
  9. 如申請專利範圍第8項所述之功率半導體元件，其中該源極摻雜區具有該第一導電型。
  10. 如申請專利範圍第7項所述之功率半導體元件，其中該第一導電型為N型，該第二導電型為P型。
  11. 如申請專利範圍第7項所述之功率半導體元件，其中該磊晶層具有該第一導電型。
  12. 如申請專利範圍第7項所述之功率半導體元件，其中該閘極溝槽的深度小於該接面深度。
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