CN103811548A - 具有低密勒电容的金氧半场效应晶体管器件及其制作方法 - Google Patents

具有低密勒电容的金氧半场效应晶体管器件及其制作方法 Download PDF

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CN103811548A
CN103811548A CN201210526150.7A CN201210526150A CN103811548A CN 103811548 A CN103811548 A CN 103811548A CN 201210526150 A CN201210526150 A CN 201210526150A CN 103811548 A CN103811548 A CN 103811548A
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gate trench
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林永发
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Anpec Electronics Corp
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Abstract

本发明公开了一种功率半导体器件，包含有一半导体基底，具有第一导电型；一外延层，位于所述半导体基底上且具有所述第一导电型；一离子阱，具有第二导电型且位于所述外延层中，其中所述离子阱具有一接面深度；一栅极沟槽，位于所述离子阱中且所述栅极沟槽的深度小于所述接面深度；一凹陷沟槽，位于所述栅极沟槽的底部；一栅极氧化层，位于所述栅极沟槽表面并填满所述凹陷沟槽，如此构成一尖端凸出结构；一栅极，位于所述栅极沟槽内；以及一漏极延伸区，具有所述第一导电型，介于所述栅极沟槽与所述外延层之间并紧邻所述尖端凸出结构。

Description

具有低密勒电容的金氧半场效应晶体管器件及其制作方法
技术领域
本发明大体上关于半导体器件技术领域，特别是关于一种具有低密勒电容的金氧半场效应晶体管(MOSFET)器件及其制作方法。
背景技术
在传统的功率晶体管中，平面型功率器件(DMOS)因来自于沟道区域(channel region)、积累层(accumulation layer)以及接面场效应晶体管(JFET)的贡献，而使得导通电阻(on-resistance)上升。
为了降低上述区域的电阻，沟渠型功率器件(UMOS)于是被提出来，更因为UMOS结构不存在的JFET区域，因此可以缩小UMOS器件的单元尺寸以提高沟道密度(channel density)，可以进一步降低导通电阻，但另一方面，UMOS器件也因其结构的关系导致栅极漏极间电容(密勒电容)上升而使得开关速度变慢。
发明内容
因此，本发明的目的，即在提供一种功率半导体器件及其制作方法，以降低密勒电容。
根据本发明的优选实施例，本发明提供一种功率半导体器件，包含有一半导体基底，具有第一导电型；一外延层，位于所述半导体基底上且具有第一导电型；一离子阱，具有第二导电型且位于所述外延层中，其中所述离子阱具有一接面深度；一栅极沟槽，位于所述离子阱中，且所述栅极沟槽的深度小于所述接面深度；一凹陷沟槽，位于所述栅极沟槽的底部；一栅极氧化层，位于所述栅极沟槽表面并填满所述凹陷沟槽，如此构成一尖端凸出结构；一栅极，位于所述栅极沟槽内；以及一漏极延伸区，具有第一导电型，介于所述栅极沟槽与所述外延层之间并紧邻所述尖端凸出结构。
根据本发明的优选实施例，本发明提供一种功率半导体器件，包含有一半导体基底，具有第一导电型；一外延层，位于所述半导体基底上；一离子阱，具有第二导电型且位于所述外延层中，其中所述离子阱具有一接面深度；一栅极沟槽，位于所述离子井中；一栅极氧化层，位于所述栅极沟槽表面；一栅极，位于所述栅极沟槽内；以及一尖端延伸掺杂区，具有第一导电型且介于所述栅极沟槽与所述外延层之间。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式并配合所附图式作详细说明如下。然而如下的优选实施方式与图式仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1至图8为依据本发明一实施例所绘示的晶体管器件的制造方法示意图。
图9例示出将牺牲氧化层刻蚀成间隙壁，再进行尖端离子注入工艺的作法。
图10至图15为依据本发明另一实施例所绘示的晶体管器件的制造方法示意图。
其中，附图标记说明如下：
10   半导体基底      22   源极掺杂区
11   外延层          30   层间介电层
12a  垫氧化层        32   阻障层
12b  硬掩膜层        34   金属层
14   牺牲氧化层      34a  接触件
14a  间隙壁          112  开口
15   尖端延伸掺杂区  122  栅极沟槽
15a  漏极延伸区      123  凹陷沟槽
15b  漏极延伸区      140  氧化层
18   栅极氧化层      140a 间隙壁
18a  尖端凸出结构    210  离子阱
20   多晶硅层        230  接触洞
20a  栅极            250  接触掺杂区
具体实施方式
请参阅图1至图8，其为依据本发明一实施例所绘示的晶体管器件的制造方法示意图。首先，如图1所示，提供一半导体基底10，例如N型重掺杂硅基底，可作为晶体管器件的漏极(drain)。接着，利用一外延工艺于半导体基底10上形成一外延层11，例如N型外延硅层。于外延层11表面形成一垫氧化层12a之后，接着，进行一离子注入工艺，于外延层11中形成一离子阱210，例如P型阱，其中离子阱210的接面深度为d1。
如图2所示，接着于外延层11上沉积一硬掩膜层12b，例如氮化硅层，然后，利用光刻、刻蚀等工艺于硬掩膜层12b中形成开112。接着利用干刻蚀工艺，经由硬掩膜层12b中的开112刻蚀离子阱210至一预定深度d2，如此形成栅极沟槽122，其中栅极沟槽122的预定深度d2须小于离子阱210的接面深度d1。
如图3所示，接下来氧化栅极沟槽122的侧壁形成牺牲氧化层14。在另一实施例中，牺牲氧化层14也可以是由沉积及刻蚀形成的间隙壁代替。牺牲氧化层14的厚度不足以填满栅极沟槽122，而留下一缝隙122a。接着，进行一尖端离子注入工艺，经由缝隙122a将N型掺质植入栅极沟槽122正下方的离子阱210中，形成一尖端延伸掺杂区15。根据另一实施例，如图9所示，也可以在形成牺牲氧化层14之后，进行一刻蚀工艺，将牺牲氧化层14刻蚀成间隙壁14a，然后才进行上述的尖端离子注入工艺。
如图4所示，接着进行另一干刻蚀工艺，利用牺牲氧化层14作为刻蚀掩膜，继续经由缝隙122a刻蚀离子阱210约略至离子阱210的接面深度为d1，显露出部分的外延层11，如此在栅极沟槽122下方形成一凹陷沟槽123，其将尖端延伸掺杂区15切开成左、右两部分作为漏极延伸区15a及15b。凹陷沟槽123的开口宽度大小可以藉由牺牲氧化层14的厚度来控制。
如图5所示，接着去除垫氧化层12a、硬掩膜层12b以及牺牲氧化层14，显露出离子阱210表面与栅极沟槽122表面。然后进行一热氧化工艺形成栅极氧化层18，使得凹陷沟槽123最后被栅极氧化层18填满，而在栅极沟槽122正下方形成尖端凸出结构18a。接着，进行一化学气相沉积(CVD)工艺沉积一多晶硅层，使多晶硅层填满栅极沟槽122，再回刻蚀多晶硅层，如此于栅极沟槽122形成栅极20a。
如图6所示，接着利用光刻工艺形成一图案化光刻胶层(未示于图中)界定出源极区域，再以离子注入工艺将掺质，例如N型掺质，注入上述源极区域，以于离子阱210中构成源极掺杂区22。之后，再将光刻胶层去除并施以热驱入工艺活化这些被注入的掺质。
最后，如图7-8所示，进行接触洞及金属化工艺，包括形成层间介电层30，于层间介电层30中形成接触洞230，于接触洞230底部以离子注入工艺形成接触掺杂区250，沉积阻障层32及金属层34，并使金属层34填满接触洞230构成接触件34a。
请参阅图10至图15，其为依据本发明另一实施例所绘示的晶体管器件的制造方法示意图。首先，如图10所示，提供一半导体基底10，例如N型重掺杂的硅基底，可作为晶体管器件的漏极。接着，利用一外延工艺于半导体基底10上形成一外延层11，例如N型外延硅层。于外延层11表面形成一垫氧化层12a之后，接着，进行一离子注入工艺，于外延层11中形成一离子阱210，例如P型阱，其中离子阱210的接面深度为d1。
如图11所示，接着于外延层11上沉积一硬掩膜层12b，例如氮化硅层，然后，利用光刻、刻蚀等工艺于硬掩膜层12b中形成开口112。接着利用干刻蚀工艺经由硬掩膜层12b中的开口112刻蚀离子阱210至一预定深度d2，如此形成栅极沟槽122，其中栅极沟槽122的预定深度d2须小于离子井210的接面深度d1。
如图12所示，接下来于栅极沟槽122的侧壁及硬掩膜层12b表面顺应地沉积氧化层140。同样的，氧化层14的厚度不足以填满栅极沟槽122而留下一缝隙122a。
接着，如图13所示，进行一刻蚀工艺将氧化层140刻蚀成间隙壁140a并显露出部分的栅极沟槽122底部。
接着，如图14所示，进行一尖端离子注入工艺经由缝隙122a将N型掺质注入栅极沟槽122正下方的离子阱210中，形成一尖端延伸掺杂区15。此实施例中并不进行切开尖端延伸掺杂区15的刻蚀工艺。
如图15所示，接着去除垫氧化层12a、硬掩膜层12b以及间隙壁140a，以显露出离子阱210表面与栅极沟槽122表面。然后进行一热氧化工艺形成栅极氧化层18，接着，进行一化学气相沉积工艺沉积一多晶硅层20，使多晶硅层20填满栅极沟槽122。
后续步骤则同图6至图8，包括回刻蚀多晶硅层20，如此于栅极沟槽122形成栅极20a，接着利用光刻工艺形成一图案化光刻胶层，以界定出源极区域，再以离子注入工艺将掺质，例如N型掺质，注入上述源极区域，以于离子阱210构成源极掺杂区22。进行接触洞及金属化工艺，包括形成层间介电层30，于层间介电层30中形成接触洞230，于接触洞230底部以离子注入工艺形成接触掺杂区250，沉积阻障层32及金属层34，并使金属层34填满接触洞230，构成接触件34a。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

1.一种功率半导体器件，其特征在于，包含：
一半导体基底，具有第一导电型；
一外延层，位于所述半导体基底上；
一离子阱，具有第二导电型且位于所述外延层中，其中所述离子阱具有一接面深度；
一栅极沟槽，位于所述离子阱中；
一凹陷沟槽，位于所述栅极沟槽的底部；
一栅极氧化层，位于所述栅极沟槽表面并填满所述凹陷沟槽，如此构成一尖端凸出结构；
一栅极，位于所述栅极沟槽内；以及
一漏极延伸区，具有所述第一导电型，介于所述栅极沟槽与所述外延层之间且紧邻所述尖端凸出结构。
2.根据权利要求1所述的功率半导体器件，其特征在于，另包含有一源极掺杂区位于所述离子阱表面并紧邻所述栅极沟槽。
3.根据权利要求2所述的功率半导体器件，其特征在于，所述源极掺杂区具有所述第一导电型。
4.根据权利要求1所述的功率半导体器件，其特征在于，所述第一导电型为N型，所述第二导电型为P型。
5.根据权利要求1所述的功率半导体器件，其特征在于，所述外延层具有所述第一导电型。
6.根据权利要求1所述的功率半导体器件，其特征在于，所述栅极沟槽的深度小于所述接面深度。
7.一种功率半导体器件，其特征在于，包含：
一半导体基底，具有第一导电型；
一外延层，位于所述半导体基底上；
一离子阱，具有第二导电型，位于所述外延层中，其中所述离子阱具有一接面深度；
一栅极沟槽，位于所述离子阱中；
一栅极氧化层，位于所述栅极沟槽表面；
一栅极，位于所述栅极沟槽内；以及
一尖端延伸掺杂区，具有所述第一导电型，介于所述栅极沟槽与所述外延层之间。
8.根据权利要求7所述的功率半导体器件，其特征在于，另包含有一源极掺杂区，位于所述离子阱表面并紧邻所述栅极沟槽。
9.根据权利要求8所述的功率半导体器件，其特征在于，所述源极掺杂区具有所述第一导电型。
10.根据权利要求7所述的功率半导体器件，其特征在于，所述第一导电型为N型，所述第二导电型为P型。
11.根据权利要求7所述的功率半导体器件，其特征在于，所述外延层具有所述第一导电型。
12.根据权利要求7所述的功率半导体器件，其特征在于，所述栅极沟槽的深度小于所述接面深度。
CN201210526150.7A 2012-11-08 2012-12-07 具有低密勒电容的金氧半场效应晶体管器件及其制作方法 Pending CN103811548A (zh)

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