CN105702732A - 带有保护屏蔽氧化物的分裂栅沟槽功率mosfet - Google Patents

带有保护屏蔽氧化物的分裂栅沟槽功率mosfet Download PDF

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CN105702732A
CN105702732A CN201510821015.9A CN201510821015A CN105702732A CN 105702732 A CN105702732 A CN 105702732A CN 201510821015 A CN201510821015 A CN 201510821015A CN 105702732 A CN105702732 A CN 105702732A
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conductive material
insulating barrier
grooves
gate trench
groove
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CN105702732B (zh
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李亦衡
管灵鹏
薛宏勇
顾鸣
顾一鸣
向泱
黄士彰
谢卡尔·拉玛莫西
李文军
常虹
马督儿·博德
保罗·托鲁普
哈姆扎·依玛兹
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

多个栅极沟槽形成在有源晶胞区中的半导体衬底中。一个或多个其他沟槽形成在不同区域。每个栅极沟槽都具有在底部的第一导电材料，以及在顶部的第二导电材料。在栅极沟槽中，第一绝缘层将第一导电材料与衬底隔开，第二绝缘层将第二导电材料与衬底隔开，第三绝缘层将第一导电材料和第二导电材料隔开。一个或多个其他沟槽都含有一部分第一导电材料，呈半U型，在其他沟槽底部，以及第二导电材料在其他沟槽顶部。在其他沟槽中，第三绝缘层将第一导电材料和第二导电材料隔开。第一绝缘层的厚度大于第三绝缘层的厚度，第三绝缘层的厚度大于第二绝缘层的厚度。

Description

带有保护屏蔽氧化物的分裂栅沟槽功率MOSFET
技术领域
本发明的各个方面主要是关于半导体功率器件，更确切地说，是关于分裂栅晶体管器件及其制备方法。
背景技术
功率金属氧化物半导体场效应晶体管（MOSFET）因其低栅极驱动功率、快速切换速度以及出色的并联性能等特性，常被用于功率器件。大多数的功率MOSFET都具有垂直结构的特点，源极和漏极区在栅极沟槽的对边上，栅极沟槽用多晶硅填充，作为栅极电极。在这种结构中，MOS通道沿沟槽的垂直侧壁形成。
分裂栅沟槽结构因其良好的高频性能和低导通状态电阻，近年来已超越传统的沟槽MOSFET，在特定应用中受到普遍欢迎。分裂栅沟槽功率MOSFET包括在栅极沟槽中的两个电极。第一电极作为栅极电极，控制MOSFET的通道形成，第二电极作为屏蔽电极，降低漏极电极和栅极电极之间的电容Cgd。分裂栅沟槽MOSFET现有的制备技术通常复杂且昂贵，处理时通常需要8个或8个以上的掩膜。
正是在这样的背景下，提出了本发明的实施例。
发明内容
因此，本发明的一个方面在于提出一种新型改良的带有多晶硅保护的屏蔽氧化物的功率MOSFET。
简单地说，本发明的各个方面包括具有多个栅极沟槽的半导体器件，形成在有源晶胞区中的半导体衬底中，以及一个或多个沟槽，形成在有源晶胞区之外的区域中的半导体衬底中。每个栅极沟槽都有一个在栅极沟槽底部的第一导电材料，以及一个在栅极沟槽顶部的第二导电材料。栅极沟槽中第一导电材料与半导体衬底被第一绝缘层隔开。栅极沟槽中第二导电材料与半导体衬底被第二绝缘层隔开，与栅极沟槽中第一导电材料被第三绝缘层隔开。一个或多个其他沟槽都含有一部分第一导电材料，呈半U型，在其他沟槽底部，以及第二导电材料在其他沟槽顶部。一个或多个其他沟槽中的第一导电材料和第二导电材料，被第三绝缘层隔开。第一绝缘层比第三绝缘层更厚，第三绝缘层比第二绝缘层更厚。
在一些实施例中，半导体器件包括一个或多个拾起沟槽，形成在拾起区中的半导体衬底中。拾起沟槽包括至少一部分第一导电材料，第一绝缘层将一个或多个拾起沟槽中的一部分第一导电材料与半导体衬底隔开。
在一些实施例中，一个或多个其他沟槽都具有一部分第一绝缘层，沿底部和沟槽的至少一个侧壁内衬。
在一些实施例中，形成在有源晶胞区之外区域中半导体衬底中的一个或多个沟槽，包括在周边区域的周边沟槽，其中周边区域在有源晶胞区和器件的边缘之间。在一些实施例中，周边沟槽中的第二导电材料与半导体衬底被第二绝缘材料隔开。在一些实施例中，每个周边沟槽都有不对称的侧壁绝缘物，其中第一绝缘层在器件边缘附近的一侧，第二绝缘层在有源晶胞区附近的一侧。
在一些实施例中，形成在有源晶胞区之外区域中半导体衬底中的一个或多个其他沟槽，包括在拾起区中的过渡沟槽，其中过渡沟槽在多个栅极沟槽和拾起沟槽之间。在一些实施例中，在过渡沟槽底部的那部分第一导电材料呈U型。在一些实施例中，过渡沟槽中的那部分第三绝缘层呈U型。
本发明的另一个方面是关于一种半导体器件的制备方法。该方法包括：a）利用第一个掩膜，制备多个沟槽，多个沟槽包括位于有源晶胞区中的一个或多个栅极沟槽，以及一个或多个过渡沟槽，一个或多个位于拾起区的拾起沟槽；b）利用第二个掩膜，在多个沟槽中制备带有第一导电材料的第一导电区，其中栅极沟槽在其底部具有第一导电区，一个或多个过渡沟槽都有一个U-型第一导电区，一个或多个拾起沟槽都用第一导电材料填充；c）为多个沟槽中的至少一部分沟槽，制备一个中间电介质区，其中为一个或多个过渡沟槽制备的中间电介质区呈U型；d）在多个沟槽中的至少一部分沟槽中，制备一个带有第二导电材料的第二导电区；e）在有源晶胞区中制备一个或多个本体区；f）利用第三个掩膜，在有源晶胞区中制备源极区；g）利用第四个掩膜，在一个或多个过渡沟槽中，形成到第二导电区的第一电接触，在一个或多个拾起沟槽中，形成到第一导电区的第一电接触；h）利用第五个掩膜，在栅极沟槽中，形成到第二导电区的第二电接触；i）沉积一个金属层；以及j）利用第六个掩膜，制成由金属层构成的源极金属区和栅极金属区。
阅读实施例的以下详细说明并参照各种附图，本发明的这些特点和优势对于本领域的技术人员来说，无疑将显而易见。
附图说明
图1表示依据本发明的一个方面，一种分裂栅晶体管器件的俯视示意图。
图2表示沿图1所示的线I、II和III的剖面示意图。
图3A-3H表示依据本发明的一个方面，沿图1所示的线I、II和III的剖面示意图，用于说明分裂栅晶体管器件的制备过程。
具体实施方式
图1表示依据本发明的一个方面，一部分分裂栅晶体管器件的俯视图。图1所示的分裂栅晶体管器件100包括在有源晶胞区101中的多个阵列分布的分裂栅沟槽110，在周边区102的一个周边沟槽，以及在拾起区103的一个过渡阵列沟槽以及一个拾起沟槽。图2表示沿图1所示的线I、II和III的剖面示意图。确切地说，在有源晶胞区101中，每个分裂栅沟槽110都有一个底部电极113（即屏蔽电极）以及一个顶部电极115（即栅极电极）。形成在沟槽底部的底部电极113，通过一个内衬绝缘材料112（即内衬氧化物或屏蔽氧化物），例如氧化物或氮化物，与半导体衬底电绝缘，内衬绝缘材料可以覆盖分裂栅沟槽110的侧壁，底部电极113就形成在分裂栅沟槽110中。顶部电极115形成在底部电极和衬底104表面之间的分裂栅沟槽的顶部。顶部电极115通过绝缘材料116（即栅极氧化物），例如氧化物或氮化物，与半导体衬底104隔开，并通过中间多晶硅电介质层114，与底部电极113隔开。在一些实施例中，栅极氧化物116的厚度小于中间多晶硅电介质层114的厚度，中间多晶硅电介质层114的厚度小于内衬绝缘材料112的厚度。
周边沟槽120形成在周边区102中。周边沟槽在底部、器件边缘附近的侧壁和栅极沟槽110附近的底部侧壁上内衬氧化物112，沿栅极沟槽110附近的顶部侧壁，内衬栅极氧化物116。周边沟槽120中的栅极电极115位于靠近栅极沟槽110的顶角中，屏蔽电极113在栅极电极115下方呈半U型，半U型的中间电介质层114将栅极电极115和屏蔽电极113分开。
过渡沟槽130和拾起沟槽140形成在拾起区103中。过渡沟槽130沿沟槽的侧壁和底部，具有内衬绝缘物112，例如氧化物。过渡沟槽130中的栅极电极115位于沟槽的中上部，屏蔽电极113呈U型，栅极电极115嵌入在U型的开口中。U型的中间电介质层114将栅极电极115和屏蔽电极113分开。拾起沟槽140包括一个屏蔽电极113，内衬绝缘物112沿沟槽的侧壁和底部。
图3A-3H表示依据本发明的一个方面，沿图1所示的线I、II和III的剖面示意图，用于说明栅极晶体管器件的制备过程。采用一个N-型器件用于解释说明。要注意的是，使用导电类型相反的类似过程，可以制备P-型器件。在图3A中，N-型衬底104（例如生长着一个N-外延层的N+硅晶圆）用作器件的漏极。在一些实施例中，衬底104顶部的掺杂浓度约为1×1016-1×1017/cm3，厚度为2-4μm。在衬底104上方使用一个硬掩膜层，例如通过沉积或热生长，在衬底104上制备一个薄氧化层105，然后在薄氧化层105上方制备一个氮化层106。在一些实施例中，氧化层105在100??至500??范围内，最好是200??左右。在一些实施例中，氮化层106的厚度约为1500??至4000??，最好是3500??左右。在氮化层106上方可以沉积另一个氧化层107，形成带有氧化物/氮化物/氧化物堆栈的硬掩膜。在一些实施例中，氧化层107的厚度约为1000??至3000??，最好是2000??左右。然后，在氧化物/氮化物/氧化物堆栈上使用一个光致抗蚀剂层（图中没有表示出），并利用沟槽掩膜，形成图案。然后，通过硬掩膜刻蚀，刻蚀掉氮化层106、氧化层107和105的裸露部分，在硅表面处停止刻蚀，保留将用于掩膜沟槽刻蚀的开口。在半导体衬底104中刻蚀沟槽开口，在有源晶胞区101中形成栅极沟槽110，在周边区102中形成一个周边沟槽120，在拾起区103中形成一个过渡沟槽130和一个拾起沟槽104。在一些实施例中，这些沟槽的目标深度约为0.6-1.5μm，最好是1.0μm左右。栅极沟槽110之间或栅极沟槽110和周边沟槽120之间的衬底区域111，有时可称为台面结构区。
在图3B中，通过氧化，生长一个内衬氧化层112。根据器件低Rds和高击穿电压的优化要求，在沟槽壁上生长一个厚内衬绝缘层112到一定厚度。在一些实施例中，内衬绝缘层的厚度约为400-800??，最好是600??左右。然后，在沟槽中和半导体衬底104上方，沉积第一导电材料113，例如多晶硅，通过化学机械抛光（CMP）除去氧化层107上方的多晶硅，仅保留栅极沟槽110、过渡沟槽130以及拾起沟槽140中的导电材料。回刻沟槽110、130和140中的第一导电材料层113，在衬底104表面下方100-600??（例如在衬底104表面下方300??左右的地方）处停止刻蚀。第一层导电材料113有时称为源极多晶硅、屏蔽多晶硅或多晶硅1。
参见图3C，在氧化物/氮化物/氧化物堆栈的顶部，使用一个光致抗蚀剂层150（例如多晶硅1掩膜），覆盖拾起沟槽140、过渡沟槽130的两边以及周边沟槽120靠近器件边缘的一侧。然后，如图3C所示，在栅极沟槽110、周边沟槽120以及过渡沟槽130的顶部，回刻裸露的第一导电材料113。由于刻蚀保留了周边沟槽120中的半U型导电材料113以及过渡沟槽中的U型导电材料113，因此要以保护内衬绝缘物112以及周边沟槽120、过渡沟槽130和拾起沟槽140中至少一部分第一导电材料113的一种方式，形成光致抗蚀剂层150的图案。在一个示例中，利用定时的回刻工艺，可以将第一导电材料层113刻蚀到目标深度。在一些实施例中，导电材料层113刻蚀到半导体衬底104的表面下方0.55μm左右的深度。
参见图3D，沿栅极沟槽110刻蚀后的顶部以及周边沟槽120，例如利用湿刻蚀，剥去裸露的内衬绝缘物112。制备薄绝缘层116（例如栅极氧化物），覆盖栅极沟槽110的沟槽侧壁顶部。另外，靠近周边沟槽120的栅极沟槽110的沟槽壁的顶部，也内衬栅极绝缘物116。然后，在分裂栅沟槽110的第一导电材料层113的底部上方，制备一个中间电介质层114。也沿周边沟槽120和过渡沟槽130中的导电材料层113，制备（例如通过氧化）中间电介质层114，使中间电介质层114在周边沟槽120中呈半U型，在过渡沟槽130中呈U型。栅极氧化物116的厚度约为150至500??，中间多晶硅电介质层114的厚度约为250至800??。
第二层导电材料115（例如多晶硅）沉积在沟槽110、120和130的顶部以及衬底104上方，通过CMP，除去氧化层107和光致抗蚀剂层150上方的多晶硅。在多晶硅的具体情况下，第二导电层115的导电材料有时也称为栅极多晶硅或多晶硅2。然后，将第二导电层115（有时也称为栅极导体）回刻至100??-600??，例如衬底表面以下300??左右，使沟槽110、120和130中第二导电材料的顶面凹向半导体衬底104的顶面以下。除去光致抗蚀剂150之后，在沟槽110、120、130和140中进行另一个氧化工艺，形成绝缘层152，然后通过CMP，除去氮化层106上方的氧化物152以及氧化层107。
参见图3E，利用湿刻蚀，剥去氮化层106。然后，利用本体掺杂注入，形成多个本体区。本次注入，例如，通过全面注入以及本体扩散，形成本体区154。本体驱动使掺杂物扩散到所需深度。然后，利用源极掩膜，进行源极掺杂注入，在有源晶胞区101中形成多个源极区156。在结构顶部以上，沉积一层氮化物。在一个示例中，氮化层的厚度约为600至1200??，例如900??左右。沿水平表面，各向异性地回刻氮化层，从而沿氧化物152附近的壁，形成氮化物垫片157。然后，在该结构上方沉积一个氮化物阻挡层158。在一个示例中，氮化物阻挡层158的厚度约为200??至500??，例如300??左右。然后，如图3E所示，沉积一个低温氧化物（LTO）层和一个含有硼酸的硅玻璃（BPSG）层159。
参见图3F，使用第一接触掩膜。在拾起区103中，利用刻蚀工艺，刻蚀ONO堆栈（LTO层159、氮化物阻挡层158、氧化物152），以触及顶部导电材料的表面（即过渡沟槽130中的导电材料115和拾起沟槽140中的导电材料113），形成穿过LTO层159的接触开口155S和155G，从而在区域II和III中分别接触到屏蔽导体113和栅极导体115。
在图3G中，使用另一个接触掩膜160，通过另一个刻蚀工艺，在有源晶胞区101中栅极沟槽110之间的台面结构区111中，打开源极和本体接触开口的阵列。确切地说，刻蚀工艺从LTO层159开始，在氮化物阻挡层158处停止。随着氮化物阻挡层158的击穿，接触沟槽162就形成了。
然后，在接触开口155S和155G以及接触沟槽162的侧壁和底部，内衬势垒金属（图中没有表示出），并在接触开口和接触沟槽中沉积导电材料（例如钨），形成导电插头164。沉积一层金属。利用金属掩膜，通过刻蚀工艺，形成一个源极金属区166和栅极金属区168和170。如图3H所示，所形成的导电插头164连接到金属区。然后，根据标准沟槽MOSFET的剩余步骤，处理晶圆，完成整个过程。
本发明所述的制备工艺，利用一个更少的掩膜，保留厚内衬绝缘物112。无需P-掩膜，保护周边沟槽120中的内衬氧化物112。这使得整个制备过程更加便宜。在绝缘物刻蚀过程中，构成屏蔽电极的导电材料113保护内衬绝缘物112，为屏蔽导体113和栅极导体115的接头形成开口。
尽管本发明依据现有的较佳实施例进行了详细说明，但应明确本说明并不用于局限。例如，虽然上述说明是指n-通道器件，但是通过转换掺杂区的导电类型，就可将本发明用于p-通道器件。阅读上述说明后，本发明的各种可选和修正方案对于本领域的技术人员无疑将显而易见。因此，应由所附的权利要求书及其全部等效内容决定本发明的真实意图及范围。

Claims (22)

1.一种半导体器件，其特征在于，包括：
多个栅极沟槽，形成在有源晶胞区中的半导体衬底中，每个栅极沟槽都有第一导电材料在栅极沟槽底部，以及第二导电材料在栅极沟槽顶部，其中栅极沟槽中的第一导电材料与半导体衬底被第一绝缘层隔开，栅极沟槽中的第二导电材料与半导体衬底被第二绝缘层隔开，并且栅极沟槽中的第二导电材料与栅极沟槽中的第一导电材料被第三绝缘层隔开；以及
一个或多个其他沟槽，形成在有源区之外的区域中的半导体衬底中，其中所述的一个或多个其他沟槽至少包含在所述一个或多个其他沟槽底部呈半U型的部分第一导电材料，以及在所述一个或多个其他沟槽顶部的部分第二导电材料，其中所述的一个或多个其他沟槽中的第一导电材料和第二导电材料被第三绝缘层隔开。
2.如权利要求1所述的半导体器件，其特征在于，所述的半导体衬底为N-型半导体衬底。
3.如权利要求1所述的半导体器件，其特征在于，所述的半导体衬底为P-型半导体衬底。
4.如权利要求1所述的半导体器件，其特征在于，还包括一个或多个拾起沟槽，形成在拾起区中的半导体衬底中，所述的一个或多个拾起沟槽连接到一个或多个所述的栅极沟槽，所述的一个或多个拾起沟槽至少包含部分第一导电材料，第一绝缘层将所述的一个或多个拾起沟槽中的部分第一导电材料与半导体衬底隔开。
5.如权利要求1所述的半导体器件，其特征在于，所述的一个或多个其他沟槽都有一部分第一绝缘层，沿沟槽底部和至少一个沟槽侧壁内衬。
6.如权利要求1所述的半导体器件，其特征在于，形成在有源晶胞区以外区域的半导体衬底中的所述一个或多个其他沟槽，是周边区中的周边沟槽，所述的周边区位于有源晶胞区和器件的边缘之间。
7.如权利要求6所述的半导体器件，其特征在于，所述的周边沟槽中的部分第二导电材料与半导体衬底被第二绝缘材料隔开。
8.如权利要求6所述的半导体器件，其特征在于，所述的每个周边沟槽都有不对称的侧壁绝缘，第一绝缘层在器件边缘附近的一侧，第二绝缘层在有源晶胞区附近的一侧。
9.如权利要求1所述的半导体器件，其特征在于，还包括形成在有源晶胞区以外的拾起区中的一个或多个过渡沟槽，所述的过渡沟槽位于多个栅极沟槽和一个拾起沟槽之间。
10.如权利要求9所述的半导体器件，其特征在于，所述的过渡沟槽底部的部分第一导电材料呈U型。
11.如权利要求10所述的半导体器件，其特征在于，所述的在过渡沟槽中的部分第三绝缘层呈U型。
12.如权利要求1所述的半导体器件，其特征在于，所述的第一绝缘层的厚度大于第三绝缘层的厚度，第三绝缘层的厚度大于第二绝缘层的厚度。
13.一种半导体器件的制备方法，其特征在于，包括：
在有源晶胞区中的半导体衬底中，制备多个栅极沟槽，每个栅极沟槽都有第一导电材料，在栅极沟槽底部，以及第二导电材料，在栅极沟槽顶部，其中，栅极沟槽中的第一导电材料与半导体衬底被第一绝缘层隔开，并且栅极沟槽中的第二导电材料与半导体衬底被第二绝缘层隔开，与栅极沟槽中的第一导电材料被第三绝缘层隔开；并且
在有源晶胞区之外的区域中的半导体衬底中，制备一个或多个其他沟槽，每个所述的其他沟槽都用在沟槽底部呈半U型的第一导电材料以及在沟槽顶部的第二导电材料填充，所述的其他沟槽中的第一导电材料和第二导电材料被第三绝缘层隔开。
14.如权利要求13所述的制备方法，其特征在于，所述的第一绝缘层的厚度大于第三绝缘层的厚度，第三绝缘层的厚度大于第二绝缘层的厚度。
15.一种半导体器件的制备方法，其特征在于，包括：
利用第一个掩膜，在半导体衬底中制备多个沟槽，多个沟槽至少包括位于有源晶胞区中的栅极沟槽，以及位于拾起区中的一个或多个过渡沟槽和一个或多个拾起沟槽；
利用第二个掩膜，在所述的多个沟槽中制备带有第一导电材料的第一导电区，所述的栅极沟槽在它们的底部具有第一导电区，所述的一个或多个过渡沟槽具有U型第一导电区，所述的一个或多个拾起沟槽用第一导电材料填充；
为所述的多个沟槽中的至少部分沟槽制备一个中间电介质区，所述的一个或多个过渡沟槽的中间电介质区呈U型；
在所述的多个沟槽中的至少部分沟槽中，制备带有第二导电材料的第二导电区；
在所述的半导体衬底中制备一个本体区；
利用第三个掩膜，在有源晶胞区中制备源极区；
利用第四个掩膜，在所述的一个或多个过渡沟槽中，形成到第二导电区的第一电接触，并且在所述的一个或多个拾起沟槽中，形成到第一导电区的第一电接触；
利用第五个掩膜，在所述的栅极沟槽中，形成到第二导电区的第二电接触；
沉积一个金属层；并且
利用第六个掩膜，制成由金属层构成的源极金属区和栅极金属区。
16.如权利要求15所述的制备方法，其特征在于，所述的多个沟槽还包括一个或多个周边沟槽，在有源晶胞区和半导体器件边缘之间的周边区中，所述的一个或多个周边沟槽具有一个半U型的第一导电区。
17.如权利要求15所述的制备方法，其特征在于，所述的一个或多个拾起沟槽连接到一个或多个所述的栅极沟槽，所述的一个或多个拾起沟槽至少包括部分第一导电材料，第一绝缘层将所述的一个或多个拾起沟槽中的第一导电材料与半导体衬底隔开。
18.如权利要求17所述的制备方法，其特征在于，所述的每个沟槽都具有部分第一绝缘层，内衬沟槽底部以及至少一个沟槽侧壁。
19.如权利要求17所述的制备方法，其特征在于，所述的一个或多个过渡沟槽包括一个位于有源晶胞区和器件边缘之间的沟槽。
20.如权利要求16所述的制备方法，其特征在于，所述的周边沟槽中的部分第二导电材料与半导体衬底被第二绝缘层隔开。
21.如权利要求16所述的制备方法，其特征在于，所述的每个周边沟槽都具有不对称的侧壁绝缘，第一绝缘层在器件边缘附近的一侧，第二绝缘层在有源晶胞区附近的一侧。
22.如权利要求15所述的制备方法，其特征在于，所述的过渡沟槽位于多个栅极沟槽和一个拾起沟槽之间。
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