CN105826386A - 带有高纵横比沟槽接头以及沟槽间亚微米间距的功率器件 - Google Patents

带有高纵横比沟槽接头以及沟槽间亚微米间距的功率器件 Download PDF

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CN105826386A
CN105826386A CN201610033164.3A CN201610033164A CN105826386A CN 105826386 A CN105826386 A CN 105826386A CN 201610033164 A CN201610033164 A CN 201610033164A CN 105826386 A CN105826386 A CN 105826386A
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trench
power device
contact
semiconductor substrate
semiconductor power
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李文军
保罗·托鲁普
常虹
李亦衡
向泱
邓觉为
薛宏勇
顾鸣
顾一鸣
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Alpha and Omega Semiconductor Ltd
Alpha and Omega Semiconductor Inc
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Alpha and Omega Semiconductor Inc
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Abstract

本发明提出了一种位于半导体衬底中的半导体功率器件，该半导体功率器件包含一个有源晶胞区和一个端接区。该半导体功率器件还包含多个栅极沟槽，形成在有源晶胞区中半导体衬底的顶部，其中每个栅极沟槽都用导电栅极材料部分填充，沟槽的顶部用高密度等离子（HDP）绝缘层填充。该半导体功率器件还包含位于栅极沟槽之间的半导体衬底的台面结构区，其中台面结构区凹陷下去，顶部台面结构表面垂直位于HDP绝缘层的顶面以下，其中覆盖在导电栅极材料上方的HDP绝缘层构成一个凸起边界限定层，包围着栅极沟槽之间有源晶胞区中的凹陷台面结构区。

Description

带有高纵横比沟槽接头以及沟槽间亚微米间距的功率器件
技术领域
本发明涉及关于半导体功率器件的制备工艺及结构尤其涉及带有临界尺寸改良后的深接触沟槽的制备工艺和结构配置，在深沟槽接头之间具有缩小的距离。
背景技术
制备半导体功率器件的传统方法，仍然面临在高纵横比以及沟槽间微小间距的沟槽中，制备电接触的技术局限。这种技术局限经常成为阻碍进一步减小电子器件尺寸和维度的瓶颈。基于这些原因，目前已采用多种技术，以试图克服这些局限。
采用光刻工艺的传统技术，用于限定打开接触沟槽的图案。通常来说，利用掩膜，选择性地曝光光致抗蚀剂层，沉积光致抗蚀剂层并形成图案，以限定打开接触沟槽的位置。然而，由于难以准确对齐，这些工艺往往受到限制。另外，光刻曝光的焦点深度以及分辨率还会引起需要制造公差的偏差和不准确，并且阻碍制备工艺的能力，以制备带有亚微米间距的接触沟槽的器件。
在Xu等人的专利8629019中，提出了一种用于沟槽功率MOSFET的自对准接头的制备方法。该方法包含通过沉积在氧化层上的氮化硅掩膜，在衬底中刻蚀沟槽，在沟槽壁上制备一个栅极氧化层。然后，通过用多晶硅层填充栅极沟槽，利用沟槽侧壁上的栅极氧化层，自对准栅极总线。与之类似，用于源极和本体区的接触窗口，也限定在氮化硅中，以便在氧化层上方刻蚀氮化硅，覆盖在源极和本体区上方。在这些接触窗口的侧壁上，生长垫片，自对准沉积在这些接触窗口中的接触金属，接触窗口作为氮化硅层中的沟槽，在侧壁上具有垫片。在本专利中Xu等人提出的方法，仍然受到首次使用掩膜的局限，限定覆盖在器件顶面上方的氮化硅层上的位置。由于要允许微小程度的误差需要公差，以便在平整表面上放置掩膜，因此仍然受到局限，阻碍减小沟槽接头之间的间距。即使Xu等人提出的不同的接触金属，以自对准方式形成在接触沟槽中，但是接触沟槽本身没有利用自对准工艺制成。
因此，对于本领域的技术人员来说，有必要改善功率器件的制备方法，尤其是精确形成在功率器件的整个顶面区域上方不同位置的沟槽接头，以解决上述技术局限。
发明内容
本发明的目的在于提出结构特点和器件配置的新型改良的制备方法，以便通过自对准工艺精确放置接触沟槽，从而克服背景技术中的困难与局限。
本发明的一个方面在于，提出了半导体功率器件新型改良的制备方法，利用选择性刻蚀工艺，制备自对准结构可选件，在沟槽栅极之间的台面结构区域带有凹槽，凹槽的侧壁限定沟槽接头位置的外边缘。从而解决了传统制备工艺中遇到的，相对于沟槽栅极来说不准确放置掩膜所需公差的难题。
本发明的另一方面在于提出半导体功率器件的新型改良的制备方法，通过在外延层的凹陷侧壁上进一步进行氧化物垫片，从而进一步缩小和限定凹陷中心处沟槽接头的位置。因此，通过精确限定的位置，无需使用传统方法的掩膜，就可以进行高纵横比的接触沟槽刻蚀工艺。以完全自对准的方式，精确限定接触沟槽的位置在台面结构区域中的源极和本体区正中央。
因此，利用本发明所述的制备工艺，还可以精确地限定沟槽之间的距离，并且无需传统方法中要求的不确定性和公差，以便减小功率器件的晶胞间距。
在一个较佳实施例中，本发明提出了一种位于半导体衬底中的半导体功率器件。该半导体功率器件包含一个有源晶胞区和一个端接区。该半导体功率器件还包含多个栅极沟槽，形成在有源晶胞区中半导体衬底的顶部，其中每个栅极沟槽都用导电栅极材料部分填充，沟槽的顶部用高密度等离子（HDP）绝缘层填充。该半导体功率器件还包含位于栅极沟槽之间的半导体衬底的台面结构区，其中台面结构区凹陷下去，顶部台面结构表面垂直位于HDP绝缘层的顶面以下，其中覆盖在导电栅极材料上方的HDP绝缘层构成一个凸起边界限定层，包围着栅极沟槽之间有源晶胞区中的凹陷台面结构区。
在一个较佳实施例中，本发明还提出了一种在半导体衬底上制备半导体功率器件的方法，半导体功率器件包含一个有源晶胞区和一个端接区。该方法包含以下步骤：a）在有源晶胞区中半导体衬底的顶部，打开多个栅极沟槽，并用导电栅极材料填充每个栅极沟槽，然后从沟槽顶部刻蚀掉导电栅极材料；b）沉积高密度等离子（HDP）氧化层，并且在顶面上方制备BPSG绝缘层，然后利用自对准接触（SAC）光致抗蚀剂掩膜，进行自对准接触刻蚀，以便从未覆盖区域中半导体衬底的顶面，除去BPSG绝缘物和HDP氧化层；以及c）进行台面结构凹陷刻蚀，以刻蚀半导体衬底，形成台面结构凹陷，顶部台面结构表面垂直在HDP绝缘层的顶面下方，覆盖在导电栅极材料上方，构成一个凸起边界限定层，包围着栅极沟槽之间有源晶胞区中的凹陷台面结构区。
阅读以下详细说明并参照附图之后，本发明的这些和其他的特点和优势，对于本领域的技术人员而言，无疑将显而易见。
附图说明
图1A和1B表示利用本发明所述的方法和结构可选件，制备半导体功率器件的侧剖面图。
图1C表示半导体功率器件的特殊结构可选件的侧剖面图，用于图1A所示的器件。
图2A至2T表示图1和1A所示本发明所述的半导体功率器件的制备工艺的一系列剖面图。
具体实施方式
图1A表示利用本发明所述的工艺步骤，制备带有深沟槽接触结构的功率器件的侧剖面图。功率器件位于N-型外延层110中，N-型外延层110形成在N-型半导体衬底（图中没有表示出）上方。半导体功率器件包含一个有源晶胞区，在顶部源极金属190-S覆盖的区域以及被栅极衬垫金属层190-G覆盖的端接区上方延伸。功率器件包含多个沟槽栅极130，形成在垫有栅极氧化层120的深沟槽115中，每个沟槽栅极都被P-型本体区150包围，本体区150包围着N-型源极区160。功率器件还包含多个源极/本体接头180，作为深沟槽接头180。每个深接触沟槽都穿过HDP氧化层145，在源极区160下方垂直延伸，然后穿过本体区160的顶部，触及形成在本体区150中的接触注入区170，并用金属层填充，构成源极/本体接头180。每个源极/本体接头180还直接接触到源极金属190-S，覆盖在HDP氧化层145的顶部和垫片层165上方。源极/本体接头180的中心，与两个邻近的有源沟槽115之间的台面结构中心对准。然而，在最后一个有源沟槽115和栅极拾取沟槽115’之间的台面结构中，源极/本体接头180”偏离台面结构的中心，更靠近最后一个有源沟槽。在本实施例中，半导体功率器件还包含一个本体箝位层（BCL）140，作为硼注入层，用于嵌制BVdss。多晶硅栅极拾取130’形成在深栅极拾取沟槽115’中，垫有栅极氧化层120，通过拾取接头180’触及金属层190-G金属层，穿过HDP氧化层145和BPSG层148，垂直延伸穿过多晶硅栅极拾取130’的顶部，栅极拾取130’的宽度大于有源晶胞区中沟槽栅极130的宽度。分隔源极金属190-S和栅极金属190-G的缝隙g延伸穿过HDP氧化层145及BPSG层148的边缘，缝隙g与更靠近有源沟槽115的栅极拾取沟槽115’的沟槽侧壁对准。
图1B表示本发明的一种可选功率器件的侧剖面图，该器件除了端接区不包含BCL层140之外，其他都与图1A所示的功率器件类似。
图1C表示图1A所示器件的半导体功率器件的专用结构可选件。确切地说，源极/本体沟槽接头180的宽度减至0.1至0.2微米，例如0.13微米，深接触沟槽之间的间距减至0.2至0.3微米，例如0.25微米。
图2A至2T表示依据本发明的结构和方法，为减小图1A所示半导体功率器件的晶胞间距，制备深沟槽接触结构的工艺步骤的一系列侧剖面图。在图2A中，热氧化层112为硬掩膜，生长在N-型外延层上方。外延层110形成在N-型半导体衬底（图中没有表示出）上方。热氧化层112的厚度大约为2700埃。在图2B中，对于有源沟槽来说沟槽光致抗蚀剂掩膜113的临界尺寸（CD）约为0.25微米，对于栅极拾取沟槽来说，其临界尺寸约为0.9微米，沟槽光致抗蚀剂掩膜113用于使硬掩膜112形成图案，构成沟槽硬掩膜层112’，然后除去掩膜113，如图2C所示。
在图2D中，通过刻蚀工艺，打开沟槽115、115’，有源沟槽115的沟槽深度约为1.45微米。打开的沟槽侧壁与衬底的顶面并不完全垂直，而是呈86.5度角。沟槽刻蚀工艺之后，进行CARO清洁工艺，具有1200埃左右层厚的一部分硬掩膜112’仍然存在。在图2E中，利用带有HF的标准清洁1（SC1）工艺，进行牺牲氧化物预清洁工艺，除去厚度50埃左右的氧化层，然后生长另一个100埃左右的牺牲氧化层，除去130埃的目标氧化层。然后呈现出厚度310埃左右的栅极氧化层120，覆盖在沟槽侧壁上方。剩余硬掩膜氧化层112’的厚度约为1000埃。在图2F中，原位磷掺杂多晶硅层130”沉积在沟槽115、115’中以及硬掩膜112’的表面上方，通过化学-机械平整（CMP）工艺，使多晶硅层130”和硬掩膜层112’的顶面平整，如图2G所示。剩余硬掩膜层112’的厚度约为800埃。然后利用CARO进行预退火清洁工艺，标准的清洁1（SC1）和标准的清洁2（SC2）清洁工艺，然后在1150摄氏度左右的温度下在多晶硅层130”上进行多退火工艺。
在图2H中，继续利用BCL光致抗蚀剂掩膜132，进行BCL注入的多个步骤。在一个典型实施例中，注入包含：a）在2100Kev下，注入掺杂浓度为2E15cm-3的BF2掺杂物；b）在100Kev下，注入掺杂浓度为1E15cm-3的硼掺杂物；c）在460Kev下，注入掺杂浓度为2E12cm-3的硼掺杂物；以及d）在700Kev下，注入掺杂浓度为2E12cm-3的硼掺杂物，以构成BCL区140。在图2I中，除去BCL注入掩膜132，首次进行氧化物突破刻蚀，除去硬掩膜氧化层130”上方300埃的硬掩膜氧化层122’的顶部。然后，通过多晶硅回刻工艺，将多晶硅层130”刻蚀到硅衬底110顶面下方约0.4微米的深处，在沟槽115和115’中构成沟槽栅极130和多晶硅拾取栅极130’。剩余的硬掩膜氧化层厚度约为200埃。
在图2J中，制备工艺继续沉积层厚3000埃左右的HDP氧化层145，然后在HDP氧化层145上方制备层厚约为4300埃左右的BPSG层148。在图2K中，利用自对准接触（SAC）光致抗蚀剂掩膜149，进行自对准接触氧化物刻蚀，从未覆盖的部分上除去HDP氧化层145和BPSG层148，并且在硅衬底110的顶面停止，带掩膜的刻蚀之后，HDP氧化层145和BPSG层148的边缘对准到栅极拾取沟槽115’的沟槽侧壁，更靠近有源沟槽115。在图2L中，利用台面结构凹陷刻蚀，刻蚀硅衬底，形成凹陷深度0.3微米左右的台面结构凹陷155。在图2M中，除去光致抗蚀剂掩膜149，然后在100Kev和600Kev之间的能量水平下，用硼离子进行全面本体注入，构成本体区150。在图2N中，继续通过全面注入，在80Kev下利用掺杂浓度约为4E15cm-3的砷掺杂物，制备源极区160，然后在950摄氏度下进行30秒退火工艺。在图2O中，利用低温氧化物沉积，在结构上方制备一个800埃左右的薄氧化层，通过全面氧化物刻蚀工艺（例如等离子体干刻蚀）在氧化层145的每个侧面形成一个氧化物垫片。然后，在图2P中，进行接触刻蚀（例如等离子体干刻蚀），打开接触开口168，在台面结构表面下方接触沟槽的深度为0.25微米。如图2O所示，两个有源沟槽115之间的台面结构上方，一对垫片165是通过台面结构的中心对称的，以致于接触开口168的中心与台面结构的中心基本对准。然而，在最后一个有源沟槽115和栅极拾取沟槽115’之间的台面结构中，连接到氧化层145和BPSG层148边缘的垫片165”，比连接到最后一个有源沟槽115上方氧化层145侧面上的垫片165和垫片165’更厚且更高，以致于垫片165’和165”形成的接触开口的中心，偏离最后一个有源沟槽115和栅极拾取沟槽115’之间的台面结构的中心，而是更靠近最后一个有源沟槽115。垫片165’的尺寸与垫片165的尺寸基本相同。在图2Q中，在接触沟槽168的底部制备接触注入物170，例如在20Kev下掺杂浓度1E14cm-3的BF2掺杂物。在图2R中，利用多晶硅拾取接触掩膜172，打开多晶硅拾取接触沟槽174。
在图2S中，除去掩膜172，通过快速热退火（RTA），在开口168和174（图中没有表示出）的侧面沉积势垒层，例如Ti/TiN势垒层，然后用钨填充接触沟槽168和174并回刻，以形成钨插头（W-插头）180、180’和180”，源极/本体接头180的中心与两个邻近有源沟槽115之间的台面结构的中心基本对准，源极/本体接头180”偏离对应台面结构的中心，更靠近最后一个有源沟槽115。在图2T中，通过制备源极接头190-S和栅极衬垫190-G并形成图案，以及标准的钝化制备和形成图案（没有明确表示出），完成制备工艺。如上所述，隔开源极金属190-S和栅极金属190-G的缝隙g，穿过HDP氧化层145和BPSG层148的边缘延伸，与更靠近有源沟槽115的栅极拾取沟槽115’的沟槽侧壁基本对准。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (22)

1.一种位于半导体衬底中的半导体功率器件，其特征在于，包含一个有源晶胞区和一个端接区，其中半导体功率器件还包含：
多个栅极沟槽，形成在有源晶胞区中半导体衬底的顶部，其中每个栅极沟槽都用导电栅极材料部分填充，沟槽顶部由高密度等离子体HDP绝缘层填充；以及
位于栅极沟槽之间的半导体衬底的台面结构区，其中台面结构区相对于HDP绝缘层的顶面凹陷，顶部台面结构表面位于HDP绝缘层的顶面下方，其中HDP绝缘层覆盖在导电栅极材料上方，构成凸起边缘限定层，包围着栅极沟槽之间的有源晶胞区中的凹陷台面结构区。
2.如权利要求1所述的半导体功率器件，其特征在于，还包含：
低温氧化层LTO，连接到HDP绝缘层的侧壁，LTO层限定台面结构-中心区位于凹陷台面结构区的中心部分，用于刻蚀台面结构中心区的接触沟槽。
3.如权利要求2所述的半导体功率器件，其特征在于，还包含：
限定在台面结构中心区的半导体衬底中向下垂直打开的接触沟槽。
4.如权利要求3所述的半导体功率器件，其特征在于，还包含：
位于接触沟槽的底面下的半导体衬底中的接触注入区。
5.如权利要求3所述的半导体功率器件，其特征在于，还包含：
填充接触沟槽的导电接触材料。
6.如权利要求4所述的半导体功率器件，其特征在于，还包含：
填充接触沟槽并且连接在接触沟槽的底面以下的接触注入区的导电接触材料。
7.如权利要求1所述的半导体功率器件，其特征在于，还包含：
位于凹陷台面结构区下方的半导体衬底中的本体区，每个包围着本体区顶部的导电类型相反的源极区。
8.如权利要求6所述的半导体功率器件，其特征在于，还包含：
位于凹陷台面结构区下方的半导体衬底中的本体区，每个都包围着在本体区顶部的导电类型相反的源极区，其中接触沟槽穿过源极区，连接位于接触沟槽底面下方的接触注入区，接触沟槽位于本体区中。
9.如权利要求8所述的半导体功率器件，其特征在于，还包含：
一个源极金属层位于HDP层和接触沟槽上方的，与填充接触沟槽的导电材料相接触，以便电连接到源极区和本体区。
10.如权利要求8所述的半导体功率器件，其特征在于，还包含：
导电类型与本体区相同的本体箝位层BCL，在有源晶胞区外围区域中栅极沟槽的底面下方垂直延伸。
11.如权利要求3所述的半导体功率器件，其特征在于，其中：
接触沟槽的宽度约为0.1至0.15微米。
12.如权利要求1所述的半导体功率器件，其特征在于，其中：
栅极沟槽的宽度约为0.25微米，邻近栅极沟槽之间的距离约为0.5微米。
13.在半导体衬底中制备含有有源晶胞区和端接区的半导体功率器件的方法，其特征在于，该方法包含：
在有源晶胞区中半导体衬底的顶部，打开多个栅极沟槽，并用导电栅极材料填充每个栅极沟槽，然后从沟槽顶部刻蚀掉导电栅极材料；
沉积高密度等离子HDP因此，并且在顶面上方制备BPSG绝缘层，然后利用自对准接触SAC光致抗蚀剂掩膜，进行自对准接触刻蚀，以便从未覆盖区域中半导体衬底的顶面，除去BPSG绝缘物和HDP氧化层；并且
进行台面结构凹陷刻蚀，以刻蚀半导体衬底，形成台面结构凹陷，顶部台面结构表面垂直在HDP绝缘层的顶面下方，覆盖在导电栅极材料上方，构成一个凸起边界限定层，包围着栅极沟槽之间有源晶胞区中的凹陷台面结构区。
14.如权利要求13所述的方法，其特征在于，还包含：
在HDP绝缘层的侧壁上沉积低温氧化层LTO，用于限定凹陷台面结构区中心部分中的台面结构中心区。
15.如权利要求14所述的方法，其特征在于，还包含：
通过台面结构区刻蚀半导体衬底，打开接触沟槽。
16.如权利要求15所述的方法，其特征在于，还包含：
在接触沟槽底面下方的半导体衬底中，制备接触注入区。
17.如权利要求16所述的方法，其特征在于，还包含：
用导电接触材料填充接触沟槽。
18.如权利要求13所述的方法，其特征在于，还包含：
在凹陷台面结构区下方的半导体衬底中注入本体区，然后在本体区的顶部注入导电类型相反的源极区。
19.如权利要求18所述的方法，其特征在于，还包含：
在HDP绝缘层的侧壁上沉积低温氧化层LTO，用于限定凹陷台面结构区中心部分中的台面结构中心区；
通过台面结构区刻蚀半导体衬底，打开接触沟槽，穿过源极区，接触沟槽位于本体区中，在接触沟槽底面下方的半导体衬底中，制备接触注入区；并且
用导电接触材料填充接触沟槽。
20.如权利要求15所述的方法，其特征在于，其中：
打开接触沟槽的工艺包含打开宽度在0.1至0.15微米左右的接触沟槽。
21.如权利要求13所述的方法，其特征在于，其中：
打开栅极沟槽的工艺包含打开宽度约为0.25微米的栅极沟槽，邻近栅极沟槽之间的距离约为0.5微米。
22.如权利要求18所述的方法，其特征在于，还包含：
制备导电类型与本体区相同的本体箝位层BCL，在有源晶胞区外围区域中的栅极沟槽的底面下方垂直延伸。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107578992A (zh) * 2017-07-17 2018-01-12 中航（重庆）微电子有限公司 自对准源极接触孔的高密度沟槽型器件结构及其制备方法
CN110800113A (zh) * 2017-06-22 2020-02-14 东京毅力科创株式会社 埋入式电力轨道

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017124220A1 (en) * 2016-01-18 2017-07-27 Texas Instruments Incorporated Power mosfet with metal filled deep source contact
IT201700057056A1 (it) 2017-05-25 2018-11-25 St Microelectronics Srl Metodo di fabbricazione autoallineata di un transistore vdmos, e transistore vdmos autoallineato
US10727326B2 (en) * 2017-08-21 2020-07-28 Semiconductor Components Industries, Llc Trench-gate insulated-gate bipolar transistors (IGBTs)
CN109119477B (zh) * 2018-08-28 2021-11-05 上海华虹宏力半导体制造有限公司 沟槽栅mosfet及其制造方法
CN112864018B (zh) * 2019-11-28 2022-07-19 华润微电子（重庆）有限公司 沟槽型场效应晶体管结构及其制备方法
CN113035722A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 具有选择性模制的用于镀覆的封装工艺
CN113035721A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 用于侧壁镀覆导电膜的封装工艺
US11728423B2 (en) 2021-04-22 2023-08-15 Alpha And Omega Semiconductor International Lp Integrated planar-trench gate power MOSFET
EP4160693A1 (en) * 2021-09-29 2023-04-05 Infineon Technologies Austria AG Transistor device a method for producing a transistor device
IT202200003125A1 (it) * 2022-02-21 2023-08-21 St Microelectronics Srl Metodo per la fabbricazione di un transistore mos con porta schermata autoallineata, e transistore mos con porta schermata

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567634A (en) * 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
CN101421832A (zh) * 2004-03-01 2009-04-29 国际整流器公司 沟槽器件的自对准接触结构
US20110241106A1 (en) * 2010-03-31 2011-10-06 Seung-Ryong Lee Semiconductor device with buried gates and method for fabricating the same
US8058670B2 (en) * 2009-06-04 2011-11-15 Force—MOS Technology Corporation Insulated gate bipolar transistor (IGBT) with monolithic deep body clamp diode to prevent latch-up
CN102544100A (zh) * 2010-12-14 2012-07-04 万国半导体股份有限公司 带有集成二极管的自对准沟槽mosfet
CN103208419A (zh) * 2012-01-16 2013-07-17 英飞凌科技奥地利有限公司 具有沟槽触点的半导体晶体管及其形成方法
CN103295888A (zh) * 2012-02-29 2013-09-11 株式会社东芝 半导体装置及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5366914A (en) * 1992-01-29 1994-11-22 Nec Corporation Vertical power MOSFET structure having reduced cell area
KR100704469B1 (ko) * 2001-12-14 2007-04-09 주식회사 하이닉스반도체 반도체 소자 제조 방법
US8629019B2 (en) * 2002-09-24 2014-01-14 Vishay-Siliconix Method of forming self aligned contacts for a power MOSFET
US7910439B2 (en) * 2008-06-11 2011-03-22 Maxpower Semiconductor Inc. Super self-aligned trench MOSFET devices, methods, and systems
US8067304B2 (en) * 2009-01-20 2011-11-29 Alpha And Omega Semiconductor, Inc. Method for forming a patterned thick metallization atop a power semiconductor chip
JP6037499B2 (ja) * 2011-06-08 2016-12-07 ローム株式会社 半導体装置およびその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567634A (en) * 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
CN101421832A (zh) * 2004-03-01 2009-04-29 国际整流器公司 沟槽器件的自对准接触结构
US8058670B2 (en) * 2009-06-04 2011-11-15 Force—MOS Technology Corporation Insulated gate bipolar transistor (IGBT) with monolithic deep body clamp diode to prevent latch-up
US20110241106A1 (en) * 2010-03-31 2011-10-06 Seung-Ryong Lee Semiconductor device with buried gates and method for fabricating the same
CN102544100A (zh) * 2010-12-14 2012-07-04 万国半导体股份有限公司 带有集成二极管的自对准沟槽mosfet
CN103208419A (zh) * 2012-01-16 2013-07-17 英飞凌科技奥地利有限公司 具有沟槽触点的半导体晶体管及其形成方法
CN103295888A (zh) * 2012-02-29 2013-09-11 株式会社东芝 半导体装置及其制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110800113A (zh) * 2017-06-22 2020-02-14 东京毅力科创株式会社 埋入式电力轨道
CN110800113B (zh) * 2017-06-22 2023-06-06 东京毅力科创株式会社 埋入式电力轨道
CN107578992A (zh) * 2017-07-17 2018-01-12 中航（重庆）微电子有限公司 自对准源极接触孔的高密度沟槽型器件结构及其制备方法

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