CN113035722A - 具有选择性模制的用于镀覆的封装工艺 - Google Patents

具有选择性模制的用于镀覆的封装工艺 Download PDF

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CN113035722A
CN113035722A CN201911348978.6A CN201911348978A CN113035722A CN 113035722 A CN113035722 A CN 113035722A CN 201911348978 A CN201911348978 A CN 201911348978A CN 113035722 A CN113035722 A CN 113035722A
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Prior art keywords
lead
chip
leads
mold
envelope
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CN201911348978.6A
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金龙男
H·卡勒
刘俊锋
丁慧英
T·施密特
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Vishay General Semiconductor LLC
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Vishay General Semiconductor LLC
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Priority to CN201911348978.6A priority Critical patent/CN113035722A/zh
Priority to JP2021512447A priority patent/JP2023509241A/ja
Priority to PCT/US2020/017135 priority patent/WO2021133420A1/en
Priority to EP20848929.4A priority patent/EP3861568A4/en
Priority to US17/059,084 priority patent/US11393699B2/en
Priority to KR1020217003855A priority patent/KR20220121173A/ko
Priority to IL280216A priority patent/IL280216B2/en
Priority to TW109104059A priority patent/TW202126134A/zh
Publication of CN113035722A publication Critical patent/CN113035722A/zh
Priority to US17/842,414 priority patent/US11764075B2/en
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Abstract

公开了用于在引线半导体封装上形成可润湿侧面的技术和装置。引线框可以包括多个引线组，每个引线组包括具有芯片表面和镀覆表面的引线，位于第一方向上的相邻引线组之间的通孔，以及布置在每个芯片引线的芯片表面上的集成电路芯片。可以在镀覆表面上施加模制包封，该模制包封包括延伸到第一方向的每个相邻引线组之间的通孔中的模制包封延伸部，每个模制包封延伸部具有峰表面。引线框组件可以部分地嵌入在模制封套中，使得模制封套的一部分接触峰表面。模制包封可以被去除以暴露出镀覆表面和包括侧壁的通孔，并且侧壁可以被镀覆以电镀层。

Description

具有选择性模制的用于镀覆的封装工艺
背景技术
扁平的“没有引线”或“无引线”半导体芯片封装将集成电路芯片(或“小片”)电且物理耦合到印刷电路板(“PCB”)，该印刷电路板具有扁平引线且没有贯穿印刷电路板(PCB)的通孔。尽管这些半导体芯片封装被称为“没有引线”或“无引线”封装，但是本公开中的术语“引线”用于指代存在于扁平无引线封装上的扁平接触垫。这些半导体芯片封装在没有引线延伸超过或超出封装的外围的意义上没有“引线”。扁平无引线封装可分为四方扁平无引线(“QFN”)封装，在封装的所有四个侧面上都有引线；以及双扁平无引线(“DFN”)封装，在两个相反的侧面上有引线。在这些半导体芯片封装内，一个或多个集成电路芯片被封装在非导电模制材料内。通常由诸如铜之类的金属制成的导电引线框电耦合至半导体芯片封装的内部部件，并且在外部暴露出可以电耦合至PCB的引线。扁平无引线封装的改进正在不断进行。
无引线半导体芯片封装具有优于其中引线延伸超出封装周边的封装的多个优点。与其他类型的半导体芯片封装相比，这种半导体芯片封装可以具有低轮廓。与具有延伸超出半导体芯片封装的周边的引线的常规封装相比，这样的半导体芯片封装可以占用较小的空间，从而在印刷电路板上具有较小的“占地面积”。与引线延伸超出封装的周边的封装相比，这种无引线半导体芯片封装也可以具有更好的热性能。
与QFN和DFN封装有关的相关行业中的一个问题涉及到与封装引线之间的焊接连接的检查。为了确保至QFN和DFN封装的正确焊接连接，必须检查连接。这些检查可以通过例如X射线或自动光学检查(AOI)进行。自动化光学检查(AOI)系统用于检查例如半导体器件和印刷电路板(PCB)的缺陷。如果引线的定向方式使得引线的侧或“侧面”的一部分可被焊料润湿，例如焊料芯吸到裸露的引线的侧面或侧壁，则QFN和DFN封装可实现AOI，其成本比X射线检查便宜。
常规的引线可湿器件可以通过以下工艺形成：该工艺在镀覆一个或多个表面之前需要一个或多个切口以产生可湿性侧面。这样的切口可能需要额外的设备，或者可能需要更多的步骤来形成可润湿的侧面。
因此，需要一种有效的方法来制造具有可润湿侧面的半导体芯片封装。
发明内容
在本发明的一方面，公开了一种用于制造引线可润湿表面的方法。该方法可以包括提供引线框，所述引线框包括：多个引线组，每个引线组包括具有芯片表面和镀覆表面的芯片引线和键合引线；第一方向上的相邻引线组之间的通孔；以及布置在每个芯片引线的芯片表面上的集成电路芯片。该方法还可以包括将模制包封施加到每个芯片引线和键合引线的镀覆表面，模制包封接触多个引线组，模制包封包括延伸到第一方向上的每个相邻引线组之间的通孔中的模制包封延伸部。每个模制包封延伸部具有峰表面。该方法可以进一步包括将引线框组件部分地嵌入到模制封套中，使得模制封套的一部分接触每个模制包封延伸部的峰表面。该方法可以进一步包括去除模制包封以暴露通孔，每个通孔包括每个引线组的芯片引线的第一引线侧壁和每个引线组的键合引线的第二引线侧壁，并将芯片引线和键合引线每个以及将第一引线侧壁和第二引线侧壁镀覆以电镀层。
在本发明的一方面，公开了一种装置，其包括引线框，该引线框包括：多个引线组，每个引线组包括具有芯片表面和镀覆表面的芯片引线和键合引线；第一方向上的相邻引线之间的通孔；以及布置在每个芯片引线的芯片表面上的集成电路芯片。该装置还包括在芯片引线和键合引线每个的镀覆表面上的模制包封，该模制包封接触多个引线组，该模制包封包括延伸到在第一方向上的每个相邻引线组之间的通孔中的模制包封延伸部，每个模制包封延伸部具有峰表面；以及模制封套，该模制封套包括模制封套的与每个模制包封延伸部的峰表面接触的一部分。
附图说明
从以示例方式结合附图给出的以下描述中可以得到更详细的理解，其中：
图1是根据一个示例的用于由封装组件在半导体芯片封装上形成可润湿侧面的示例性方法的流程图；
图2A是封装组件的俯视图，示出了根据一个示例的具有引线、芯片和通孔的引线框；
图2B是根据一个示例的图2A的封装组件的剖视图；
图2C是根据一个示例的图2A的封装组件的仰视图；
图3是根据一个示例的具有模制包封和模制封套的封装组件的剖视图；
图4是根据一个示例的图3的封装组件的剖视图，其中模制包封被移除；
图5是根据一个示例的具有镀覆表面电镀层和侧壁电镀层的封装组件的剖视图；
图6是根据一个示例的具有连接膜的封装组件的剖视图；
图7A是根据一个示例的封装组件的俯视图，示出了在封装组件内形成通道的切口和切割图案；
图7B是根据一个示例的图7A的封装组件的剖视图；
图7C是根据一个示例的图7A的封装组件的仰视图；
图8是根据示例的具有底部和侧壁电镀层的完成的半导体芯片封装的截面图；
图9A是根据示例的具有底部和侧壁镀层的DFN封装的底侧的透视图；
图9B是根据一个示例的具有底部和侧壁镀层的图9A的DFN封装的顶侧的透视图；
图9C是根据示例的具有底部和侧壁镀层的QFN封装的底侧的透视图；以及
图9D是根据示例的具有底部和侧壁镀层的图9C的QFN封装的顶侧的透视图。
具体实施方式
在下面的描述中使用某些术语只是为了方便，而不是限制。单词“右”、“左”、“顶”和“底”表示在附图中所参考的方向。然而，要理解的是，这样的基于方位的术语仅用于参考，并且各实施例可以在不同的方向上实施，使得可以基于这样的各个不同方向来调整应用这些术语。除非另外特别说明，否则权利要求书和说明书的相应部分中使用的词语“一”和“一个”被定义为包括一个或多个所提及的项目。该术语包括上面具体提到的词、其派生词以及类似含义的词。短语“至少一个”后跟两个或多个项目的列表，例如“A，B或C”，是指A，B或C中的任何单独一个及其组合。
本文提供的描述是为了使本领域技术人员能够制造和使用所阐述的实施例。然而，各种修改、等同、变化、组合和替代对于本领域技术人员而言将仍是显然的。任何和所有这样的修改、变化、等同、组合和替代旨在落入由权利要求书限定的本发明的精神和范围内。
本文公开了用于在半导体芯片封装上(优选地在DFN和/或QFN半导体芯片封装上)形成底部和侧壁可润湿侧面的技术。该技术包括具有多个非切单的半导体芯片封装的封装组件。封装组件包括引线框，该引线框具有芯片和与其耦接的其他内部封装部件(例如，引线键合)。芯片和其他部件形成非切单的半导体芯片封装的不同区域，如本文进一步公开的。引线框在封装组件的一端与另一端之间以及在半导体芯片封装的各种裸露引线和芯片焊盘之间提供连续的电连接。诸如引线键合或拉杆的元件可以帮助形成电连接。该电连接可以用于电镀期间的电流流动，其可以是在DFN和/或QFN封装上形成底部和侧壁可润湿侧面的过程中发生的步骤。
图1示出了根据本发明的一方面的用于由封装组件形成半导体芯片封装的工艺100的流程图。图1的工艺100结合图2-9来讨论，图2-9示出了随着工艺100而进行的封装组件200的各阶段。如本文所引用的，引线框25可以由诸如铜片的引线框材料切割而成。如本文所引用的，引线框组件可以是具有多个带有第一引线22a和第二引线22b的引线组22的引线框25。引线框组件可以包括任何金属合金。可以将引线组22蚀刻到引线框25的一部分中。尽管公开了引线组22包括两个引线(即22a和22b)，但是应当理解，引线组可以包括多于一个的不同数量的引线(例如4条引线)。
如图2A-2C所示，封装组件200被示出具有顶表面201和底表面202。引线框25可以包括多个引线组22，每个引线组包括至少芯片引线22a和键合引线22b。引线框25可以在相邻的引线组22之间包括通孔23，如图2A-2C所示。通孔23可以对应于或以其他方式被称为间隔、孔、贯穿孔、间隙、空隙等。每个通孔23可以形成在键合引线22b的侧壁55和相邻引线组22的芯片引线22a的侧壁56之间。尽管在图2A至图2C中示出了沿X方向的相邻引线组22之间的通孔23，但要理解的是，通孔23可以在引线框25中沿任何可应用的方向(例如，Y方向)设置，并且图2-9中所示的示例不是限制性的。
在步骤10处，为简单起见，一个或多个集成电路芯片20(在本文中称为“芯片”)可以沉积在引线框25的引线组22的芯片引线22a上。引线框组件可包括集成到单个零件或单元中的多个引线组22。多个半导体芯片封装可以在封装组件200中以芯片封装阵列形成，其然后被切割(例如，切单)成单独的半导体芯片封装，如本文进一步公开的。每个半导体芯片封装可以包括：引线组22，其包括芯片引线22a和键合引线22b；芯片引线22a上的芯片20；芯片20经由将芯片20连接到键合引线22b的导线21而键合到键合引线22b。如图3所示，模制封套32也可以是如本文进一步公开的半导体芯片封装的一部分。单个的半导体芯片封装可以是与封装组件中一个或多个其他半导体芯片封装分离的半导体芯片封装，如本文进一步所述的。
在步骤11中，设置其他部件，例如导线21、导电夹(半导体芯片封装中的将芯片耦合到一个或多个引线的元件)或其他元件，以形成多个半导体芯片封装。值得注意的是，在步骤11中，多个芯片20中的每一个可以经由将芯片20连接到键合引线22b的导线21键合到每个对应的键合引线22b，如图2A和2B所示。
图2A示出了在图1的工艺100的步骤11之后具有顶表面201的封装组件200的俯视图。如图2A所示，提供多个引线组22作为引线框25的一部分。每个引线组22包括芯片引线22a和键合引线22b。在芯片表面27a(例如，如图2A和图2B所示的顶表面)上在每个芯片引线22a上沉积芯片20。如图2B所示，将芯片20沉积在引线组22的芯片引线22a上，并且将芯片20电连接至同一引线组22的键合引线22b。可以使用结合至沉积在引线组22的芯片引线22a的芯片表面27a上的给定芯片20的导线21来实施该电连接，给定的导线21连接到键合引线22b的芯片表面27a。
图2B示出了在图1的工艺100的步骤11之后图2A的封装组件200的剖视图。如图2B所示，提供多个引线组22作为引线框25的一部分，每个引线组包括芯片引线22a和键合引线22b。多个芯片20沉积在引线组22的芯片引线22a上。芯片20可以被电连接到相应引线组22的键合引线22b。芯片20到相应键合引线22b之间的电连接可以使用导线21进行，如参考图2a所公开的。
图2C示出了在图1的工艺100的步骤11之后图2A和2B的封装组件200的仰视图。如图2C所示，多个引线组22可以以阵列构造布置。图2C示出了引线组22的芯片引线22a和键合引线22b的镀覆表面27b(例如，底表面)。如图所示，在引线框25中在X方向上彼此相邻的引线组22之间提供了通孔23。尽管在图2C中通孔23被示出为在X方向上在相邻的引线组22之间，但是要理解的是，通孔23可以在引线框25中沿诸如Y方向的任何可应用方向设置，并且图2-8中所示的示例不是限制性的。如本文中进一步指出的，在Y方向上彼此相邻的引线组22(例如，图2C中的顶部和底部)可以在半导体封装的制造过程中彼此电独立，如本文所公开的。
在图1的工艺100的步骤12，且如图3所示，可以在封装组件200的底表面202上施加模制包封31的带。模制包封31可以包括模制包封延伸部31a，其延伸到引线组22之间的通孔23中，如本文进一步公开的。此外，可以在引线框25和半导体芯片封装的其他部件周围沉积模制封套32，并且模制封套32的一部分可以延伸直至并终止于模制包封延伸部31a的峰表面31b。值得注意的是，模制包封31可被施加到封装组件200的底部202。模制包封31可防止在步骤12处沉积的模制封套32延伸越过引线框25的底部并且模制封套件32的一部分可以延伸直至模制包封延伸部31a的峰表面31b并停在此处。
如图3所示，模制包封31可被施加到封装组件200的底表面202，并且可覆盖封装组件200的引线组22的芯片引线22a和键合引线22b的镀覆表面27b。模制包封31可以包括模制包封延伸部31a，该模制包封延伸部31a延伸到引线框25的通孔23中(如图2A-2C所示)。模制包封延伸部31a可以部分或全部延伸通过通孔23。如图3所示，模制包封延伸部31a可以从平行于引线组22的镀覆表面27b的第一平面延伸到每个模制包封延伸部31a的峰表面31b。每个模制包封延伸部31a的峰表面31b可以平行于每个引线组22的芯片引线22a和键合引线22b的芯片表面27a。模制包封延伸部31a与每个相邻引线组22的键合引线22b的侧壁55和芯片引线22a的侧壁56相邻并在它们之间。如图3所示，模制包封延伸部31a可以填充在侧壁55和56之间的整个空间中。值得注意的是，模制包封延伸部31a填充在侧壁55和56之间的整个表面，使得模制封套32不延伸到通孔23中，因此，不会覆盖侧壁55和56。
根据实施例，在将模制包封31施加到封装组件200的底表面201上之前，模制包封31可以被预成形为包括模制包封延伸部31a。模制包封31可以通过诸如光刻、蚀刻、退火等之类的任何适用工艺被成形为包括模制包封延伸部31a。根据该实施例，模制包封延伸部31a的位置可以与引线框25的通孔23预先对准。根据另一实施例，模制包封31可以施加到封装组件200的底表面201上，且模制包封延伸部31a可以被模制到通孔23中，使得它们延伸到通孔23中直至模制包封延伸部31a的峰表面31b，如图3所示。根据该实施例，用于模制包封31的材料可以是可延展的，使得在模制包封31位于封装组件200的底表面201上的同时压力和/或热量施加到模制包封31上时，模制包封31的材料延伸到通孔23中以形成模制包封延伸部31a。如图3所示，模制包封延伸部31a可被成形为凸出的凸部，其被形成为填充通孔23。
如图3所示，在图1的工艺100的步骤13处，可以将芯片20和其他部件(例如，导线21)封装在模制封套32内(也称为“模制”，“模”，“封装”，“封装材料”，“模制封套材料”或其他类似术语)。模制封套32可以是不导电的，并且可以覆盖所有或大部分封装部件，但是可以不覆盖每个引线组22的芯片引线22a和键合引线22b的镀覆表面27b，并且也可以不覆盖键合引线22b的侧壁55和芯片引线22a的侧壁56，因为被模制包封延伸部31a阻止了这样做。模制封套32可包括与每个引线组22的芯片引线22a和键合引线22b的底表面27b相反的顶部主表面32a。模制封套32可具有与每个引线组22的多个芯片引线22a和接合引线22b的底表面27(除了通孔23之外)相邻且基本平行的底部主表面32b。
模制封套32的部分在图3中示出，但也可以理解的是，从图3所示的截面图看，模制封套32可以覆盖引线框25和相关的部件(例如，芯片20和导线21)。在一个实施例中，模制封套32可以是部分或完全不透明的，并且可以具有给定的颜色(例如，黑色，灰色等)，使得引线框25和相关联的部件在俯视图中可能是不可见的。然而，将理解的是，在俯视图中，如图3所示，出于说明目的，模制封装32被示为透明的，使得引线框和相关联的部件在图2中可见。如图所示，模制封套32封装每个引线组22的芯片20，多个引线芯片引线22a和接合引线22b，并且可以设置在每个引线组22的芯片引线22a和接合引线22b之间的空间之间。
模制封套32可以为封装组件200的部件提供物理和电的屏障。模制封套32可以是二氧化硅填充的树脂、陶瓷、无卤化物的材料或其他保护性封装材料，或其组合。可以通过在一个工艺过程中模制热固性材料来形成模制封套32，在该工艺过程中，塑料在传输室中通过热量和压力而软化，然后在高压下通过合适的注口、流道和浇口被迫压入封闭的模具中以进行最终固化。模制封套32也可以通过使用液体来形成，该液体可以被加热以通过在UV或环境气氛中固化而形成固体；或者通过使用固体来形成，该固体被加热以形成液体然后冷却以形成固体模具。
根据一个实施例，如图3所示，在施加模制包封31之前，可以将膜30施加到每个芯片引线22a和键合引线22b的镀覆表面27b上，并且膜30可以延伸到通孔23中，从而覆盖侧壁55和56。膜30还可以在每个引线组22的芯片引线22a和键合引线22b之间的间隙之间延伸，如图3所示。根据该实施例，可以将模制包封31施加到膜30的与引线组22的芯片引线22a和键合引线22b的镀覆表面27b相反的表面上。因此，模制包封31可以覆盖镀层表面27b下方的膜30，并且模制包封延伸部31可以在通孔23内覆盖膜30。可替换地，可以在将模制包封31施加到封装组件200的底表面201上之前将膜30施加到预成形的模制包封31上。
在图1的工艺100的步骤13中，如图4所示，在步骤12之后，可以从引线框25去除膜30和/或模制包封31。可以在引线框组件200上施加一个或多个标记(未示出)。所述标记可以包括一个或多个基准标记，这些基准标记是可由机器检测到的标记，其允许机器将其自身对准以进行切割。在步骤13之后，提供封装组件200，该封装组件200包括多个非切单的半导体芯片封装，其封装部件(例如，芯片、引线框以及将芯片耦合到引线框的部件)被封装在模制材料32中。值得注意的是，如图4所示，每个引线组22的芯片引线22a和键合引线22b的镀覆表面27b可以暴露。此外，如图4所示，键合引线22b的侧壁55和芯片引线22a的侧壁56也可以暴露。
在图1的工艺100的步骤14处，每个引线组22的多个芯片引线22a和键合引线22b的镀覆表面27b以及键合引线22b的侧壁55和芯片引线22a的侧壁56可以分别镀覆有电镀层50和电镀层51，如图5所示。如本文所公开的，每个引线组22的多个芯片引线22a和键合引线22b的镀覆表面27b可以是与每个引线组22的多个芯片引线22a和键合引线22b的被结合到在步骤11中沉积的导线21的表面相反的表面。值得注意的是，镀覆表面27b和结合引线22b的侧壁55以及芯片引线22a的侧壁56的表面在去除膜30和/或模制包封31之后暴露。
电镀层50和电镀层51可以相同或可以包括两种不同的电镀材料。电镀层50和电镀层51可以同时或以两个不同的步骤施加。在图1的工艺100的步骤14，可以通过电镀过程来施加电镀层50和电镀层51，如图5所示。电镀层50和/或电镀层51可包括一层或多层金属，例如锡或锡合金，电镀在每个引线组22的多个芯片引线22a和键合引线22b的镀覆表面27b上(即，电镀层50)以及键合引线22b的侧壁55和芯片引线22a的侧壁56(即，电镀层51)，并且可以保护镀覆表面27b以及侧壁55和56免受氧化。此外，电镀层50和/或电镀层51可以提供用于焊接的可润湿表面。在电镀过程中施加电镀层50和/或电镀层51可以包括沉积导电电镀材料，该导电电镀材料覆盖镀覆表面27b(例如，底表面)和/或侧壁55和56，并且允许焊料粘附至每个引线组22的多个芯片引线22a和键合引线22b以及键合引线22b的侧壁55和芯片引线22a的侧壁56。电镀层50和/或电镀层51材料可以沉积在暴露的镀覆表面27b和侧壁55和56上。在步骤14的电镀过程中，可以将引线框25浸入浴中，并且可以将引线框25电耦合到电解电镀装置(未示出)的阴极。电解电镀装置的阳极可以与电镀材料耦合，电镀材料也浸入浴中。可以将电流施加到引线框，该电流使电镀材料沉积在每个引线组22的多个芯片引线22a和键合引线22b的镀覆表面27b以及键合引线22b的侧壁55和芯片引线22a的侧壁56上，使得例如每个引线组22的多个芯片引线22a和键合引线22b的镀覆表面27b以及键合引线22b的侧壁55和芯片引线22a的侧壁56被镀有电镀材料。电镀层50材料可以是多种电镀材料中的任何一种，例如锡、金、钯或银。
在图1的工艺100的步骤15中，可以将连接膜60施加到模制封套32的顶部主表面32a上，如图6所示。如图所示，连接膜60可以施加在多个引线组22上。连接膜60可以是附接到模制封套32的顶部主表面32a的任何适用的膜。连接膜60可以使用任何适用的粘合剂材料附接到模制封套32的顶部主表面上。
在图1的工艺100的步骤16处，如图7A-7C所示，可以应用切单工艺。如图7A至图7C所示，可以在步骤16之后将引线框25切单为单独的半导体芯片封装80。可以使用适用的切割装置和/或技术(例如具有锯条的锯，或激光切割机、等离子切割机或水射流切割机，或本领域技术人员已知的任何其他可接受的切割设备和/或技术)来实现步骤16的切单工艺。如本文进一步所述，在步骤16的切单过程可以包括制作一个或多个切口71(例如71a和/或71b)。切口71a可以在X方向上延伸(例如，如图7A和7C中所示从封装组件200的左侧到右侧)，并且从模制封套32的底部主表面32b开始并且向上延伸穿过模制封套32的顶部主表面32a。根据一个实施例，切口71a还可以切割穿过引线连接器28，如图7A所示。如本文中所应用的，引线连接器28可以连接两个相邻的引线，并且可以是引线框(例如，引线框25)本身的一部分，或者可以由一种或多种其他材料形成。切口71b可以在相邻的引线组22之间形成，并且可以在Y方向上延伸，并且可穿过通孔23制得，从模制封套32的与被去除的模制包封延伸部31a的峰表面31b相对应的底表面开始，并且可以延伸穿过模制封套32的顶部主表面32a以形成一个或多个通道70。通道70每个都可包括在通道70的每个部分的每一侧上镀有电镀层51的侧壁55和56。在步骤16的切单过程中，可以将封装组件200切单为仅通过连接膜60连接的单独的半导体芯片封装80。根据实施例，通道70的不对应于通孔23的部分小于通孔23(例如，通道70的壁的宽度小于侧壁55至侧壁56之间的距离)。
图7B示出了在图1的工艺100的步骤16中的图7A的包装组件200的剖视图。图7B示出了沿Y方向制成的一系列平行切口71b，以形成多个通道70。值得注意的是，沿Y方向的一系列平行切口71b始于通孔23，并延伸通过模制封套32。图7B示出了部分地延伸到连接膜60中的通道70，但是应当理解，根据一个实施例，通道70可以形成直到但不穿过连接膜70的一部分。如图7B所示，连接膜60的至少一部分跨过多个引线组22在模制封套32的主峰表面32a之上连续。
如在图7C的底视图中所示，在步骤16处的切单处理可以包括沿着第一方向(例如，X方向)切割穿过模制封套32的底部主表面32b作出第一系列的平行切口71a。第一系列的平行切口可以延伸直至连接膜60或连接膜60的一部分的深度。值得注意的是，该第一系列的平行切口71a仅穿过引线连接器28和/或未电连接的相邻引线组22(例如，如果从俯视图(如图7A所示)或从仰视图(如图7C所示)观看封装组件200时彼此上下布置的引线)之间的区域，并且不切穿引线组22。步骤16处的切单还可包括沿着第二方向(例如，Y方向)形成第二系列的平行切口71b，第二方向基本垂直于第一方向。第二系列的平行切口71b可以从通孔23开始，并且具体地从模制封套32的与被去除的模制包封延伸部31a的峰表面31b相对应的底表面开始，并且可以延伸穿过模制封套32的顶部主表面32a达到直至连接膜60或连接膜60的一部分以形成通道70的深度。
可以将第一系列的平行切口71a和第二系列的第二切口71b制成直至不完全延伸穿过连接膜60的深度，以允许半导体芯片封装80在步骤16的切单期间保持为单个封装件组件200。要注意的是，连接膜60可以具有这样的特性(例如，强度、刚性、弹性等)：其使连接膜60能够保持封住装组件200的多个半导体芯片封装80(它们通过通道70分隔开)，以作为由连接膜60连接的单个单元的一部分保留。例如，连接膜60可以使封装组件200的半导体芯片封装80加上多个通道70具有的在X方向上的宽度基本上等于在步骤16切单之前的封装组件200的宽度(例如，如图6所示，在步骤16之前的封装组件200的宽度)。连接膜60可以由可以导电或可以不导电的任何适用材料制成。
替代地，根据一个实施例，在步骤16中，代替用连接带60来带封住封装组件200的顶表面201的是，可以将连接带60施加到封装组件200的底表面202(未示出)。例如，在步骤16的切单过程可以包括在将连接带60施加到底表面的同时，从模制封套32的顶部主表面32a形成一个或多个切口71(例如71a和/或71b)。根据该实施例，切口71a可以在X方向上延伸，并且从模制封套32的顶部主表面32a开始，并且向下延伸穿过模制封套至模制封套32的底部主表面32b。根据一个实施例，切口71a还可以切穿引线框25的一部分(例如，如果引线连接器28是引线框25的一部分)。切口71b可以在相邻的引线组22之间形成，并且可以在Y方向上延伸，并且穿过通孔23形成，从模制封套32的顶部主表面32a开始，并且向下延伸穿过模制封套32到达模制封套32的对应于已移除的模制包封延伸部31a的峰表面31b的底表面，以创建一个或多个通道70。通道70的每一个在通道70的每个部分的每一侧可包括镀有电镀层51的侧壁55和56。根据实施例，通道70的不对应于通孔23的部分小于通孔23(例如，通道70的壁的宽度小于侧壁55至侧壁56之间的距离)。
在图1的工艺100的步骤17中，如图8所示，去除连接膜60。如图所示，在步骤17去除连接膜60之后，仅剩下封装组件200的多个半导体芯片封装80。多个半导体芯片封装件80中的每个包括：具有芯片引线22a和键合引线22b的引线组22；与每个引线组22的每个芯片引线22a接合的芯片20；将芯片20电连接到每个引线组22的相应键合引线22b的导线21。另外，多个半导体芯片封装80中的每一个都包括在芯片引线22a和键合引线22b的镀覆表面27b上的电镀材料(例如，电镀材料50)，以及在每个引线组22的引线侧壁55和56上的电镀材料(例如电镀材料51)。电镀材料(例如50和/或51)可用于将给定的半导体芯片封装安装到印刷电路板(PCB)。
尽管在此示出和/或描述了引线组中的引线的特定数量和配置(例如，引线组22中的芯片引线22a和键合引线22b)，但是本公开的技术可应用于具有任何引线和/或芯片配置的组件封装。另外，本领域技术人员可以理解，可以使用相同或相似的技术来提供具有可润湿侧面的QFN封装，作为具有可润湿侧面的DFN封装。
图9A和9B示出了具有可润湿侧面250的DFN封装，在两个相应的引线(未示出)的底部上具有第一电镀材料50，并且在DFN封装250的引线侧壁(未示出)上具有第二电镀层51。第一电镀材料50和第二电镀材料51可以根据图1的工艺100进行电镀，如本文所公开。另外，如图9A所示，拉杆区域35也可以被镀覆(例如，具有第二电镀层51)。如本文所公开的，拉杆区域35可有助于形成用于电镀期间(例如，在第一电镀层50和/或第二电镀层51期间)的电流流动的电连接。
图9C和9D示出了QFN封装260，该QFN封装260在相应的引线(未示出)的底部上具有第一电镀材料50，并且在QFN封装260的引线侧壁(未示出)上具有第二电镀材料51。可以根据图1的工艺100来电镀第一电镀材料50和第二电镀材料51，如本文所公开。
值得注意的是，如本文所述，图1的工艺100可以被执行，以提供一种电镀工艺，以形成具有可润湿侧面的半导体芯片封装。工艺100通过在模制封套的过程中使用具有模制包封延伸部的模制包封来隔离通孔，然后在去除模制包封之后暴露出引线的侧壁和镀覆表面，从而在切单之前进行电镀。在单片化之前进行电镀可以简化电镀过程，并且可以降低单片化之后进行电镀的复杂性。
应当理解，前述内容仅以示例的方式而不是任何限制的方式给出。可以预期的是，在不脱离本发明的精神和范围的情况下，可以对所描述的实施例进行各种替换和修改。如此详细地描述了本发明，对于本领域的技术人员来说将理解和显而易见的是，在不改变本文实施的发明概念和原理的前提下，可以进行许多物理改变(在本发明的详细描述中仅例示了其中的一些)。还应当理解，仅结合优选实施例的一部分的许多实施例是可能的，相对于那些部分，这些实施例不会改变本文实施的发明构思和原理。因此，本实施例和可选配置在所有方面都应被认为是示例性和/或说明性的，而不是限制性的，本发明的范围由所附权利要求书而不是前述说明来指示，并且落入所述权利要求的等同含义和范围内的此实施例的所有替代实施例及其变化均包涵于其中。

Claims (20)

1.一种制造引线可润湿表面的方法，该方法包括：
提供引线框，所述引线框包括：多个引线组，每个引线组包括具有芯片表面和镀覆表面的芯片引线和键合引线；位于第一方向上相邻引线组之间的通孔；以及布置在每个芯片引线的芯片表面上的集成电路芯片；
将模制包封施加到芯片引线和键合引线的每个的镀覆表面上，所述模制包封接触所述多个引线组，该模制包封包括延伸到第一方向上的每个相邻引线组之间的通孔中的模制包封延伸部，每个模制包封延伸部具有峰表面；
将引线框组件部分地嵌入到模制封套中，使得模制封套的一部分接触每个模制包封延伸部的峰表面；
去除模制包封以暴露出通孔，每个通孔包括每个引线组的芯片引线的第一引线侧壁和每个引线组的键合引线的第二引线侧壁；和
将芯片引线和键合引线每个的镀覆表面以及将第一引线侧壁和第二引线侧壁镀覆以电镀层。
2.根据权利要求1所述的方法，还包括：
施加连接膜到模制封套的顶部主表面；
将引线框组件切单为独立的半导体芯片封装，该切单包括：
沿实质上垂直于第一方向的第二方向，从通孔并穿过模制封套的顶部主表面到直至连接膜或连接膜的一部分的深度，形成第一系列的平行切口；
沿着第一方向，穿过模制封套的与连接膜相反的表面，到直至到达连接膜或连接膜的一部分的深度，形成第二系列的平行切口；和去除连接膜。
3.根据权利要求1所述的方法，还包括：
施加连接膜至模制封套的底部主表面；
将引线框组件切单为独立的半导体芯片封装，该切单包括：
沿着实质上垂直于第一方向的第二方向，从模制封套的顶部主表面到通孔，形成第一系列的平行切口；
沿第一方向从模制封套的顶部主表面，到下达连接膜或连接膜的一部分的深度，形成第二系列的平行切口；和
去除连接膜。
4.根据权利要求1所述的方法，其中，所述模制包封延伸部从与芯片引线和键合引线的镀覆表面平行的第一平面延伸到每个模制包封延伸部的峰表面，使得每个模制包封延伸部的峰表面平行于每个引线组中的芯片引线和键合引线的芯片表面。
5.根据权利要求1所述的方法，其中，所述模制包封的一部分跨过所述多个引线组是相继的。
6.根据权利要求1所述的方法，其中，每个引线组中的芯片引线和键合引线通过导线电连接。
7.根据权利要求1所述的方法，其中，所述电镀层包括锡材料和锡合金材料中的至少一种。
8.根据权利要求1所述的方法，其中，所述镀覆包括：
在每个引线组的芯片引线和键合引线的镀覆表面以及第一引线侧壁和第二引线侧壁上提供镀覆材料溶液，
将电源电耦合到引线框和镀覆材料溶液，以及
通过电源将电流施加到引线框。
9.根据权利要求1所述的方法，其特征在于，所述模制包封延伸部被成形为凸形的凸起。
10.如权利要求1所述的方法，其中，所述模制包封延伸部使用光刻、蚀刻和退火中的一种或多种形成。
11.一种设备，包括：
引线框，其包括：多个引线组，每个引线组包括具有芯片表面和镀覆表面的芯片引线和键合引线；第一方向上的相邻引线组之间的通孔；以及设置在每个芯片引线的芯片表面上的集成电路芯片；
沿着芯片引线和键合引线每个的镀覆表面定位的模制包封，该模制包封接触所述多个引线组，该模制包封包括延伸到第一方向上的每个相邻引线组之间的通孔中的模制包封延伸部，每个模制包封延伸部具有峰表面；和
模制封套，包括模制封套的与每个模制包封延伸部的峰表面接触的部分。
12.根据权利要求11所述的装置，其中，所述模制包封延伸部从与芯片引线和键合引线的镀覆表面平行的第一平面延伸至每个模制包封延伸部的峰表面，使得每个模制包封延伸部的峰表面平行于每个引线组中的芯片引线和键合引线的芯片表面。
13.根据权利要求11所述的装置，其中，所述模制包封延伸部从与芯片引线和键合引线的镀覆表面平行的第一平面延伸到每个模制包封延伸部的峰表面，使得每个模制包封延伸部的峰表面位于第一平面和与每个引线组中的芯片引线和键合引线的芯片表面平行的第二平面之间。
14.根据权利要求11所述的装置，其进一步包括在模制包封与芯片引线和键合引线每个的镀覆表面之间的膜。
15.如权利要求12所述的装置，其特征在于，所述膜还位于每个模制包封延伸部的峰表面与模制封套的一部分之间。
16.根据权利要求11所述的装置，其中，所述模制包封的一部分跨过所述多个引线组是相继的。
17.根据权利要求11所述的装置，其中，每个引线组中的芯片引线和键合引线通过导线电连接。
18.根据权利要求11所述的装置，其中，所述模制包封延伸部被成形为凸形的凸起。
19.根据权利要求11所述的装置，其中，所述模制封套是不导电的。
20.根据权利要求11所述的装置，其中，所述模制封套占据每个引线组的芯片引线和键合引线之间的空间。
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