TWI833739B - 半導體封裝及製造其之方法 - Google Patents
半導體封裝及製造其之方法 Download PDFInfo
- Publication number
- TWI833739B TWI833739B TW108111152A TW108111152A TWI833739B TW I833739 B TWI833739 B TW I833739B TW 108111152 A TW108111152 A TW 108111152A TW 108111152 A TW108111152 A TW 108111152A TW I833739 B TWI833739 B TW I833739B
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- Taiwan
- Prior art keywords
- die
- leads
- plated
- strips
- package
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000007747 plating Methods 0.000 claims abstract description 37
- 238000009713 electroplating Methods 0.000 claims abstract description 24
- 238000005538 encapsulation Methods 0.000 claims abstract description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 5
- 238000010168 coupling process Methods 0.000 claims description 5
- 238000005859 coupling reaction Methods 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 239000002775 capsule Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 4
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 239000008188 pellet Substances 0.000 claims 1
- 238000005520 cutting process Methods 0.000 abstract description 17
- 230000009977 dual effect Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 19
- WABPQHHGFIMREM-RNFDNDRNSA-N lead-211 Chemical compound [211Pb] WABPQHHGFIMREM-RNFDNDRNSA-N 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000007689 inspection Methods 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000006467 substitution reaction Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000008187 granular material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000012778 molding material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/4814—Conductive parts
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- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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Abstract
用於形成一雙側扁平無引線的半導體封裝的技術係在此加以揭示。該技術係開始於一封裝組件,該封裝組件包含多個未單粒化的封裝。該半導體封裝組件包含一具有耦接至其的晶粒的引線架組件。一模製囊封覆蓋該些晶粒的至少部分,並且露出複數個引線。一第一切割步驟係露出該引線架的引線的側壁。一電鍍步驟係在該些露出的引線上沉積一鍍覆。一第二切割步驟係與該些階梯式切割側壁對準地切割穿過該模製囊封。一垂直於該些階梯式切割的第三切割步驟係穿過該引線架以及模製囊封來加以做成,以單粒化該些晶粒成為個別的封裝。
Description
本申請案係有關於具有側壁鍍覆的半導體封裝。
相關申請案之交互參照
此申請案係主張2019年3月8日申請的美國申請案號PCT/US2019/021272的益處,該美國申請案的內容係被納入在此作為參考。
扁平“無引線的”或是“沒有引線的”半導體封裝係利用扁平的引線而且在無通孔延伸穿過印刷電路板(PCB)之下,將積體電路晶粒電性且實體耦接至印刷電路板(“PCB”)。注意到的是,儘管這些封裝被稱為“無引線的”或是“沒有引線的”封裝,但是在本揭露內容中的術語“引線”係被用來指存在於扁平無引線的封裝上的扁平的接觸墊。這些封裝沒有“引線”的意思是沒有延伸超出或超過該封裝的外部周邊的引線。扁平無引線的封裝可被分類為四邊扁平無引線的(“QFN”)封裝,其係在該封裝的所有四個側邊上具有引線、以及雙邊扁平無引線的(“DFN”)封裝,其係在兩個相對的側邊上具有引線。在這些封裝之內,一或多個積體電路晶粒係被囊封在一種非導電的模製材料之內。一通常由一種像是銅的金屬所做成的導電的引線架係電耦接至該封裝的內部的構件(例如是晶粒),並且從外部露出可以電耦接至一PCB的引線。對於扁平無引線的封裝
係不斷地做成改良。
沒有引線的封裝係具有數個優點優於具有延伸超過該封裝的一周邊的引線的封裝。相較於其它類型的封裝,此種封裝可以具有一低的輪廓。相較於習知的具有延伸超過封裝的周邊的引線的封裝,此種封裝可以佔用較少空間,並且藉此在一印刷電路板上具有一較小的“覆蓋區”。相較於具有延伸超過封裝的周邊的引線的封裝,此種沒有引線的封裝亦可以具有更佳的熱效能。
在關於QFN及DFN半導體封裝的相關的產業中之一問題係有關於焊料連接至該些封裝的引線的檢查。為了確保正確的焊料連接至QFN及DFN半導體封裝,檢查該些連接是必要的。這些檢查例如可以藉由X射線、或是藉由自動化的光學檢查(AOI)來加以執行。自動化的光學檢查(AOI)系統例如是被用來檢查半導體裝置以及印刷電路板(PCB)是否有缺陷。若該些引線係以引線的側邊或“側面(flank)”的部分是可藉由焊料潤濕的,例如藉由使得焊料吸附露出的引線的側邊或側壁的此種方式來加以定向,則QFN及DFN半導體封裝可以容許利用比X射線檢查較不昂貴的AOI。
因此,需要有一種有效率的製造一DFN半導體封裝的方法,其係提供可潤濕的側面,藉此容許AOI能夠確認正確的焊料連接。
在本發明的一特點中,一種用於製造具有階梯式切割的可潤濕的側面的半導體封裝的方法係被提出。該方法係包含進行穿過一封裝組件的鍍覆條並且部分穿過該封裝組件的一模製囊封的一第一系列的平行的切割,其中該封裝組件係包含複數個被組織成列的晶粒封裝,每一個晶粒封裝係具有被囊封在該模製囊封中的一積體電路晶粒以及複數個引線,其中該些晶粒封裝係經由該些鍍覆條而被電耦接在一起,並且其中在每一個晶粒封裝之內,一晶粒承
座係經由聯結(tie)接合以及引線接合的一或兩者來電耦接至相對的鍍覆條。該方法亦包含電鍍該些引線的露出表面。該方法進一步包含進行與該第一系列的平行的切割對準的完全穿過該模製囊封的一第二系列的平行的切割,藉此形成階梯式切割的可潤濕的側面。該方法亦包含進行垂直於該第一系列的平行的切割以及該第二系列的平行的切割的一第三系列的平行的切割,該第三系列的平行的切割係完全穿過該模製囊封以及該引線架來加以做成的。
在本發明的另一特點中,透過一種用於製造具有階梯式切割的可潤濕的側面的半導體封裝的方法所製造的一種雙側扁平無引線(DFN)的半導體封裝係被提出。該方法係包含進行穿過一封裝組件的鍍覆條並且部分穿過該封裝組件的一模製囊封的一第一系列的平行的切割,其中該封裝組件係包含複數個被組織成列的晶粒封裝,每一個晶粒封裝係具有被囊封在該模製囊封中的一積體電路晶粒以及複數個引線,其中該些晶粒封裝係經由該些鍍覆條而被電耦接在一起,並且其中在每一個晶粒封裝之內,一晶粒承座係經由聯結接合以及引線接合的一或兩者來電耦接至相對的鍍覆條。該方法進一步包含電鍍該些引線的露出表面。該方法亦包含進行與該第一系列的平行的切割對準的完全穿過該模製囊封的一第二系列的平行的切割,藉此形成階梯式切割的可潤濕的側面。該方法進一步包含進行垂直於該第一系列的平行的切割以及該第二系列的平行的切割的一第三系列的平行的切割,該第三系列的平行的切割係完全穿過該模製囊封以及該引線架來加以做成的。
在本發明的另一特點中,一種雙側扁平無引線(DFN)的半導體封裝係被提出。該DFN半導體封裝係包含一模製囊封。該DFN半導體封裝亦包含一至少部分被設置在該模製囊封之內的引線架,其中該引線架係具有一被設置在該引線架的一晶粒承座上的積體電路晶粒,該引線架亦使得一聯結條或是一引線接合中之一從該晶粒承座延伸至該模製囊封的一邊緣。該DFN半導體封
裝亦包含在該封裝的相對的側邊上的一對相對的階梯式切割的可潤濕的側面,其係露出該引線架的引線的側壁以被電解鍍覆。該些電解鍍覆的側壁係被配置以接收焊料,以用於例如附接至一印刷電路板(PCB)。
100:方法
102:步驟
104:步驟
106:步驟
150:方法
152:步驟
154:步驟
156:步驟
158:步驟
200:封裝組件
202:模製囊封材料
203:鍍覆條
204:封裝邊緣引線
205:引線架組件
206:晶粒承座
207:可潤濕的引線側邊
209:非可潤濕側邊
210:封裝
211:源極引線
213:閘極引線
215:聯結條
217:聯結條
219:聯結條
220:側壁
301:切割器
310:鍍覆材料
312:階梯式切割的可潤濕的側面
402:晶粒
404:引線接合
500:電鍍裝置
502:溶液
504:電源
506:鍍覆材料
508:鍍覆材料
更詳細的理解可以從以下結合所附的圖式所舉例的說明而獲得,其中:圖1A是根據一例子的一種用於形成一封裝組件的舉例說明的方法的流程圖;圖1B是根據一例子的一種用於形成一DFN半導體封裝的舉例說明的方法的流程圖;圖2A係描繪根據一例子的對於一封裝組件所做的一第一組的切割;圖2B係描繪根據一例子的電鍍被施加至該封裝組件的可潤濕的側面;圖2C係描繪根據一例子的與該些階梯式切割的可潤濕的側面對準,完全穿過該模製物所做成的一第二組的切割;圖2D係描繪根據一例子的垂直於該第一及第二組的第三組切割,以單粒化該些晶粒;圖2E係描繪根據一例子的具有可潤濕的側面的單粒化的晶粒;圖3A係描繪根據一例子的圖2A的第一系列的切割的橫截面圖;圖3B係描繪根據一例子的圖2C的第二系列的切割的橫截面圖;圖4A係描繪根據一例子的一具有可潤濕的側面的單粒化的晶粒的一頂端正投影視圖;圖4B係描繪根據一例子的一具有可潤濕的側面的單粒化的晶粒的一透視的頂端正投影視圖;
圖4C係描繪根據一例子的一具有可潤濕的側面的單粒化的晶粒的一底部正投影視圖;圖4D係描繪根據一例子的一具有可潤濕的側面的單粒化的晶粒的一透視的底部正投影視圖;以及圖5係描繪根據一例子的一電解鍍覆技術。
某些術語係在以下的說明中只是為了便利而被使用,因而並非限制性的。該些字詞"右"、"左"、"頂端"及"底部"係指明在所參照到的圖式中的方向。除非另有明確地相反的陳述,否則如同用在申請專利範圍以及在說明書的對應的部分中的字詞"一"及"一個"係被定義為包含所參照到的項目中的一或多個。此術語係包含在以上明確提及的字詞、其之衍生詞、以及具有類似意義的字詞。該措辭"至少一個"接著是例如"A、B或C"的一表列的兩個或多個項目係表示A、B或C的任一個別者、以及其之任意組合。
在此提出的說明是欲使得熟習此項技術者能夠完成及利用所闡述的實施例。然而,各種的修改、等同、變化、組合、以及替換對於熟習此項技術者而言都仍然會是相當明顯的。任何及所有的此種修改、變化、等同、組合、以及替換都欲落在藉由申請專利範圍所界定的本發明的精神與範疇之內。
在此係揭示用於在DFN半導體封裝上形成可潤濕的側面的技術。該技術係開始於一封裝組件,該封裝組件係包含多個未單粒化的封裝。該封裝組件係包含一引線架組件,其係具有耦接至其的晶粒以及其它的內部封裝構件(例如,引線接合)。該些晶粒以及其它構件係形成未單粒化的封裝的不同的區域。該些晶粒以及其它構件係被囊封在一種非導電的模製囊封材料之內(亦被稱為一“模製物”、“模塑”、“封裝”、“封裝材料”、或是在此的其它類似的術
語),其係覆蓋大多數的封裝構件,但是可以保留露出某些電性接觸墊(在此被稱為“引線”)以及可能的熱接觸墊(在此被稱為“晶粒承座”)。該引線架係提供在該封裝組件的一端與另一端之間、以及在該些封裝的各種露出的引線與晶粒承座之間的一連續的電連接。例如是引線接合或聯結條的元件可以協助形成該電連接。此電連接係被用來容許在電鍍期間的電流流動。在界定不同的封裝晶粒的區域的邊界處是鍍覆條,其係該引線架組件的部分,在該些晶粒封裝被單粒化之前電性連結該些不同的晶粒封裝。
舉例而言,一例如是鋸、水刀切割裝置,雷射切割裝置、或是一電漿切割裝置的切割裝置係穿過該引線架並且部分地到一深度,但是未完全穿過該模製物來進行階梯式切割,以露出該些引線的某些側壁。接著,這些露出的側壁的至少部分係被電解鍍覆。此外,該些引線的底表面係被電解鍍覆,並且某些露出的晶粒承座或接觸墊的底表面可以被電解鍍覆。在每一個晶粒封裝之內,一晶粒承座係經由聯結條或引線接合來耦接至右邊及左邊的鍍覆條,以容許用於電解鍍覆的電流流動。接著,一切割裝置係在和該些第一切割相同的方向及位置上進行完全穿過該模製物的切割,以分開該些列的晶粒封裝。一垂直於該第一及第二組的切割的第三組切割係加以進行,以單粒化該些晶粒。藉由該第三組切割露出的邊緣並未被鍍覆。因此,一完成的半導體封裝可被形成為一DFN半導體封裝。
圖1A是根據本發明之一特點的一種用於形成一封裝組件的舉例說明的方法100的流程圖。該方法100係開始在步驟102,其中一或多個晶粒係被置放到一引線架組件之上。該引線架組件係包含被整合成為單一部件或單元的多個封裝引線架。該引線架組件可包含一或多個基準標記,該基準標記是可藉由一機器偵測的標記,其係容許該機器本身能夠對準以用於切割。該引線架組件可以是任何的金屬合金。晶粒封裝通常是以一陣列的晶粒封裝來加以形成
的,其係接著被切割(“單粒化”)成為個別的晶粒封裝。為了形成此陣列,單一引線架組件係從例如是一片銅的一種引線架材料來加以切割的。該引線架組件係具有被整合於其中的多個對應於個別的封裝的引線架。在步驟102,該些積體電路晶粒中的一或多個係被置放在該引線架組件上。在步驟104,其它例如是引線接合的構件、導電夾片(在該封裝之內耦接晶粒至一或多個引線的元件)、或是其它的元件係被置放以形成封裝。在步驟106,一模製囊封係被沉積在該些封裝的引線架以及其它的構件的周圍。該模製囊封係提供一物理及電性屏障給該封裝的構件。在方法100的結束處是一包含多個未單粒化的封裝晶粒的封裝組件,其中封裝構件(例如,晶粒、該引線架、以及耦接該晶粒至該引線架的構件)係被囊封在一模製材料之內。
圖1B是根據本發明之一特點的一種用於形成一DFN半導體封裝的舉例說明的方法100的流程圖。圖1B的方法150係結合圖2A-2E來加以論述,圖2A-2E係描繪一封裝組件200隨著該方法150的進行的階段。該方法150開始於一封裝組件200(被展示在圖2A中),其係包含一引線架組件205,該引線架組件205係具有一被設置在其上並且附接至其的積體電路晶粒。該晶粒係藉由一封裝材料202(至少部分地)加以圍繞。該連續的引線架組件205係包含複數個鍍覆條203、晶粒承座206(或是“墊”)、以及封裝邊緣引線204,其在圖2A中係完全電耦接在一起。該些引線204係由一種導電材料所形成的,並且被配置以接受鍍覆(在此更詳細地加以敘述),以便於作用為可焊接的接點以供該封裝連接至一印刷電路板。非導電的模製囊封材料202係圍繞該引線架組件205。該些封裝是雙側扁平無引線的(“DFN”)封裝,因為該些封裝係具有兩個包含複數個用於外部的電耦接的引線204的相對的可潤濕的引線側邊207、以及兩個並不包含引線的相對的非可潤濕側邊209。
該封裝組件200係包含一陣列的未切割的(或是“接合的”或“未單
粒化的”)封裝210。該些封裝係包含例如是積體電路晶粒的電路元件、例如是引線接合的導電的元件、以及其它未顯示在圖2A-2E中的元件,因為這些圖只有展示該封裝組件200的底表面(其中例外的是該些聯結條215、217及219係因為這些元件是在該模製囊封202的內部,所以並未在該封裝的底表面上露出,但是其係為了清楚起見而被展示在圖2A-2E中)。更明確地說,應瞭解的是在所描繪的封裝組件200中,該模製囊封202係已經沉積在該引線架204以及其它構件的周圍,並且因此所看見的是該模製囊封202以及該引線架205穿過該模製囊封202而被露出的部分。所展示並且在此說明書中所述的特定封裝配置是一例子,因而此配置的細節不應該被視為限制性的。例如,每一個封裝210係被展示有一晶粒承座206、一閘極引線213、以及一源極引線211。因此,在該些封裝210中,一熱耦接至該晶粒承座206的晶粒係電耦接至引線204,並且經由在該封裝210的例如是引線接合的內部的導電元件來電耦接至該閘極引線213以及該源極引線211。儘管一特定數目及配置的引線204係被展示,但本揭露內容的技術係可應用於具有任意配置的引線204及/或晶粒承座206的封裝210。譬如,在某些封裝中,一閘極引線及/或源極引線可以是不存在的。引線可以用任意的配置存在。此外,任意數目的晶粒都可以存在於該些封裝之內,其係分別以不同的配置來連接至引線。
該些鍍覆條203是該引線架組件205的部分,其最終並不構成在該些晶粒封裝210被單粒化之後的個別的晶粒封裝210的引線架。換言之,該些鍍覆條203係提供橫跨該些晶粒封裝210的結構完整性及導電性以用於電鍍。
在步驟152,一切割裝置係執行完全穿過該引線架205並且部分穿過該模製囊封202的一第一階梯式切割。此切割係相鄰該些封裝210的可潤濕的引線側邊207來做成的,以便於露出該些引線204的側壁以用於電鍍。該切割裝置例如可以是一具有一實體刀片的鋸、一雷射切割器、一電漿切割器、或是
一水刀切割器、或是任何其它如同對於具有此項技術中的技能者而言為已知可接受的切割技術。該些切割在此可以被稱為一第一系列的平行的切割。該切割係被描繪在圖2A中。所用的刀片(或是其它切割元件)的寬度係足以切割兩個相鄰的晶粒封裝210的引線204的邊緣。再者,該切割係被做成完全穿過該引線架205(明確地說,穿過該些水平的鍍覆條203),但是並不完全穿過對應的模製囊封,此係容許該封裝組件200能夠以單一整合或連結的單元來加以處理通過後續的步驟。在步驟152的切割係在該些引線204的部分形成側壁220。
在步驟154,一電解鍍覆製程係被執行,其係利用一電解鍍覆裝置以便於鍍覆該引線架組件205。引線架通常是由一種例如是銅的材料所做成的。一層例如是錫或一錫合金的一種金屬係被鍍覆在該銅的表面上,以保護免於氧化,並且提供一可潤濕的表面以用於焊接。在一典型的電解鍍覆配置中,該引線架係被浸在一錫溶液中,並且該引線架係電耦接至一電解鍍覆裝置的陰極。該陽極係耦接至該鍍覆材料,其亦被浸在該溶液中。一電流係被施加至該引線架,其係使得該鍍覆材料沉積在該引線架的表面上,因而該些引線204以及晶粒承座206係被鍍覆該鍍覆材料。在用於在此所述的技術的電解鍍覆技術中,一種除了錫以外的鍍覆材料可被使用,例如是金、鈀、或是銀。在步驟152所做成的切割係露出該些引線204的可潤濕的側壁220,因而鍍覆該些引線204一種鍍覆材料。在步驟152中所做成的切割係電性斷開該些列的引線架的耦接,但是在每一個列之內,有如同在該圖中的朝向的從左到右的電性連續性。更明確地說,在每一個封裝210中,電流係從一左鍍覆條203,通過待被鍍覆的封裝210的每一個元件來流向一右鍍覆條203,並且接著透過該共用的鍍覆條203來流過下一個封裝210。在每一個封裝210中待被鍍覆的每一個別的元件係因此電耦接至該左及右鍍覆條203。明確地說,該晶粒承座206係透過一聯結條215來耦接至一左鍍覆條203。一聯結條是該引線架的一部分,其係提供在該晶
粒封裝210中的元件與鍍覆條203或是在該晶粒封裝210外部的其它元件之間的導電性及/或結構的連續性。在某些例子中,聯結條一般是比其它是該引線架205的部分並且從該晶粒封裝210延伸出的導電的元件薄的,並且聯結條通常並不延伸至該晶粒封裝210的底表面。該晶粒承座206亦電耦接至數個引線204。該晶粒承座206係透過一聯結條217來進一步耦接至該右鍍覆條203。該源極引線211以及該閘極引線213都是透過聯結條219來耦接至該右鍍覆條203。為了電耦接該晶粒承座206、該閘極引線213、或是該源極引線211的任一個至該右鍍覆條203之目的,該些源極及閘極引線的聯結條219、以及耦接該晶粒承座206至該右鍍覆條203的聯結條217的任一個都可以被例如是引線接合的其它導電的元件所取代。一引線接合係與一聯結條不同在於一引線接合並不是該引線架的一部分,而是被沉積或耦接在該引線架或構件的部分之間(例如是在一晶粒承座與一引線之間),以提供一電連接。
在步驟156,一切割裝置係進行與該第一組的平行的切割對準的一第二組的平行的切割。如同在圖2C中所示,該第二組的平行的切割的寬度係小於在步驟152所做成的第一組的切割的寬度。這些切割係形成該些晶粒的階梯式切割可潤濕的側面,並且完全地分開用於不同列的模製囊封。該些階梯式切割可潤濕的側面是階梯式切割的側邊,其係露出該些引線的側壁以用於焊料的施加,因而它們可以例如經由AOI來加以檢查。該些階梯式切割的兩個寬度係在圖2C中被展示為寬度1(W1)以及寬度2(W2),其中W1是大於W2。
在步驟158,一切割裝置係進行垂直於該第一及第二組的平行的切割的一第三組平行的切割。該第三組平行的切割係被對準以切割穿過該些鍍覆條203,以便於單粒化該些晶粒210。該第三組平行的切割係被做成足夠深的,以完全地切割穿過該引線架205以及該模製囊封202。圖2E係描繪具有可潤濕的側面的單粒化的封裝210。
圖3A-3B係描繪相關於步驟152及156的細節。一切割器301係在兩個圖中都被展示。如同在步驟152中所述並且如同在圖2A中所示,圖3A係描繪完全穿過該引線架並且部分穿過該模製物的階梯式切割的一個例子。在圖3A中所示的切割係在一第一厚度下加以做成的,該第一厚度係被配置以露出該些封裝210的引線204的側壁。該切割係在圖3A中被展示為利用一具有一標示為“Z1”的厚度的鋸刀來做成的,但是任何用於做成該切割的技術上可行的手段都可被利用,例如是一雷射切割器、一電漿切割器、或是一水刀切割器、或是任何其它如同對於具有此項技術中的技能者而言為已知可接受的切割技術。
圖3B係描繪該第二階梯式切割的一個例子,其係完全穿過在步驟152及圖2A的階梯式切割之後仍保留的封裝材料。該些引線204係具有一經由電解鍍覆而沉積於其上的鍍覆材料310,以形成階梯式切割的可潤濕的側面312。
圖4A-4D係描繪一單粒化的晶粒封裝210的不同的視圖,其係描繪根據圖1B的方法150所形成的階梯式切割的可潤濕的側面。圖4A及4B係描繪正投影視圖,其係描繪該封裝210的頂端及側邊,並且圖4C及4D係描繪正投影視圖,其係描繪該封裝210的底部及側邊。
一起參照圖4A-4D,所描繪的封裝210係包含一模製囊封202並且具有階梯式切割的可潤濕的側面312,其中根據在圖1B中所述的技術,電解鍍覆係被形成在兩個相對的側邊的引線204上。該些階梯式切割的可潤濕的側面312係包含做成步驟152及156的階梯式切割所在的晶粒封裝210的部分,並且亦包含被電解鍍覆的引線204。電耦接至該引線架205的在該模製囊封202內部的聯結條215、217及219的部分的邊緣係在該封裝210的未鍍覆的側邊中露出。圖4C及4D係描繪該些引線204以及晶粒承座206的底表面,其如同在此別處所述的是電解鍍覆的。
該舉例說明的封裝210係在內部包含一晶粒402。該晶粒402係被安裝在晶粒承座206之上,並且熱耦接至晶粒承座206,該晶粒承座206是該引線架205的一部分。引線接合係將該晶粒404耦接至該引線架205的引線204。該源極引線211以及閘極引線213係經由引線接合404來耦接至該晶粒402。再者,該源極引線211係耦接至一聯結條219,該聯結條219並未被鍍覆的,並且在完成的封裝中是無功能的,但是其係如同相關圖1B及2A-2E所述的為了維持在晶粒封裝之間的電性連續性以用於鍍覆之目的而被使用。該閘極引線213係耦接至一聯結條219,該聯結條219亦未被鍍覆的,並且作用為一類似用於該源極引線211的聯結條219的作用。該晶粒承座206係耦接至一聯結條217,該聯結條217亦在完成的封裝中未作用任何目的,並且未被鍍覆的,但是其係在鍍覆期間被利用來做成橫跨不同的晶粒封裝的完整的電連接。一聯結條215係存在於一相對的側邊上,並且耦接至該晶粒承座206。該聯結條215係作用為一類似其它聯結條的目的,並且未被鍍覆的。
圖5係描繪一舉例說明的電解鍍覆技術。此種技術例如可被使用作為在圖2B中描繪的步驟104的部分。根據該技術,在一電鍍裝置500中,該封裝組件200(其只有一部分係被展示在圖5中)係被設置在一溶液502之內。一電源504的陰極係電耦接至該引線架205,並且該電源504的陽極係耦接至一鍍覆材料506。當電流係藉由該電源504而被施加時,鍍覆材料508係沉積到該引線架205的露出表面之上。
將會體認到的是,先前的內容只是藉由舉例,而非藉由任何的限制來加以提出。所思及的是,各種的替代及修改都可以對於所述實施例來加以做成,而不脫離本發明的精神與範疇。在已經詳細地敘述本發明之下,將體認到並且對於熟習此項技術者而言將會明顯的是許多的物理改變(只有一些物理改變係被例示在本發明的詳細說明中)都可以在不改變本發明的被體現於其中的
概念及原理下加以做成。亦將體認到的是許多只納入該較佳實施例的部分的實施例是可能的,其相關的那些部分並不會改變本發明的被體現於其中的概念及原理。本實施例以及選配的配置係因此在所有的方面都將被視為範例及/或舉例說明的,而非限制性的,本發明的範疇係藉由所附的申請專利範圍而不是藉由先前的說明來加以指出的,並且落入該申請專利範圍的等同的意義及範圍內的所有替代實施例以及對於此實施例的改變係因此被涵括於其中。
202:模製囊封材料
204:封裝邊緣引線
206:晶粒承座
210:封裝
211:源極引線
213:閘極引線
217:聯結條
219:聯結條
312:階梯式切割的可潤濕的側面
Claims (19)
- 一種用於製造半導體封裝之方法,所述方法包括:提供引線架組件,所述引線架組件包含:複數個鍍覆條,所述複數個鍍覆條包括彼此分隔開且在第一方向上延伸的第一組鍍覆條以及彼此分隔開且在第二方向上延伸的第二組鍍覆條,所述第一方向垂直於所述第二方向;以及被組織成列的複數個晶粒封裝,每一個晶粒封裝具有積體電路晶粒以及複數個引線,所述複數個晶粒封裝的每一個晶粒封裝具有底表面、第一側和相對的第二側、第三側和相對的第四側,其中,所述複數個晶粒封裝的每一個晶粒封裝位在所述第一組鍍覆條中之鄰近所述晶粒封裝的所述第一側的一鍍覆條以及所述第一組鍍覆條中之鄰近所述晶粒封裝的所述第二側的一相對鍍覆條之間,並且所述複數個晶粒封裝的每一個晶粒封裝附接且電耦接至所述第一組鍍覆條中之鄰近所述晶粒封裝的所述第一側的所述鍍覆條以及所述第一組鍍覆條中之鄰近所述晶粒封裝的所述第二側的所述相對鍍覆條;其中,所述複數個晶粒封裝的每一個晶粒封裝位在所述第二組鍍覆條中之鄰近所述晶粒封裝的所述第三側的一鍍覆條以及所述第二組鍍覆條中之鄰近所述晶粒封裝的所述第四側的一相對鍍覆條之間,並且所述複數個晶粒封裝的每一個晶粒封裝附接且電耦接至所述第二組鍍覆條中之鄰近所述晶粒封裝的所述第三側的所述鍍覆條以及所述第二組鍍覆條中之鄰近所述晶粒封裝的所述第四側的所述相對鍍覆條;所述複數個晶粒封裝中的每一個晶粒封裝包括:晶粒承座,其經由單一第一聯結條來電耦接至在所述第一組鍍覆條中之鄰近所述晶粒封裝的所述第一側的所述鍍覆條中的個別鍍覆條,且所述晶粒承座經由單一第二聯結條來電耦接至在所述第一組鍍覆條中之 鄰近所述晶粒封裝的所述第二側的所述鍍覆條中的相對的個別鍍覆條;複數個引線,所述複數個引線的每一個引線具有側壁和底表面,所述複數個引線的至少一部分從所述晶粒承座延伸並且電耦接至所述晶粒承座,而所述複數個引線的至少一個引線與所述晶粒承座分隔開並且經由單一第三聯結條來電耦接至在所述第一組鍍覆條中之鄰近所述晶粒封裝的所述第二側的所述個別鍍覆條;藉由模製囊封來囊封所述引線架組件的至少部分,而露出所述複數個引線的底表面以及所述晶粒承座的底表面,所述引線架組件和所述模製囊封形成封裝組件;進行完全穿過所述封裝組件的所述第二組鍍覆條並且部分穿過所述封裝組件的所述模製囊封的第一系列的平行的切割,以產生所述複數個引線的側壁表面的露出部分;電鍍所述複數個引線的所述側壁表面的所述露出部分的至少部分;進行與所述第一系列的平行的切割對準的完全穿過所述模製囊封的第二系列的平行的切割,所述第二系列的平行的切割的寬度小於所述第一系列的平行的切割的寬度,藉此形成階梯式切割的可潤濕側邊;以及進行垂直於所述第一系列的平行的切割以及所述第二系列的平行的切割的第三系列的平行的切割,所述第三系列的平行的切割完全穿過所述模製囊封以及所述第一組鍍覆條。
- 如請求項1所述之方法,其中所述複數個引線的第一組引線被設置在鄰近於所述複數個晶粒封裝的個別晶粒封裝的所述第三側,且其中所述複數個引線的第二組引線被設置在鄰近於所述複數個晶粒封裝的個別晶粒封裝的所述第四側。
- 如請求項2所述之方法,其中所述第一組引線的側壁彼此沿著 鄰近於個別晶粒封裝的所述第三側的所述第二組鍍覆條中的個別鍍覆條的面向表面而對準;其中所述第二組引線的側壁彼此沿著鄰近於個別晶粒封裝的所述第四側的所述第二組鍍覆條中的個別鍍覆條的面向表面而對準。
- 如請求項1所述之方法,其中所述複數個引線中的所述至少一個引線與所述晶粒承座分隔開並且包括閘極引線。
- 如請求項4所述之方法,其中:所述複數個引線中的至少一個引線包括源極引線,所述源極引線與所述晶粒承座及所述閘極引線分隔開並且經由單一第四聯結條電耦接至與所述閘極引線相同的個別鍍覆條。
- 如請求項5所述之方法,其中所述第二聯結條延伸在所述閘極引線和所述源極引線之間。
- 如請求項1所述之方法,其進一步包括:電鍍所述晶粒承座的露出的所述底表面,並且電鍍所述複數個引線的露出的所述底表面。
- 如請求項1所述之方法,其中所述複數個晶粒封裝的每一個晶粒封裝的所述第一側以及所述複數個晶粒封裝的每一個晶粒封裝的所述第二側沒有被電解鍍覆。
- 如請求項1所述之方法,其中所述第一聯結條具有的直徑大於所述第二聯結條的直徑。
- 一種用於製造半導體封裝之方法,所述方法包括:提供晶粒封裝,其包括晶粒承座以及複數個引線,所述晶粒承座和所述複數個引線具有底表面,所述複數個引線中的每個引線具有側壁,其中所述複數個引線中的至少部分引線從所述晶粒承座延伸並且電耦接至所述晶粒承座,並且其中所述複數個引線中的至少一個引線是與所述晶粒承座 分隔開;提供複數個鍍覆條,其圍繞、附接且電耦接至所述晶粒封裝,所述複數個鍍覆條包括:彼此分隔開且在第一方向延伸的第一組鍍覆條以及彼此分隔開且在第二方向延伸的第二組鍍覆條,所述第一方向垂直於所述第二方向;經由單一第一聯結條而將所述晶粒承座的第一側電耦接至所述第一組鍍覆條的所述複數個鍍覆條中的一個鍍覆條;經由單一第二聯結條而將所述晶粒承座的相對的第二側電耦接至所述第一組鍍覆條的所述複數個鍍覆條中的另一個鍍覆條;經由單一第三聯結條而將所述複數個引線中之與所述晶粒承座分隔開的所述至少一個引線電耦接至所述第一組鍍覆條的所述複數個鍍覆條中的一個鍍覆條;藉由模製囊封來囊封所述晶粒承座的至少部分以及所述複數個鍍覆條中的至少部分,而露出所述複數個引線的所述底表面以及所述晶粒承座的所述底表面;進行穿過所述複數個鍍覆條的所述第二組鍍覆條並且部分穿過所述模製囊封的第一系列的平行的切割,以產生所述複數個引線的側壁表面的露出部分;電鍍所述複數個引線的所述側壁表面的露出部分的至少部分;進行與所述第一系列的平行的切割對準的完全穿過所述模製囊封的第二系列的平行的切割,所述第二系列的平行的切割的寬度小於所述第一系列的平行的切割的寬度,藉此形成階梯式切割的可潤濕側邊;以及進行垂直於所述第一系列的平行的切割以及所述第二系列的平行的切割的第三系列的平行的切割,所述第三系列的平行的切割係完全穿過所述模製囊封 以及所述複數個鍍覆條的所述第一組鍍覆條。
- 如請求項10所述之方法,其中所述複數個引線中之與所述晶粒承座分隔開的所述至少一個引線包括閘極引線。
- 如請求項11所述之方法,其中所述複數個引線中之至少一個引線包括源極引線,所述源極引線與所述晶粒承座及所述閘極引線分隔開並且經由單一第四聯結條電耦接至與所述閘極引線相同的個別鍍覆條。
- 如請求項12所述之方法,其中所述第二聯結條延伸在所述閘極引線和所述源極引線之間。
- 如請求項10所述之方法,其中所述晶粒封裝的所述第一側以及所述晶粒封裝的所述第二側沒有被電解鍍覆。
- 如請求項10所述之方法,其中所述第一聯結條具有的直徑是大於所述第二聯結條的直徑。
- 如請求項10所述之方法,其中所述複數個引線中的第一組引線被設置在相鄰於所述第二組鍍覆條中的一鍍覆條,並且其中所述複數個引線中的相應的第二組引線被設置在相鄰於所述第二組鍍覆條中的另一鍍覆條。
- 如請求項16所述之方法,其中所述第一組引線的側壁彼此沿著所述第二組鍍覆條中的個別鍍覆條的面向表面而對準;其中所述第二組引線的側壁彼此沿著所述第二組鍍覆條中的個別鍍覆條的面向表面而對準。
- 如請求項10所述之方法,其中所述引線包括銅,並且所述電鍍用錫來鍍覆所述引線。
- 一種雙側扁平無引線半導體封裝,其使用如請求項10所述之方法所製成的。
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080006937A1 (en) * | 2006-06-23 | 2008-01-10 | Texas Instruments Incorporated | Solderability Improvement Method for Leaded Semiconductor Package |
US20090079044A1 (en) * | 2007-09-20 | 2009-03-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method thereof |
TW201019404A (en) * | 2008-11-07 | 2010-05-16 | Chipmos Technologies Inc | Method of fabricating quad flat non-leaded package |
TW201128758A (en) * | 2010-02-12 | 2011-08-16 | Siliconware Precision Industries Co Ltd | Quad flat non leaded package structure capable of preventing electromagnetic interference and method for forming the same |
TW201133655A (en) * | 2010-03-22 | 2011-10-01 | Powertech Technology Inc | Packaging method of array-cutting type quad flat non-leaded packages |
US20150294924A1 (en) * | 2014-04-15 | 2015-10-15 | Zhigang Bai | Combined qfn and qfp semiconductor package |
US20170133302A1 (en) * | 2009-01-29 | 2017-05-11 | Semiconductor Components Industries, Llc | Leadless semiconductor packages, leadframes therefor, and methods of making |
TW201803060A (zh) * | 2016-04-07 | 2018-01-16 | 微晶片科技公司 | 具有改良接觸引線之扁平無引線封裝 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3759131B2 (ja) * | 2003-07-31 | 2006-03-22 | Necエレクトロニクス株式会社 | リードレスパッケージ型半導体装置とその製造方法 |
US7169651B2 (en) * | 2004-08-11 | 2007-01-30 | Advanced Semiconductor Engineering, Inc. | Process and lead frame for making leadless semiconductor packages |
US20150035166A1 (en) | 2009-01-29 | 2015-02-05 | Semiconductor Components Industries, Llc | Method for manufacturing a semiconductor component and structure |
EP2361000A1 (en) * | 2010-02-11 | 2011-08-24 | Nxp B.V. | Leadless chip package mounting method and carrier |
US9418919B2 (en) | 2010-07-29 | 2016-08-16 | Nxp B.V. | Leadless chip carrier having improved mountability |
EP2622635B1 (en) | 2010-09-29 | 2018-09-05 | Nexperia B.V. | Singulation of ic packages |
EP2980845B1 (en) * | 2014-08-01 | 2019-11-27 | Nexperia B.V. | A leadless semiconductor package and method |
US20160126169A1 (en) * | 2014-10-29 | 2016-05-05 | Nxp B.V. | Leadless semiconductor device and method of making thereof |
US20160148876A1 (en) * | 2014-11-20 | 2016-05-26 | Microchip Technology Incorporated | Flat no-leads package with improved contact pins |
JP6500299B2 (ja) * | 2015-03-10 | 2019-04-17 | 新日本無線株式会社 | リードフレームおよびそれを用いた半導体装置の製造方法 |
US10032645B1 (en) * | 2015-11-10 | 2018-07-24 | UTAC Headquarters Pte. Ltd. | Semiconductor package with multiple molding routing layers and a method of manufacturing the same |
JP6744149B2 (ja) * | 2016-06-20 | 2020-08-19 | ローム株式会社 | 半導体装置およびその製造方法 |
US10079198B1 (en) * | 2017-05-31 | 2018-09-18 | Stmicroelectronics, Inc. | QFN pre-molded leadframe having a solder wettable sidewall on each lead |
JP7267767B2 (ja) * | 2019-02-20 | 2023-05-02 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
CN113035722A (zh) * | 2019-12-24 | 2021-06-25 | 维谢综合半导体有限责任公司 | 具有选择性模制的用于镀覆的封装工艺 |
-
2019
- 2019-03-08 KR KR1020217032303A patent/KR20210135298A/ko not_active Application Discontinuation
- 2019-03-08 US US17/436,454 patent/US20220181239A1/en active Pending
- 2019-03-08 EP EP19918773.3A patent/EP3935662A4/en active Pending
- 2019-03-08 JP JP2021551936A patent/JP7384918B2/ja active Active
- 2019-03-08 CN CN201980093796.0A patent/CN113614879A/zh active Pending
- 2019-03-08 WO PCT/US2019/021272 patent/WO2020185192A1/en unknown
- 2019-03-29 TW TW108111152A patent/TWI833739B/zh active
-
2021
- 2021-09-02 IL IL286084A patent/IL286084A/en unknown
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080006937A1 (en) * | 2006-06-23 | 2008-01-10 | Texas Instruments Incorporated | Solderability Improvement Method for Leaded Semiconductor Package |
US20090079044A1 (en) * | 2007-09-20 | 2009-03-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method thereof |
TW201019404A (en) * | 2008-11-07 | 2010-05-16 | Chipmos Technologies Inc | Method of fabricating quad flat non-leaded package |
US20170133302A1 (en) * | 2009-01-29 | 2017-05-11 | Semiconductor Components Industries, Llc | Leadless semiconductor packages, leadframes therefor, and methods of making |
TW201128758A (en) * | 2010-02-12 | 2011-08-16 | Siliconware Precision Industries Co Ltd | Quad flat non leaded package structure capable of preventing electromagnetic interference and method for forming the same |
TW201133655A (en) * | 2010-03-22 | 2011-10-01 | Powertech Technology Inc | Packaging method of array-cutting type quad flat non-leaded packages |
US20150294924A1 (en) * | 2014-04-15 | 2015-10-15 | Zhigang Bai | Combined qfn and qfp semiconductor package |
TW201803060A (zh) * | 2016-04-07 | 2018-01-16 | 微晶片科技公司 | 具有改良接觸引線之扁平無引線封裝 |
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