TW201133655A - Packaging method of array-cutting type quad flat non-leaded packages - Google Patents

Packaging method of array-cutting type quad flat non-leaded packages Download PDF

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Publication number
TW201133655A
TW201133655A TW099108433A TW99108433A TW201133655A TW 201133655 A TW201133655 A TW 201133655A TW 099108433 A TW099108433 A TW 099108433A TW 99108433 A TW99108433 A TW 99108433A TW 201133655 A TW201133655 A TW 201133655A
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Taiwan
Prior art keywords
temporary carrier
carrier film
pads
array
wafers
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TW099108433A
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Chinese (zh)
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Chang-Chih Lin
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Powertech Technology Inc
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Priority to TW099108433A priority Critical patent/TW201133655A/en
Publication of TW201133655A publication Critical patent/TW201133655A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

Disclosed is a packaging method of array-cutting type quad flat non-leaded packages. One surface of a metal foil is completely covered by a temporary carrier formed by printing. The metal foil is selectively etched by exposure, developing and etching to form a plurality of contact pads attached onto the temporary carrier. At least a plating metal is formed over the contact pads. A plurality of chips are disposed on the temporary carrier. An encapsulant is formed on the temporary carrier to encapsulate and combine the contact pads and the chips. Then, the temporary carrier is removed by solvent dissolving, and the encapsulant is further cut to divide a plurality of package units. Accordingly, there can be avoided the problem of residual stress during packaging processes, the encapsulating volume is reduced, and furthermore cheaper and wider applications are presented.

Description

201133655 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置之封裝技術，特別係有關 於一種陣列切割式四方扁平無引腳封裝方法。 【先前技術】 近年來’四方扁平無引腳封裝（Quad Flat N〇n~leaded package，QFN)由於具有良好的電性傳輸和導熱性能、體 積小、重量輕之優點’其應用正在快速增長。四方扁平 無引腳封裝是一種無引腳式的小型半導體封裝結構，習 知使用無外引腳之導線架作為晶片載體。在呈現正方形 或矩形的封膠體底面會有延伸到邊緣的内引腳下表面， 以提供導熱與導電之作用。正由於四方扁平無引腳封裝 不需要傳統的SOIC與TSOP封裝的鷗翼狀引腳，封震產 品内導電路徑能夠縮短’同時使得内部自感係數與佈線 電阻降低。故除了能提供卓越的電性能之外，封裝產品 的尺寸亦可進一步地縮小。 如第1圖所示，為習知的陣列切割式四方扁平無引腳 封裝構造未切割前之截面示意圖，習知構造主要包含一 導線架110、一晶片140與一封膠體150。該導線架U0 係包含相同金屬材質之一晶片承座113與複數個細長指 狀之周邊接墊112。該晶片140係設置於該晶片承座U3 上，並且藉由複數個銲線142電性連接該晶片140之銲 墊141至該些周邊接墊112。該封膠體150係設置於該 導線架110之上表面111，並密封該晶片14〇與該些銲 201133655 線142。為了避免在封裝製程中周邊接墊112的散離位 移’該些周邊接》112必須一體連接至導線架在切割道 的框條且為周邊單排(至多兩排)的排列。在依照切割道 152單離切割出封裝單元之過程中必然會切磨到該些周 邊接墊U2的外側，易有金屬毛邊與接墊鬆動掉落之問 題。 以下進一步說明習知四方扁平無引腳封裝構造之製 造方法，包含以下步驟：「貼附導線架於膠帶上」之步驟 1、「設置晶片於導線架上」之步驟2、「固化黏晶膠」之 步驟3、「以打線方式電性連接晶片與導線架」之步驟4、 「電漿清洗導線架」之步驟5、「模封形成封膠體」之步 驟6、「撕離膠帶」之步驟7 '「後洪烤」之步驟8、厂殘 膠去除」之步驟9、「雷射標記」之步驟1〇以及「切割 封膠體」之步驟i卜配合參閱第】圖步驟】是提供該 導線架110’並貼附於一黏性PI膠帶上(圖中未繪出）， 該谬帶的設置僅能些許減少模封時產生在導線架下方的 模封溢膠，但無法完全避免模封溢膠的發生可能，並且 壓滾黏合膠帶與導線架之過 姆程t即在兩者之間的黏接界 面產生一機械應力。步驟2是藉由已知黏晶膠黏著固定 複數個晶片⑽於該導線架11G之晶片承座113上黏 晶膝可為熱固性環氧化合物。在步驟3中加熱固化黏晶 膠。之後’執仃步驟4，打線形成該些銲線142,例如金 線或—)線，以電性連接該些晶“0與該導線 架110之接墊112，再刦许丰碰r 執仃步驟5利用電漿清洗該導線 4 201133655 架110，移除在貼附膠帶時可能沾附於該些接墊112側 邊之黏著劑，以提供較佳的模封黏合.特性。接著，執行 步驟6,模封形成該封膠體15〇以密封該些晶片與 該些銲線142。執行步驟7,以機械或人工方式撕離在導 線架下方的膠帶。在完成步驟7之後，執行一後烘烤 mold cure)之步驟8，利用烘烤爐的加熱以完全固化該封201133655 VI. Description of the Invention: [Technical Field] The present invention relates to a packaging technology for a semiconductor device, and more particularly to an array-cut quad flat no-lead packaging method. [Prior Art] In recent years, the Quad Flat N〇n~leaded package (QFN) has been rapidly growing due to its excellent electrical and thermal conductivity, small size, and light weight. The quad flat no-lead package is a leadless small semiconductor package structure, and it is known to use a lead frame without an external lead as a wafer carrier. The bottom surface of the inner pin extending to the edge is provided on the bottom surface of the square or rectangular encapsulant to provide heat conduction and conduction. Because the quad flat no-lead package eliminates the need for gull-wing pins in conventional SOIC and TSOP packages, the conductive path in the sealed product can be shortened while reducing the internal self-inductance coefficient and wiring resistance. In addition to providing excellent electrical performance, the size of the packaged product can be further reduced. As shown in FIG. 1, a schematic cross-sectional view of a conventional array-cut quad flat no-lead package is shown before uncut. The conventional structure mainly includes a lead frame 110, a wafer 140 and a gel 150. The lead frame U0 comprises a wafer holder 113 of the same metal material and a plurality of elongated finger peripheral pads 112. The wafer 140 is disposed on the wafer holder U3, and the pads 141 of the wafer 140 are electrically connected to the peripheral pads 112 by a plurality of bonding wires 142. The encapsulant 150 is disposed on the upper surface 111 of the lead frame 110 and seals the wafer 14 and the soldered 201133655 line 142. In order to avoid the scatter position of the peripheral pads 112 during the packaging process, the peripheral connections 112 must be integrally connected to the frame of the lead frame at the scribe line and arranged in a single row (up to two rows). In the process of cutting out the package unit in accordance with the cutting path 152, the outer side of the peripheral pads U2 is inevitably cut, and the metal burrs and the pads are loosely dropped. The following is a further description of the manufacturing method of the conventional quad flat no-lead package structure, including the following steps: "Steps of attaching the lead frame to the tape", Step 2 of "Setting the wafer on the lead frame", "Curing the adhesive glue Step 3, Step 4 of "Electrically Connecting the Wafer and Lead Frame by Wire Threading", Step 5 of "Plastic Cleaning Lead Frame", Step 6 of "Mold Sealing Forming Encapsulant", Step of "Tear Off Tape" Step 7 of “Step 8 of “Back Burning”, Step 9 of “Removal of Residual Rubber”, Step 1 of “Laser Marking” and Step 1 of “Cutting Sealant” The frame 110' is attached to a viscous PI tape (not shown), and the yoke can only be used to reduce the over-molding of the molding under the lead frame, but the molding cannot be completely avoided. The occurrence of overflow glue is possible, and the pressure-bonding adhesive tape and the lead frame of the lead frame t, that is, the bonding interface between the two generates a mechanical stress. Step 2 is to fix the plurality of wafers (10) by a known adhesive bond to the wafer holder 113 of the lead frame 11G to form a thermosetting epoxy compound. In step 3, the adhesive is cured by heating. Then, in step 4, the wire is formed to form the wire 142, such as a gold wire or a wire, to electrically connect the crystal "0" to the pad 112 of the lead frame 110, and then robbing the bumper r. Step 5: cleaning the wire 4 201133655 frame 110 with plasma to remove the adhesive that may adhere to the sides of the pads 112 when the tape is attached to provide better mold adhesion and characteristics. Then, perform the steps. 6. Forming the encapsulant 15 to seal the wafers and the bonding wires 142. Performing step 7 mechanically or manually tears off the tape under the lead frame. After completing step 7, performing a post-baking Step 8 of baking the mold cure, using the heating of the baking oven to completely cure the seal

膠體150，隨後執行步驟9，以化學方式去除該導線架 110在接墊112之下表面之模封溢膠。執行步驟1〇，在 該封膠體150之頂面形成雷射標記，作為產品辨識碼。 最後’執行步冑U，沿著切割道152陣列切割該封膠體 150，以單體化分離該封膠體15〇為複數個封裝單元。 如第3圖所示，此為該導線架11〇之局部上視示, 圖。一般而言，該導線架110之材質係可選用易於飯亥, 之金屬’例如··銅。以往是先以㈣方式形成該導線架 110’在該導線架110成形之後會具有許多孔洞，再塵The colloid 150 is then subjected to step 9 to chemically remove the overfill of the leadframe 110 on the lower surface of the pad 112. After step 1 is performed, a laser mark is formed on the top surface of the sealant 150 as a product identification code. Finally, step 胄 is performed, and the encapsulant 150 is cut along the array of dicing streets 152 to singulate and separate the encapsulant 15 into a plurality of package units. As shown in Fig. 3, this is a partial view of the lead frame 11A. In general, the material of the lead frame 110 is made of a metal such as copper. In the past, the lead frame 110' was formed in the manner of (4). After the lead frame 110 is formed, it will have many holes and dust.

貼固疋於膠帶’以作為晶片載體方能繼續後續封裴 步驟。在膠帶的貼附至撕離的封裝過程中，會產生應力 殘留之問題’該封膝體150易有變形與在接塾下表面 留膠帶黏著劑夕 劑之問題，將降低了產品的可靠性。此外， 由於所使用的膠帶不作為蝕刻載體，製程更為繁瑣不 便，亦增加了整體的製造成本。 繁貞不 【發明内容】 為了解決上述之問題，本發明之主要目的係在於 陣列切割式四方色见3| 種 方扁千無引腳封裝方法，以暫時載體膜取 5 201133655 代以往膠帶雯做 解方式去 做為蝕刻載體，並在封膠體形成之後以溶 與黏i膠=時載體膜，故封裝製程中不會有殘留應力 戈留之問題。 本發明之-女—n 扁平無的係在於提供—種陣列切割式四方 宜與廣泛的應用方法，可以縮小封裝體積，並能提供便 本發明的 案來實現 的及解決其技術問題是採用以下技術方 聊封裂方Γ本發明揭示—種陣列切割式四方扁平無弓| 整彼覆-暫時=含：提供一金屬荡。以印刷方式完 影與該金屬猪之一表面。以曝光、顯 x丨方式圖案化蝕刻該金屬箔，以 暫時截/取馮貼附於該 呷戰體膜上之複數個接墊。形成 覆苔钴冤鍍金屬，以 以暫時载體膜上之該些接墊。設 暫時載艚胺， π置複數個晶片於該 栽體膜上’並使該些晶片電性連接至上 ::::。形成-封膠想於該暫時載继膜上，以密封: 與該些晶片。當該封膠趙形成之後，以溶 万式去除該暫時載體膜，以顯露該些接墊於上述表面 •ρ位.〇 ^該暫時載體膜去除之後，切到兮咖 單駚π 傻切割該封膠體，以 體化分離為複數個封裝單元，每一 5 , 母封裝卓兀内結合有 '—個之該些晶片與該些接墊。 本發明的目的及解決其技術問題還 措施進一步實I 還了採用以下技術The tape is attached to the tape as a wafer carrier to continue the subsequent sealing step. In the process of attaching the tape to the peeling package, there is a problem of residual stress. The knee body 150 is easily deformed and the adhesive agent is left on the lower surface of the joint, which will reduce the reliability of the product. . In addition, since the tape used is not used as an etching carrier, the process is more complicated and inconvenient, and the overall manufacturing cost is also increased. In order to solve the above problems, the main object of the present invention is to form an array-cut quadrilateral color to see a 3 | square flat 1000-pin package method, to take a temporary carrier film to take 5 201133655 The solution method is used as an etching carrier, and after the formation of the sealant, the carrier film is dissolved and adhered, so that there is no problem of residual stress remaining in the packaging process. The invention of the present invention is to provide an array-cutting method and a wide range of application methods, which can reduce the package volume, and can provide the solution of the present invention and solve the technical problem. The technical party talks about the cracking of the square. The invention discloses that the array is cut into a square flat without a bow | the whole cover - temporary = containing: providing a metal swing. Finished with the surface of one of the metal pigs by printing. The metal foil is patterned and etched by exposure and display to temporarily intercept/take a plurality of pads attached to the film of the battle film. A moss coated cobalt ruthenium metal is formed to temporarily seal the pads on the carrier film. It is assumed that the amide is temporarily loaded, π is placed on the carrier film, and the wafers are electrically connected to the upper ::::. The formation-sealing is intended to be applied to the temporary carrier film to seal: with the wafers. After the sealant is formed, the temporary carrier film is removed by a lysis method to expose the pads on the surface. ρ position. 〇^ After the temporary carrier film is removed, the diced 駚 駚 傻 傻 傻The encapsulant is separated into a plurality of package units by body composition, and each of the 5 and the mother package has a plurality of the wafers and the pads. The object of the present invention and the technical problems thereof are further solved.

SJ 在前述之陣列切割式四方扁平無引腳封裝方法中在 上述圖案化㈣之步針形叙該些接㈣可為陣列排 6 201133655 列在該些封裝單元内並且不相連接。 在前述之陣列切割式四方扁平無引腳封 上述圖案化韻刻之步驟中該金屬羯更可形中，在 暫時載體膜上之複數個晶片，附於該 丨回曰日乃枣屋，並且該電鍍 覆蓋該些晶片承座’以供設置該些晶片。 ’、 在前述之陣列切割式四方扁平無引腳封 設置該些晶片之步帮中，在該些晶片承座上决中，在 屬係邛共晶接合該些晶片。 -電鍍金In the above-mentioned array-cut quad flat no-lead packaging method, the SJ is described in the above-mentioned patterning (four) step pin type (4), and the array row 6 201133655 is listed in the package units and is not connected. In the foregoing step of the array-cut quad flat no-lead seal, the metal ruthenium is more formable, and a plurality of wafers on the temporary carrier film are attached to the 曰回曰日日枣屋, and The plating covers the wafer holders ' for providing the wafers. In the above-described array-cut quad flat no-lead package, in the step of arranging the wafers, the wafers are eutectic bonded to the wafers. - electroplating gold

在前述之陣列切割式四方扁平無引腳封裝方法中 溶解去除該暫時載體膜之步驟之後與在切割 步驟之前’可另包含之步驟…膠體之 接塾之顯露表面。丨驟為.形成-外接合層於該些 在前述之陣列切割式四方扁平無引㈣裝 外接合層之材質係可為錫。 中’該 該 在 以 在 在前述之陣列切割式四方扁平無引腳封 金屬结之材質係可為銅’該電鍍金屬係為鎳/細/合 在前述之陣列切割式四方扁平無引腳封裝方法^ 設置該些晶片之步驟之後，可藉由設置複數個銲線 使該些晶片電性連接至該些接塾上的電錢㈣。 在前述之陣列切割式四方扁平無引腳封震方 切割該封膠體之步驟中僅切割到該封膠體； 些接墊與該暫時載體膜。 刀J該 在刖述之陣列切割式四方扁平無引腳封裂方法中，該 暫時载體膜係可為銲罩介電材料，並且該暫時载體膜：⑸ 7 201133655 厚度不小於該金屬落之厚度的三分之一。 在前述之陣列切割式四方扁平無引腳封裝方法中，可 另包含-後供烤步帮，係實施於上述去除該暫時裁體膜 之步驟之後，以完全固化該封膠體。 由以上技術方案可以看出，本發明之陣列切割式四方 扁平無引腳封裝方法，有以τ優點與功效： 本發明係藉由在㈣前以印刷方式披覆暫時载體膜In the aforementioned array-cut quad flat no-lead packaging method, the step of dissolving and removing the temporary carrier film and the step of additionally including the step of colloidal bonding are performed before the cutting step. The material of the forming-external bonding layer in the array-cut quad flat no-lead (tetra) outer bonding layer may be tin. The material that can be used in the above-mentioned array-cut quad flat no-lead metallization can be copper. The electroplated metal is nickel/fine/closed in the aforementioned array-cut quad flat no-lead package. Method ^ After the step of setting the wafers, the plurality of bonding wires can be electrically connected to the electricity (4) on the interfaces. In the step of cutting the sealant by the array cutting quad flat no-pin seal, only the sealant is cut; some pads and the temporary carrier film. The knife J is in the array cutting quad flat no-pin sealing method described above, the temporary carrier film may be a solder mask dielectric material, and the temporary carrier film: (5) 7 201133655 thickness is not less than the metal falling One third of the thickness. In the foregoing array-cut quad flat no-lead packaging method, a post-bake step can be additionally included after the step of removing the temporary trim film to completely cure the encapsulant. It can be seen from the above technical solution that the array-cut quad flat no-lead packaging method of the present invention has the advantages and effects of τ: The present invention covers the temporary carrier film by printing before (4).

與在封料以溶解方式去除暫時㈣料為其中一 技術手#又。由於是以暫時載體膜取代以往膠帶更 做為蝕刻載體，故在封裝製程中不會有殘留應力與 黏著膝殘留之問題。 藉由蝕刻前以印刷方式披覆暫時載體膜與在封膠後 以溶解方式去除暫時載體膜作為其中一技術手段。 在暫時載體膜上飯刻形成之接墊可為陣列排列並且 不相連接，毋須如同習知的接墊排列於周邊，故可 以縮小封裝體積。 二、可藉由钱刻前以印刷方式坡覆暫時載體膜與在封膠 後以溶解方式去除暫時載體膜作為其中一技術手 段。本發明直接使用暫時載體膜作為蝕刻載體，故 可降低直接使用導線架作為載體之成本，更配合暫 時載體膜上金屬箱之材質係選用銅，亦可降低整體 的製造成本。因此’能提供便宜與廣泛的應用。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 8 201133655 注意的是，該些圖示均為 .^ , ^ a -韧化之示意圖，僅以示意方法 來說明本發明之基本架構 ^ ^ ^ . Α 何及實施方法，故僅顯示與本案 有關之7〇件與組合關係， ^ 竑 圓尹所顯不之兀件並非以實際 實施之數目、形狀、尺 寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例戋 ^ ^ ^ , 飞已誇張或是簡化處理，以提供更 清楚的描述。+ i 實施之數目、形狀及尺寸比例為-種 選置性之設計，詳细 裡 „ ^ ，疋件佈局可能更為複雜。 依據本發明之第一且 八體實施例，一種陣列切割式四方 扁平無？I腳封裝方法臬 當以…說明於第4圖之方塊流程圖、 第5A至5Q圖之元件 _ 不意圖以及第6圖繪示其接替 與晶片承座形成於暫時…其接墊 割式四方扁平A 2丨 上視不意圖。該陣列切 亜半趣.「如 成很稞弟4圖’包含以下主 , 供一金屬箔」之步驟2〗、「以印刷方 披覆一暫時載體膜 ^ 影盘蝕列方—、国 屬治」之步驟22、「以曝光、顯 23、「形成電鑛金屬以薄基: 成接塾」之步驟 屬覆蓋接墊」之步驟24、「設詈 於暫時載體胰之舟 叹置B日片 之步驟25、「形成封膠體 溶解方式去除暫時腾 J之步驟26以 …及r切二:：27、「後㈣」之步 出的元件锖參閲*s! 29’在各步供上表現 至5Q圖’詳細說明如下所示。 育先’執行步驟21。 屬羯210。1俨而 《參閱第5A圖所示’提供一金 /、體έ，該金屬箔210係為一可蝕刻之;fe 片，其材質係可為# , J馮鋼，由於鋼為較便宜 能降低整體的製“ 士 金屬材枓’故 ^成本。該金屬羯210之厚度係可介於 9 201133655 50至loo微米（μπι)之間。 執行步驟22。請參閱第5Β與5C圖所示，以印刷方 式完整披覆一暫時載體膜220於該金屬箔210之一表面 211。所謂是印刷方式除了可以是網版印刷也可以採用已 知的可均勻形成液態塗層的技術，例如滾壓印刷或是旋 轉塗佈。詳細而言，如第5Β圖所示’可藉由一刮刀221 或是滚壓筒（roll coating tool)均勻塗佈呈液態之該暫時 載體膜220於該表面211。接著，如第5C圖所示，烘烤 該暫時載體膜220，並且在固化之後翻轉該暫時載體膜 220 ’以使該金屬箔210位於該暫時載體膜220之上方。 在一較佳實施例中，該暫時載體膜220係可為銲罩介電 材料’並且該暫時載體膜220之厚度不小於該金屬箔21〇 之厚度的三分之一’以有效表現出載體作用。具體而言， 該暫時載體膜220之最小厚度係可介於2〇至5〇微米（μιη) 之間。 S1 執行步驟23。請參閱第5£>至511圖所示，以曝光、 顯影與蝕刻方式圖案化蝕刻該金屬落21〇 ,以形成為貼 於該暫時載體膜220上之複數個接墊212。如第5D圖 斤示可先形成一光阻層270於該金屬箔21〇上。接著， 第5Ε圖所不，進行一曝光動作，利用υν光照射該光 層270 ^在曝光動作完成之後，如第圖所示，進行 j影動作，此時移除部分之該光阻層27〇，並且顯露出 二屬4 210之預钱刻的部位。再如第5G圖所示，進 行-餘刻動作，在該光阻層27〇之保護下圖案化触刻該 10 201133655 金屬箔210 ’以形成該些接墊212。在一較佳實施例中， 該金屬箔210更可形成為貼附於該暫時载體膜22〇上之 複數個晶片承座213。最後，如第5H圖所示，完全移除 該光阻層270,使得該些接墊212能顯露於該暫時載體 膜220上。由於在本步驟中，該暫時載體膜22〇係可作 為蝕刻載體，在製程中僅需要進行一次蝕刻動作，而毋 須在製程前預先蝕刻該金屬箔21〇，故能簡化整體的製 程步驟，更可降低以往使用導線架作為載體之成本。 執行步驟24。請參閱第51圖所示，形成至少一電鍍 金屬230,以覆蓋該暫時載體膜22〇上之該些接墊212。 在一較佳實施例中，該電鍍金屬23〇係可為鎳/鈀/金， 以k供防錄與容易焊接之功能。此外，該電鍍金屬23〇 係可更覆蓋該些晶片承座2 13，以供設置晶片240。特別 是’該些晶片承座213與該些接墊212皆是在同一蝕刻 動作中完成，並且該電鍍金屬23〇亦是在一次電鍍動作 中同時覆蓋該些晶片承座213與該些接墊212，故能輕 易地簡化整體的製作過程，並大幅提升產能。 執行步驟25。請參閱第5j與5K圖所示，設置複數 個晶片240於該暫時載體膜22〇上，並使該些晶片24〇 電性連接至該些接墊212上的電鑛金屬230。可以使用 傳統黏晶膠先塗在該些晶片承座213上再黏著固定該些 晶片240之外，在不同實施例中，在設置該些晶片24〇 之步驟中’可利用晶圓等級預先形成在晶背的晶粒貼附 材料或是額外附加的預型片來固定該些晶片24〇。該些 11 201133655 晶片240係可為形成有積體電路（integrated circuit，IC) 之元件’例如記憶體、邏輯元件以及特殊應用積體電路 (ASIC) ’可由一晶圓（wafer)分割成顆粒狀，並且該些晶 片240之主動面係可形成有複數個銲墊241。之後，如 第5K圖所示’可藉由打線技術形成複數個銲線242，以 使該些晶片240之該些銲墊241電性連接至該些接塾 212上的電鍍金屬23〇。 執行步驟26。請參閱第5L圖所示，形成一封膠體250 於該暫時載體膜220上，以密封與結合該些接墊212與 該些晶片240。在本實施例中，該封膠體250係可由壓 模形成’並包含熱固性樹脂與無機陶瓷粉末之混合物。 由於本發明利用印刷方式完整彼覆該暫時載體膜220於 該金屬箔2 1 0再將該金屬箔2 1 0圖案化蝕刻，所形成之 接墊212之下表面完整且直接地被該暫時載體膜220所 覆蓋，該封膠體250之溢膠無法侵入該些接墊212之下 方，大幅改善模封溢膠的問題。此外，在該些接墊2 1 2 之側邊不會有習知膠帶貼附於導線架之黏著劑殘留，故 該封膠體25 0對該些接墊212以及該些晶片承座213的 結合力良好，可省略或縮短習知電漿清洗之步驟。 執行步驟27 ^請參閱第5M與5N圖所示，當該封膠 體250形成之後，以溶解方式去除該暫時載體膜220， 以顯露該些接墊212於上述表面之部位。首先，如第5M 圖所示，利用一洗劑222例如防焊漆有機溶劑，沖洗溶 解該暫時載體膜220，使得該暫時載體膜220逐漸被溶 12 201133655 解而析出。持續進行沖洗溶解動作，直到如f 5N圖所 示完全去除該暫時載體膜22〇，此時會顯露出該些接塾 212與該些晶片承座213未被該電鍍金屬23〇所包覆之 部位，並且該封膠體250之底面與該些接墊212係為共 平面之狀態。之後，可利用一後烘烤步驟，卩完全固： 該封膠體250。在本實施例中，完全固化之後的封膠體 250應選用不可被該洗劑222所溶解之材質。因此，該 暫時載體膜220毋須以機械或手動方式撕離，而是以溶 籲解方式自動去除，能夠在自動化作業下達到無膠帶黏著 劑與應力殘留之效果。此外’由於該暫時載體膜22〇係 以印刷方式形成，使得該暫時載體膜22〇與該些接墊2 Μ 以及該些晶片承座213之間能達到無缝隙的緊密結合關 係，故在製程中毋須擔心會有模封溢膠之問題產生，能 夠省略模封溢膠之去除步驟，進而降低製程成本。 在另一較佳變化實施例中，後烘烤步驟28係可實施 φ 於上述去除該暫時載體膜220之步驟27之後，以完全固 化該封膠體250。因此，即使該封膠體25〇意外地在該 些接墊212之下表面產生模封溢膠，亦可在上述去除步 驟27中被移除。在不同實施例中，若能讀保無模封溢膠 之問題，後烘烤步驟28亦可實施於上述去除步驟27之 前。 在本實施例中，如第50圖所示，在溶解去除該暫時 載體膜220之步驟之後，可形成一外接合層26〇於該些 接墊212之顯露表面，以提升導電接合性與抗氧化性。 13 201133655 更進一步地，該外接合層260亦可覆蓋於該些晶片承座 213之顯露4位。具體而言，該外接舍層260之材質係 可為錫’可利用化學鍍或電鍍方式形成。 執行步驟29。請參閱第5p圖所示，當該暫時載體膜 22〇去除之後，藉由複數個切割刀具253，沿著複數個切 割道252切割該封膠體25〇。再請參閱第5Q圖所示，在 切割之後’可單體化分離為複數個封裝單元251，每一 封裝單元251内結合有至少一個之該些晶片24〇與該些 接墊212。具體而言，該些切割道252係位於兩相鄰之 封裝單元251之間，且不會穿過該些接墊212。事實上， 在切割該封膠體250之步驟中，該些切割刀具253沿著 該些切割道252進行切割時僅會切割至該封膠體25〇， 而不會切割至該些接墊212與該暫時載體膜22〇，除了 能使該些切割刀具253之磨耗率大幅地降低之外，更毋 須擔心在切割中切傷了該些接墊212與該些晶片24〇而 影響了整體的電性功能。 U] 在本發明中’藉由在蝕刻前以印刷方式披覆該暫時载 體膜220 ’以暫時載體膜220為蝕刻載體，經圖案化姓 刻與封膠之後以溶解方式去除該暫時載體臈22〇，故該 暫時載體膜220能取代以往黏性膠帶，並作為蝕刻該金 屬箔210之載體用途。在該封膠體250形成之後，是以 該洗劑222去沖洗該暫時載體膜22〇。該暫時載體膜22〇 隨著沖洗動作而逐漸溶解析出。因此，在本發明中是利 用溶解方法將該暫時載體膜220去除，而顯露出該此曰 14 201133655 片承座2i3與該些接墊212未被 Λ电锻金屬230所覆蓋 之邻位’故封裝製程中不會有殘 問題。 留應力與黏著膠殘留之With the removal of the temporary (four) material in the sealing material in a dissolved manner, one of the technical hands # again. Since the conventional carrier film is used as the etching carrier instead of the conventional tape, there is no problem of residual stress and residual knee adhesion during the packaging process. It is one of the technical means to cover the temporary carrier film by printing before etching and to remove the temporary carrier film in a dissolved manner after sealing. The pads formed on the temporary carrier film can be arranged in an array and are not connected. It is not necessary to arrange the pads in the periphery as in the conventional pads, so that the package volume can be reduced. 2. The temporary carrier film can be sloped by printing before the ink is cut and the temporary carrier film can be removed by dissolution after sealing as one of the technical means. The invention directly uses the temporary carrier film as an etching carrier, so that the cost of directly using the lead frame as a carrier can be reduced, and the material of the metal box on the temporary carrier film is selected to be copper, which can also reduce the overall manufacturing cost. Therefore, it can provide cheap and wide-ranging applications. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it should be noted that the drawings are all schematic diagrams of .^, ^ a -toughening, and are illustrated by way of illustration only. The basic structure of the present invention ^ ^ ^ . 实施 and the implementation method, so only the 7 pieces and the combination relationship related to the case are displayed, ^ 竑 尹 尹 尹 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显Proportional drawing, some size ratios and other related size ratios 戋^ ^ ^, flying exaggerated or simplified processing to provide a clearer description. + i The number, shape and size ratio of the implementation are the design of the alternative. In detail, the layout of the components may be more complicated. According to the first and eighth embodiments of the present invention, an array-cut square The flat-free I-pin package method is described in the block diagram of FIG. 4, the components of the 5A to 5Q diagrams _ not intended, and the sixth diagram shows that the replacement and the wafer holder are formed temporarily... The cut-type square flat A 2 丨 is not intended. The array is very interesting. "If you are a very good brother, the picture 4 contains the following main, for a metal foil" step 2〗 Step 22 of the carrier film ^ shadow plate - the national governance", "Steps for exposure, display 23, "formation of electro-mineral metal to thin base: in-line" is a cover pad", step 24, " Step 25 of the temporary carrier pancreas sighs the B-day film, "The steps of forming the sealant dissolution method to remove the temporary entanglement J, and the second step::27, "after (four)" step 锖See *s! 29' for performance on each step to 5Q chart' detailed description is as follows. The first step is to perform step 21.羯210. 1俨 and "see Figure 5A to provide a gold / body έ, the metal foil 210 is an etchable; fe film, the material can be #, J Fenggang, due to steel To be cheaper, the overall cost of the "metal material" can be reduced. The thickness of the metal crucible 210 can be between 9 201133655 50 and loo micron (μπι). Perform step 22. See pages 5 and 5C. As shown, a temporary carrier film 220 is completely overprinted on one surface 211 of the metal foil 210. The so-called printing method can also employ a known technique for uniformly forming a liquid coating, in addition to screen printing. For example, roll printing or spin coating. In detail, as shown in FIG. 5, the temporary carrier film 220 can be uniformly coated in a liquid state by a doctor blade 221 or a roll coating tool. Surface 211. Next, as shown in Fig. 5C, the temporary carrier film 220 is baked, and the temporary carrier film 220' is inverted after curing so that the metal foil 210 is positioned above the temporary carrier film 220. In an embodiment, the temporary carrier film 220 can be a solder mask dielectric The material 'and the thickness of the temporary carrier film 220 is not less than one third of the thickness of the metal foil 21' to effectively exhibit the effect of the carrier. Specifically, the minimum thickness of the temporary carrier film 220 may be between 2 〇. Between 5 〇 micron (μιη) S1 is performed in step 23. Referring to Fig. 5 to 511, the metal etch is patterned by exposure, development and etching to form a paste. A plurality of pads 212 on the temporary carrier film 220. A photoresist layer 270 may be formed on the metal foil 21A as shown in FIG. 5D. Then, in the fifth diagram, an exposure operation is performed to utilize the υν light. After irradiating the light layer 270 ^, after the exposure operation is completed, as shown in the figure, a shadow action is performed, at which time a portion of the photoresist layer 27 is removed, and a portion of the second genus 4 210 is exposed. Further, as shown in FIG. 5G, a carry-after-etch operation is performed to pattern the 10 201133655 metal foil 210 ′ under the protection of the photoresist layer 27 to form the pads 212. In a preferred embodiment, The metal foil 210 may be formed to be attached to the plurality of temporary carrier films 22 The wafer carrier 213. Finally, as shown in Fig. 5H, the photoresist layer 270 is completely removed, so that the pads 212 can be exposed on the temporary carrier film 220. Since in this step, the temporary carrier film The lanthanum can be used as an etch carrier, and only one etching operation is required in the process, and the metal foil 21 预先 is not etched before the process, so that the overall process steps can be simplified, and the cost of using the lead frame as a carrier can be reduced. Step 24 is performed. Referring to FIG. 51, at least one plating metal 230 is formed to cover the pads 212 on the temporary carrier film 22. In a preferred embodiment, the electroplated metal 23 can be nickel/palladium/gold, with k for anti-recording and easy soldering. In addition, the plating metal 23 can further cover the wafer holders 2 13 for mounting the wafer 240. In particular, the wafer holders 213 and the pads 212 are all completed in the same etching operation, and the plating metal 23 is also covered by the wafer holders 213 and the pads in a single plating operation. 212, it can easily simplify the overall production process and significantly increase production capacity. Go to Step 25. Referring to Figures 5j and 5K, a plurality of wafers 240 are disposed on the temporary carrier film 22, and the wafers 24 are electrically connected to the electro-mineral metal 230 on the pads 212. A conventional adhesive can be applied to the wafer holders 213 and then adhered to the wafers 240. In various embodiments, in the step of disposing the wafers 24, the wafer level can be pre-formed. The wafer-attached material on the back of the crystal or an additional pre-form is used to hold the wafers 24〇. The 11 201133655 wafer 240 can be an element formed with an integrated circuit (IC), such as a memory, a logic element, and an application-specific integrated circuit (ASIC), which can be divided into particles by a wafer. And the active surface of the wafers 240 can be formed with a plurality of pads 241. Then, as shown in FIG. 5K, a plurality of bonding wires 242 can be formed by a wire bonding technique, so that the pads 241 of the wafers 240 are electrically connected to the plating metal 23〇 on the pads 212. Go to step 26. Referring to Figure 5L, a colloid 250 is formed on the temporary carrier film 220 to seal and bond the pads 212 and the wafers 240. In the present embodiment, the encapsulant 250 is formed by compression molding and comprises a mixture of a thermosetting resin and an inorganic ceramic powder. Since the present invention uses the printing method to completely etch the temporary carrier film 220 on the metal foil 2 10 and then etches the metal foil 210, the lower surface of the formed pad 212 is completely and directly used by the temporary carrier. Covered by the film 220, the glue of the sealant 250 cannot penetrate under the pads 212, which greatly improves the problem of molding overfill. In addition, on the side of the pads 2 1 2, there is no adhesive residue adhered to the lead frame by the conventional tape, so the sealing body 25 is combined with the pads 212 and the wafer holders 213. The force is good, and the steps of conventional plasma cleaning can be omitted or shortened. Step 27 is performed. Referring to Figures 5M and 5N, after the encapsulant 250 is formed, the temporary carrier film 220 is removed in a dissolved manner to expose portions of the pads 212 on the surface. First, as shown in Fig. 5M, the temporary carrier film 220 is dissolved and dissolved by a lotion 222 such as a solder resist organic solvent, so that the temporary carrier film 220 is gradually precipitated by dissolution. The rinsing and dissolving action is continued until the temporary carrier film 22 is completely removed as shown in FIG. 5 5 , and the tabs 212 and the wafer holders 213 are not covered by the plating metal 23 显. The bottom surface of the sealant 250 and the pads 212 are in a coplanar state. Thereafter, a post-baking step can be utilized to completely cure the encapsulant 250. In this embodiment, the encapsulant 250 after complete curing should be made of a material that is not soluble by the lotion 222. Therefore, the temporary carrier film 220 does not need to be peeled off mechanically or manually, but is automatically removed by a solvent solution, and the effect of the tape-free adhesive and stress residual can be achieved under automated work. In addition, since the temporary carrier film 22 is formed in a printing manner, the temporary carrier film 22 is closely bonded to the pads 2 and the wafer holders 213, so that the process is in a process. The lieutenant must worry about the problem of mold overfilling, and can eliminate the removal step of the mold overflow, thereby reducing the process cost. In another preferred variation, the post-baking step 28 can be performed φ after the step 27 of removing the temporary carrier film 220 described above to completely cure the encapsulant 250. Therefore, even if the encapsulant 25 accidentally produces a molding overfill on the lower surface of the pads 212, it can be removed in the above removing step 27. In various embodiments, the post-baking step 28 can also be performed prior to the removal step 27 described above if the problem of the mold-free overflow is read. In this embodiment, as shown in FIG. 50, after the step of dissolving and removing the temporary carrier film 220, an outer bonding layer 26 may be formed on the exposed surface of the pads 212 to improve conductive bonding and resistance. Oxidizing properties. 13 201133655 Further, the outer bonding layer 260 may also cover the exposed 4 positions of the wafer holders 213. Specifically, the material of the outer layer 260 can be formed by electroless plating or electroplating. Go to step 29. Referring to Figure 5p, after the temporary carrier film 22 is removed, the encapsulant 25 is cut along a plurality of cutting passes 252 by a plurality of cutting tools 253. Referring to FIG. 5Q, after dicing, it can be singulated into a plurality of package units 251, and each package unit 251 is combined with at least one of the wafers 24 and 212. Specifically, the scribe lines 252 are located between two adjacent package units 251 and do not pass through the pads 212. In fact, in the step of cutting the sealant 250, the cutting tools 253 cut only to the sealant 25 沿着 along the scribe lines 252 without cutting to the pads 212 and the The temporary carrier film 22 is not only capable of greatly reducing the wear rate of the cutting tools 253, but also the need to worry that the pads 212 and the wafers 24 are cut during the cutting to affect the overall electrical function. . U] In the present invention, by temporarily coating the temporary carrier film 220' before the etching, the temporary carrier film 220 is used as an etching carrier, and the temporary carrier is removed in a dissolved manner after patterning and sealing. 22, the temporary carrier film 220 can replace the conventional adhesive tape and serve as a carrier for etching the metal foil 210. After the encapsulant 250 is formed, the temporary carrier film 22 is rinsed with the lotion 222. The temporary carrier film 22 is gradually dissolved and precipitated in accordance with the rinsing action. Therefore, in the present invention, the temporary carrier film 220 is removed by a dissolution method, and the 曰14 201133655 piece holder 2i3 and the adjacent pads 212 are not covered by the electric forging metal 230. There are no problems in the packaging process. Residual stress and adhesive residue

特別是，在上述圖案化蝕刻之I , <步驟甲形成之該些接墊 212係可為陣列排列在該些 一 址，地 -展早70 251内並且不相連 接U配合參酌第5Q圖所示），故太 ^ ^ )故本發明的接墊可以多排 陣列配置且不需要延伸到切割 ^ ^ ^ ^ 達到縮小封裝體積並 铨供便且與廣泛的應用’例如 用於本發明所揭示的 連接方式’或在另一變化實雜你丨士 ★ 貫施例中亦可運用於覆晶 ^方式。如第6圖所示’在該些封裝單元251中之該 二接墊2 12係皆為電性獨立 倜之狀態。該些接墊212係可 為夕排交錯排列於該晶片承 小厘213該些接墊212可為 矩形或方塊體，不需要延伸&丨&利* 两 萬要延伸到切割道。在-較佳實施例 由:本發明之該暫時載體膜220係可作為餘刻載 故犯藉由不同的蝕刻方式以變換該些接墊212之形 狀、大小或配置，以因應各種不同的產品需求，例如可 ^ j周邊兩排以上的配置。該些接墊的排列可更加 、該二接墊212之間邊緣至邊緣的間隙可等於或 不超過該些捲 —梁墊212之同向邊長。在本實施例中，該些 塾212之間邊緣至邊緣的間隙約為0.25爱米，該些接 墊212之同向邊長約為〇 25爱米該些接塾μ?至: 道的最短距離約為〇.125楚米。 依據本發明之第二具體實施例，另-種陣列切割式四 方扁平無引腳封裝方法舉例說明於第7A至7F圖之元件In particular, the pads 212 formed in the above-described patterned etching I, <Step A may be arranged in an array at the same address, in the ground-extension 70 251 and not connected to the U. As shown in the drawings), the pads of the present invention can be arranged in a plurality of rows and do not need to be extended to the cutting surface to achieve a reduced package volume and to be used in a wide range of applications, for example, for use in the present invention. The method of revealing the connection 'or another variation can be used in the application of the gentleman ^ method. As shown in Fig. 6, the two pads 2 12 in the package units 251 are electrically independent. The pads 212 may be staggered for the wafer row 213. The pads 212 may be rectangular or block-shaped, and do not need to extend &&& In the preferred embodiment, the temporary carrier film 220 of the present invention can be used as a residual carrier to change the shape, size or configuration of the pads 212 in response to various products. Demand, for example, can be configured in two or more rows around the j. The pads may be arranged in a more uniform manner, and the gap between the two pads 212 may be equal to or less than the same side length of the plurality of rolls-beam pads 212. In this embodiment, the edge-to-edge gap between the turns 212 is about 0.25 meters, and the same side length of the pads 212 is about 25 meters. The distance is about 125.125Cumi. According to a second embodiment of the present invention, another array-cut quad flat no-lead package method is illustrated in the components of Figures 7A through 7F.

T t SI 15 201133655 截面示意圖。其中與第·一實施例相同的主要元件將以相 同符號標示，不再詳予贅述。 請參閱第7A圖所示，提供一金屬箔21 0，並以印刷 方式完整彼覆一暫時載體膜220於該金屬箔210之一表 面211。在棋烤以使該暫時載體膜220成形之後，翻轉 該暫時載體臈220，此時該金屬箔210位於該暫時載體 膜220之上。 請參閱第7B圖所示，以曝光、顯影與蝕刻方式圖案 鲁 化姓刻該金屬箔210,以形成為貼附於該暫時載體膜220 上之複數個接墊212。在本實施例之該步驟中，該金屬 領210係可毋須形成晶片承座，僅是形成該些接墊212。 請參閱第7C圖所示，形成至少一電鍵金屬230，以 覆蓋該暫時載體膜220上之該些接墊212»較佳地，由 於在本實施例中未有晶片承座形成’故能夠減少該電錄 金屬230之使用量’進而降低了整體的製造成本。 φ 請參閱第7D圖所示，設置複數個晶片240於該暫時 載體膜220上，並使該些晶片240電性連接至該些接墊 212上的電鍍金屬23 0。在本實施例中，可直接以複數個 晶圓級晶片貼附膜280(Die Attach Film，DAF)將該些晶 片240之背面黏貼至該暫時載體膜22〇上未形成有該些 接墊212之空白區域，令該些晶片24〇直接設置於該暫 時载體膜220 Ji。之後，再藉由打線方式形成複數個銲 線242，以電性連接該些晶片24〇之複數個銲墊241至 該些接墊212。 1^1 16 201133655 . 請參閱第7E圖所示，形成一封膠體250於該暫時載 體膜220上，以密封與結合該些接墊212與該些晶片 240。之後’再利用洗劑沖洗該暫時載體膜22〇，以溶解 方式去除該暫時載體膜220，由於過程中以化學方式進 行移除該暫時载體膜220之動作，故毋須擔心會有殘留 應力與黏著膠殘留之問題產生。 明參閱第7F圖所示，形成一外接合層260於該些接 塾212之顯露表面。當該暫時載體膜220被移除之後， ® 會同時顯露出該些接墊212未被該電鍵金屬23〇所覆蓋 P彳/、該些曰曰圓級晶片貼附旗28〇。由於該些晶圓級 a曰片貼附犋280不具有電性導通之作用，故該外接合層 260僅形成於該些接墊212之顯露表面而未形成於該 些晶圓級晶片貼附膜280。在本實施例中，因為省略了 晶片承座之高度，能夠降低該封膠體25〇之厚度，更使 侍產im具備了體積小與重量輕之優點。 • 以上所述，僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，耗本發明已讀佳實施例 揭露如上，然而並非用以限定本發日月，任何熟悉本項技 術者，在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修飾，均仍屬於本發明的技術範圍 内。 【圖式簡單說明】 第1圖：為習知的陣列切割式四方扁平無引腳封裝構造 未切割前之截面示意圖。 17 201133655 第2圖：為習知的陣歹彳切 之方塊流程圖。 方扁平無5丨腳封裝方法 第3圖：為習知的陣列切 中所使用之導綠架之Ά扁千無引腳封裝方法 第4圖··依據本發明之第—局部上視示意圖。 式四方扁平無⑼封具裝體方實:例的-種㈣ 第5入至5Q圖··依據本發明 法之方塊流程圖。 割式四方扁平盔 一具體實施例的陣列切 面示意圖。4腳封裝方法在製程中元件截 第6圖：依據本發明之第— 、體實施例的陣列切割式四 方扁平無引腳封桊古& 之圖案化敍刻後繪示所 形成之接塾與H + 、 、片承座於暫時載體膜上之局部 上視示意圖。 第7A至7F圖：依據本發明一 ^第一具體實施例的一種陣 列切割式四方扁平無引腳封裝方法在主要製程 中元件截面示意圖。 【主要元件符號說明】 步驟1 貼附導線架於膠帶上 步驟2 設置晶片於導線架上 步驟3 固化黏晶膠 步驟4 以打線方式電性連接晶片與導線架 步驟5 電漿清洗導線架 步驟6 模封形成封膠體 步驟7 撕離膠帶 18 201133655 步驟8 後烘烤 步驟9 殘膠去除 步驟1 0 雷射標記 步驟11 切割封膠體 步驟2 1 提供一金屬箔 步驟22 以印刷方式披覆一暫時載體膜於金屬箔 步驟23 以曝光、顯影與蝕刻方式圖案化蝕刻金屬箔以 形成接墊 ® 步驟24 形成電鍍金屬於接墊 步驟25 設置晶片於暫時載體膜上 步驟26 形成封膠體 步驟27 以溶解方式去除暫時載體膜 步驟28 後烘烤 步驟29 切割封膠體 110 導線架 111 上表面 112 周邊接墊 113 晶片承座 140 晶片 141 銲墊 142 銲線 150 封膠體 152 切割道 210 金屬箔 211 表面 212 接墊 213 晶片承座 220 暫時載體膜 221 刮刀 222 洗劑 230 電鍍金屬 240 晶片 241 銲墊 242 銲線 250 封膠體 19 201133655 251封裝單元 252切割道 253切割刀具 260 外接合層 270光阻層 2 8 0 晶圓級晶片貼附膜T t SI 15 201133655 Cross-section schematic. The same elements as those in the first embodiment will be denoted by the same reference numerals and will not be described in detail. Referring to Fig. 7A, a metal foil 210 is provided and a temporary carrier film 220 is integrally printed on one surface 211 of the metal foil 210 in a printed manner. After the chess is baked to shape the temporary carrier film 220, the temporary carrier 臈 220 is inverted, at which time the metal foil 210 is positioned over the temporary carrier film 220. Referring to Fig. 7B, the metal foil 210 is patterned by exposure, development and etching to form a plurality of pads 212 attached to the temporary carrier film 220. In this step of the embodiment, the metal collar 210 does not require the formation of a wafer holder, but only the pads 212 are formed. Referring to FIG. 7C, at least one of the key metal 230 is formed to cover the pads 212 on the temporary carrier film 220. Preferably, since no wafer holder is formed in the embodiment, the reduction can be reduced. The amount of use of the electromagnet metal 230 further reduces the overall manufacturing cost. φ As shown in FIG. 7D, a plurality of wafers 240 are disposed on the temporary carrier film 220, and the wafers 240 are electrically connected to the plating metal 230 on the pads 212. In this embodiment, the back surface of the wafers 240 can be directly adhered to the temporary carrier film 22 by a plurality of wafer-level wafer attaching films 280 (DAF), and the pads 212 are not formed. The blank area is such that the wafers 24 are directly disposed on the temporary carrier film 220 Ji. Then, a plurality of soldering wires 242 are formed by wire bonding to electrically connect the plurality of pads 241 of the plurality of wafers 24 to the pads 212. 1^1 16 201133655 . Referring to FIG. 7E, a colloid 250 is formed on the temporary carrier film 220 to seal and bond the pads 212 and the wafers 240. Thereafter, the temporary carrier film 22 is rinsed by a washing agent to remove the temporary carrier film 220 in a dissolved manner. Since the temporary carrier film 220 is chemically removed during the process, there is no fear of residual stress. The problem of adhesive residue is generated. Referring to Figure 7F, an outer bonding layer 260 is formed on the exposed surface of the pads 212. After the temporary carrier film 220 is removed, ® will simultaneously reveal that the pads 212 are not covered by the key metal 23〇, and the round wafers are attached to the flag 28〇. Since the wafer level a 贴 贴 280 does not have an electrical conduction function, the outer bonding layer 260 is formed only on the exposed surface of the pads 212 and is not formed on the wafer level wafers. Film 280. In the present embodiment, since the height of the wafer holder is omitted, the thickness of the sealant 25 can be reduced, and the product im is advantageous in that it is small in size and light in weight. The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. The preferred embodiment of the present invention has been disclosed above, but is not intended to limit the present invention. Any simple modifications, equivalent changes, and modifications made by those skilled in the art without departing from the technical scope of the present invention are still within the technical scope of the present invention. [Simple diagram of the diagram] Figure 1: Schematic diagram of the conventional array-cut quad flat no-lead package structure before uncut. 17 201133655 Fig. 2: Flow chart of the block for the conventional array. Square flat no 5 foot package method Fig. 3: A method for packaging the green frame used in the conventional array cutting method. Fig. 4 is a partial top view according to the present invention. Four-square flat no (9) seal assembly body: example - species (four) 5th to 5Q diagram · According to the block diagram of the method of the present invention. Cut-type square flat helmet A schematic view of an array of a specific embodiment. 4-pin encapsulation method in the process of component truncation Figure 6: According to the invention, the array-cut quadrilateral flat no-lead seal of the body embodiment is patterned and stenciled to form the interface A schematic top view of the H + , and the sheet on the temporary carrier film. 7A to 7F are views showing a cross-sectional view of an element in a main process in an array-cut quad flat no-lead package method according to a first embodiment of the present invention. [Main component symbol description] Step 1 Attach the lead frame to the tape. Step 2 Set the wafer on the lead frame. Step 3: Curing the adhesive. Step 4 Electrically connect the wafer and lead frame by wire bonding. Step 5 Plasma cleaning lead frame Step 6 Molding to form the encapsulant Step 7 Tear off the tape 18 201133655 Step 8 Post-baking step 9 Residue removal step 1 0 Laser marking step 11 Cutting the encapsulant Step 2 1 Provide a metal foil Step 22 Print a temporary carrier Film in metal foil step 23: patterning and etching metal foil by exposure, development and etching to form pads® Step 24 Forming plating metal on the pad Step 25 Setting the wafer on the temporary carrier film Step 26 Forming the encapsulant step 27 in a dissolved manner Removal of temporary carrier film Step 28 Post-baking step 29 Cutting encapsulant 110 Lead frame 111 Upper surface 112 Peripheral pad 113 Wafer holder 140 Wafer 141 Pad 142 Wire bond 150 Sealant 152 Cutter 210 Metal foil 211 Surface 212 Pad 213 wafer holder 220 temporary carrier film 221 blade 222 lotion 230 plating metal 240 Wafer 241 Pad 242 Wire Bonding 250 Sealing Body 19 201133655 251 Packaging Unit 252 Cutting Road 253 Cutting Tool 260 Outer Bonding Layer 270 Photoresist Layer 2 8 0 Wafer Level Wafer Attachment Film

2020

Claims (1)

201133655 七、申請專利範圍· 種陣列切割式四方扁平盔μ阶+ ，十無引腳封裝方法，包 提供一金屬箔； 以印刷方式完整彼覆一暫時葡 节旰載體膜於該金屬箔之一 表面； 以曝光、顯影與蝕刻方式圖案化蝕刻該金屬猪，以 形成為貼附於該暫時載體膜 戰體膜上之複數個接墊； 形成至少一電鍍金屬，以霜荃201133655 VII, the scope of application for patents · Array-cut quadrilateral flat helmet μ-order +, ten-lead package method, package provides a metal foil; complete by printing a temporary Portuguese 旰 carrier film in one of the metal foil Surface etching; patterning the metal pig by exposure, development and etching to form a plurality of pads attached to the film film of the temporary carrier film; forming at least one plating metal to frost 復蓋誘暫時載體膜上之該 些接塾； 設置複數個晶片於該暫時載體肢 町戰髖膜上，並使該些晶片 電性連接至該些接墊上的電錢金屬； 形成一封膠體於該暫時載體膜上 執遐臊上，以密封與結合每 些接墊與該些晶片； 當該封膠體形成之後，以溶解太々i μ / 合解方式去除該暫時載韻 膜，以顯露該些接墊於上述表面之部位.以及 當該暫時載體膜去除之後，切割該封膠體，以單體 化分離為複數個封裝單元，每—封裝單元内結合 有至少一個之該些晶片與該些接墊。 依據申請專利範圍第i項之陣列切割式四方扁平無 引腳封裝方法，其中在上述圖案化㈣之步驟中形 成之該些接塾係料列排列在些封t #元内並且 不相連接。 依據申請專利範圍第】項之陣列切割式四方扁 引腳封裝方法，苴中在Η诚圖垒几社w '… 八甲在上迷圖案化蝕刻之步驟中該 21 3 201133655 龙镯洎更形成為貼附於該暫時載體膜上之複數個晶 片承座，並且該電鍍金屬係更覆蓋該些晶片承座，曰 以供設置該些晶片。 4依據申請專利範圍第3項之陣列切割式四方扁平無 引腳封裝方法，其中在設置該些晶片之步驟中在 該些晶片承座上之該電鑛金屬係共晶接合該些曰曰 片。 — aa 5、依據申請專利範圍第i項之陣列切割式四 | 6 引腳封裝方法，在溶解去除該暫時載體膜之步驟： 後與在切割該㈣體之步驟之前，$包含之步驟 為：形成—外接合層於該些接墊之顯露表面。 ，據申請專利範圍第5項之陣列㈣式四方 乂：封裝方法，其中該外接合層之材質係為锡/、 、依據申請專利範圍第i或6項之陣列切割式 平無引腳封裝方法’其中該金屬落之材質係為鋼， 該電鍍金屬係為鎳/鈀/金。 8、依據申請專利範圍第1或4項之陣列切割式四方扁 平無引腳封裝方法，在設置該些晶片之步驟， 藉由設置福封加 複數個銲線，以使該些晶片電性連接 些接墊上的電鍍金屬。 " 依據申請專利範圍第1或2項之陣列切割式四方扁 平無引腳封裝方法，其中在切割該封膠體之步驟中 僅切割到該鉍脚 Ύ 对膠體，而不切割該些接墊與該暫時 體膜。 m 22 201133655 1 ο、依據申請專利範圍第1或2項之陣列切割式四方 扁平無引腳封裝方法，其中該暫時載體膜係為銲罩 介電材料，並且該暫時載體膜之厚度不小於該金屬 箔之厚度的三分之一。 11、依據申請專利範圍第1、2、3、4或5項之陣列切 割式四方扁平無引腳封裝方法，另包含一後烘烤步 驟，係實施於上述去除該暫時載體膜之步驟之後， 以完全固化該封膠體。Covering the plurality of contacts on the temporary carrier film; setting a plurality of wafers on the temporary carrier limbs to fight the hip membrane, and electrically connecting the wafers to the money metal on the pads; forming a colloid Performing on the temporary carrier film to seal and bond each of the pads and the wafers; after the sealant is formed, the temporary carrier film is removed by dissolving the 々i μ /recombination method to reveal The pads are on the surface of the surface. After the temporary carrier film is removed, the encapsulant is diced and separated into a plurality of package units, and at least one of the wafers is bonded to each of the package units. Some pads. The array-cut quad flat no-pin package method according to claim i, wherein the plurality of tabs formed in the step of patterning (4) are arranged in a plurality of t# elements and are not connected. According to the patent application scope item 】 array cutting quad flat pin packaging method, 苴中在Η诚图垒社w '... 八甲 in the step of the pattern etching process, the 21 3 201133655 dragon bracelet 洎 formation A plurality of wafer holders attached to the temporary carrier film, and the plating metal further covers the wafer holders for mounting the wafers. 4. The array-cut quad flat no-lead packaging method according to claim 3, wherein the electro-mineral metal eutectic bonding of the germanium on the wafer holders in the step of disposing the wafers . — aa 5. According to the array-cutting four | 6-pin encapsulation method of the scope of the patent application, after the step of dissolving and removing the temporary carrier film: and after the step of cutting the (four) body, the steps of the inclusion are: Forming an outer bonding layer on the exposed surface of the pads. According to the fifth aspect of the patent application scope (four) type square: package method, wherein the material of the outer joint layer is tin /, according to the patent application scope i or 6 array cutting flat no-lead packaging method 'The material in which the metal falls is made of steel, and the plated metal is nickel/palladium/gold. 8. According to the array-cut quad flat no-lead packaging method of claim 1 or 4, in the step of disposing the wafers, a plurality of bonding wires are added by setting a fuse to electrically connect the wafers. Electroplated metal on some pads. " The array-cut quad flat no-lead packaging method according to claim 1 or 2, wherein in the step of cutting the encapsulant, only the crucible is cut to the colloid without cutting the pads and The temporary body membrane. The method according to claim 1 or 2, wherein the temporary carrier film is a solder mask dielectric material, and the temporary carrier film has a thickness of not less than One third of the thickness of the metal foil. 11. The array-cut quad flat no-lead packaging method according to claim 1, 2, 3, 4 or 5 of the patent application, further comprising a post-baking step performed after the step of removing the temporary carrier film To completely cure the sealant. t Si 23t Si 23
TW099108433A 2010-03-22 2010-03-22 Packaging method of array-cutting type quad flat non-leaded packages TW201133655A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI575624B (en) * 2015-05-14 2017-03-21 聯發科技股份有限公司 Semiconductor package and fabrication method thereof
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI575624B (en) * 2015-05-14 2017-03-21 聯發科技股份有限公司 Semiconductor package and fabrication method thereof
US9842831B2 (en) 2015-05-14 2017-12-12 Mediatek Inc. Semiconductor package and fabrication method thereof
US10340259B2 (en) 2015-05-14 2019-07-02 Mediatek Inc. Method for fabricating a semiconductor package
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof

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