US20160307831A1 - Method of making a qfn package - Google Patents

Method of making a qfn package Download PDF

Info

Publication number
US20160307831A1
US20160307831A1 US15/194,254 US201615194254A US2016307831A1 US 20160307831 A1 US20160307831 A1 US 20160307831A1 US 201615194254 A US201615194254 A US 201615194254A US 2016307831 A1 US2016307831 A1 US 2016307831A1
Authority
US
United States
Prior art keywords
leads
film layer
assembly
die
qfn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/194,254
Inventor
Dan Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US15/194,254 priority Critical patent/US20160307831A1/en
Publication of US20160307831A1 publication Critical patent/US20160307831A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Definitions

  • a leadframe strip containing multiple connected leadframes has multiple semiconductor dies mounted on it.
  • This assembly is sealed with mold compound resins.
  • the sealed assembly is diced (singulated) to form individual QFN packages.
  • a saw with a rotating blade is moved along preset cutting lines across the sealed assembly. Both mold compound and leadframe metal are cut in the dicing process.
  • a method of making a plated leadframe comprises forming a first film layer on a first side of a metal plate; forming a second film layer on a second side of the metal plate opposite the first side; and etching the first film layer in a predetermined pattern that exposes portions of the first side of the metal plate.
  • a QFN comprises an encapsulant block having opposite top and bottom surfaces and a plurality of side surfaces, wherein only the bottom surface comprises exposed metal surfaces.
  • FIG. 1 is a schematic side elevation view of a first assembly created in an initial stage of integrated circuit (“IC”) package formation.
  • IC integrated circuit
  • FIG. 2 is a side elevation view of the assembly of FIG. 1 showing a photo-mask applied thereto.
  • FIG. 3 is a side elevation view of the assembly of FIG. 2 after photo etching.
  • FIG. 4 is a side elevation view of the assembly of FIG. 3 showing chemical etching of a metal layer.
  • FIG. 5 is a side elevation view of the assembly of FIG. 4 after chemical etching.
  • FIG. 6 is a side elevation view of the assembly FIG. 5 after removal of portions of a first film layer.
  • FIG. 7 is a cross-sectional side elevation view of the assembly FIG. 6 showing metal plating of remaining metal portions thereof.
  • FIG. 8 is a cross-sectional side elevation view of the assembly of FIG. 7 after metal plating.
  • FIG. 9 is a cross-sectional side elevation view of the assembly FIG. 8 after application of a tape player to the plated metal portions thereof.
  • FIG. 10 is a cross-sectional side elevation view of the assembly FIG. 9 after removal of a second film layer there from.
  • FIG. 11 is a cross-sectional side elevation view of the assembly of FIG. 10 illustrating metal plating of unplated surfaces of two metal portions to form two plated leads.
  • FIG. 12 is a cross-sectional side elevation view of the assembly of FIG. 11 illustrating two plated leads formed by the operation of FIG. 11 .
  • FIG. 13 is a cross-sectional side elevation view of the assembly of FIG. 12 after mounting of a die thereon.
  • FIG. 14 is an expanded top plan view of the assembly illustrated in FIG. 13 showing additional plated leads.
  • FIG. 15 is a cross-sectional side elevation view of the assembly of FIG. 13 after wire bonding of the die to adjacent plated leads.
  • FIG. 16 is a cross-sectional side elevation view of the assembly of FIG. 15 after encapsulation thereof in mold compound.
  • FIG. 17 is a cross-sectional side elevation view of the assembly FIG. 16 showing removal of a second film layer therefrom.
  • FIG. 18 is a cross-sectional side elevation view of a larger portion of the assembly shown in FIG. 17 after removal of the film layer therefrom and showing dicing cuts made thereto.
  • FIG. 19 is a top plan view of one integrated circuit package singulated from the assembly shown in FIG. 18 .
  • FIG. 20 is a bottom plan view of the integrated circuit package illustrated in FIG. 19 .
  • FIG. 21 is a top plan view of a prior art leadframe sheet showing the position of saw streets.
  • FIG. 22 is a top plan view of a leadframe sheet of the type illustrated in FIG. 14 showing the position of saw streets.
  • FIG. 23 is a flow chart of an example embodiment of a method of making a plated leadframe.
  • FIG. 24 is a flowchart of an example embodiment of a method of making a plurality of QFN's.
  • FIG. 25 is a flowchart of an example embodiment of a method of making a flat no lead package.
  • FIGS. 1-20 schematically illustrate various stages in the formation of a leadless integrated circuit package, such as, for example, a QFN (Quad Flat No Lead integrated circuit package).
  • a leadless integrated circuit package such as, for example, a QFN (Quad Flat No Lead integrated circuit package).
  • FIG. 1 is a schematic side elevation view of a first assembly created in an initial stage of integrated circuit package formation.
  • a metal plate 110 has a first dry film 120 and a second dry film 130 laminated to it.
  • the metal plate 110 may be, for example, a thin, e.g. 200 um (100 um ⁇ 500 um) copper, gold or aluminum plate 110 , from which leads of a leadframe are to be formed.
  • the dry film layers may be thin, for example 25 um, and the films may be made from, for example, binder polymer (acrylic or styrene), monomer and photoinitiator.
  • the film layers may be laminated to the metal layer by conventional lamination processes.
  • the metal plate 110 has a first side 112 and an opposite second side 114 .
  • the first dry film layer 120 having a first side 122 and an opposite second side 124 is laminated to the plate 110 , with the second side 124 of the first dry film layer 120 in contact with the first side 112 of the plate 110 .
  • the second dry film 130 has a first side 132 and an opposite second side 134 , with the first side 132 of the second film layer engaging the second side 114 of the metal plate 110 .
  • a photo-mask 140 having opaque portions 142 , 144 is positioned over the first film layer 120 .
  • Light 146 is applied to the first film layer 120 through openings 141 , 143 , 145 , etc. in the mask 140 to photo etch exposed portions 152 , 154 , 156 of the first film layer 120 .
  • FIG. 3 illustrates the assembly of FIG. 2 after photo-etching. Only portions 158 and 160 of the first dry film layer 120 remain.
  • FIG. 4 illustrates etching of the metal plate 110 through open portions 162 , 164 , 166 with etching chemicals 170 .
  • FIG. 5 illustrates the assembly of FIG. 4 after chemical etching. All portions of the metal plate 110 , FIG. 1 , have been etched away except for portions 172 and 174 positioned beneath first film layer portions 158 , 160 .
  • FIG. 6 illustrates the assembly of FIG. 4 after removal of first film layer portions 158 , 160 , as by use of conventional film stripping processes.
  • the only portions of the original assembly that remain are the second dry film layer 130 and metal sheet 110 portions 172 , 174 , which are now referred to as leads 172 , 174 .
  • the metal portions or leads 172 , 174 have first sides 112 A and 1126 , respectively, corresponding to the first side 112 of the metal plate 110 , FIG. 1 .
  • the leads 172 and 174 have bottom sides 114 A and 1146 , respectively, corresponding to the second side 114 of the metal plate 110 .
  • the lead portions of the assembly of FIG. 6 are plated with plating material 176 , for example with nickel, lead, gold or some combination thereof.
  • This plating may be performed by conventional plating process, such as by electrolytic Ni/Pd/Au plating or electrolytic tin plating
  • FIG. 8 shows the second film layer 130 with leads 172 , 174 having plating layers 178 , 180 applied thereto.
  • the plating layer 178 has a (top) surface 182 and two lateral side surfaces 184 , 186 .
  • the plating layer 180 has a (top) surface 192 and lateral side surfaces 194 , 196 .
  • a tape 210 having a first smooth/nonadhesive surface 212 and a second tacky/adhesive surface 214 .
  • the tape 210 is attached, adhesive surface 214 down, to the top plated surfaces 182 , 192 of the leads 172 , 174 .
  • the dry film layer 130 is removed, leaving surfaces 114 A of lead 172 and 1146 of the lead 174 exposed.
  • FIG. 11 illustrates the assembly of FIG. 10 in a flipped over position and shows application of a mask 222 to the leads 172 , 174 .
  • the mask 222 has openings 218 and 220 therein aligned with surfaces 114 A and 114 B of the leads 172 , 174 .
  • Plating material 216 is applied through the openings, such that surfaces 114 A and 1146 are coated with plating layers 224 and 226 , respectively, as shown in FIG. 12 .
  • the leads 172 , 174 thus plated, are now referred to as plated leads 234 , 236 . This essentially completes the lead formation process.
  • FIG. 14 is a top plan view of a larger portion of this overall assembly. As shown by FIG. 14 the die 250 is positioned at the center of a plurality of surrounding leads designated 230 , collectively. In the illustrated embodiment of FIG. 14 , only the leads that are directly adjacent to the die 250 form part of the leadframe associated with die 250 . In other embodiments other leads positioned outwardly of the leads 230 may be associated with the die 250 . In the embodiment of FIG. 14 , leads 240 positioned outwardly of the leads 230 are associated with other leadframes which surround other dies that may be identical to die 250 .
  • FIG. 15 again, illustrates only a portion of the entire leadframe and die assembly being formed. It may be seen from FIG. 15 that the die 250 has an active circuit side 252 positioned upwardly in the drawing, and a backside 254 , which is attached to the adhesive surface 214 of tape 210 .
  • bond wires 262 , 264 attach electrical contacts (not shown) on surface 252 of the die 250 to the plated surfaces 224 , 226 of plated leads 234 , 236 , as by use of conventional wire bonding processes.
  • FIG. 16 is a cross sectional elevation view of the assembly of FIG. 15 , after application of a layer of mold compound 270 thereto.
  • Mold compound 270 has a top surface 272 and a bottom surface 274 .
  • the bottom surface 274 interfaces with the adhesive side 214 of the tape 210 .
  • the mold compound 270 may be applied using conventional processes, such as, for example, through use of a transfer mold.
  • FIG. 18 is a side elevation view of a larger portion of the die/lead/mold block assembly shown in FIG. 17 that illustrates singulated portions 282 , 284 and as yet unsingulated portions 286 , 288 , of the assembly, which are being formed into individual integrated circuit packages 282 , 284 . As discussed in greater detail with respect to FIG. 22 , none of the cuts 281 , 283 extend through metal.
  • FIG. 19 is a top plan view and FIG. 20 is a bottom plan view of one integrated circuit package 284 formed by singulating the mold block 270 .
  • no portions of the die 250 leads 230 or bond wires 262 , 264 , etc., are exposed at the top surface 272 .
  • the bottom surface 254 of the die 250 and the bottom plated portions of the leads 230 are exposed at the bottom surface 274 of the block of mold compound 270 .
  • FIG. 22 is a top plan view of a portion of the block of mold compound 270 .
  • the mold compound in this view is transparent to show the positions of the die and leads.
  • the portion of the mold compound 270 shown in FIG. 22 corresponds to the portion of the unmolded assembly shown in FIG. 14 .
  • the cut lines or “saw streets” 281 , 283 , 285 , 287 do not intersect any of the leads 230 , 240 , although, in the case of saw streets 285 , 287 , the saw streets pass close to end portions of the leads 230 , 240 . Since the saw streets do not pass through any metal, no metal is cut during singulation and therefore no metal burrs are created using applicant's IC forming method.
  • FIG. 21 illustrates saw cutting operations of the prior art.
  • a mold compound encapsulated conventional leadframe sheet 290 (in which the mold compound is transparent for illustrative purposes) is severed along a plurality of saw streets 292 , 294 , 296 , 298 to form a plurality integrated circuits having corresponding leadframes 302 , 304 , 306 , etc.
  • Each leadframe 302 , 304 , 306 , etc. comprises a centrally mounted die pad 312 (only one shown) connected by tie bars 314 to support strips 320 , 322 .
  • Each leadframe also comprises a plurality of leads 317 , 316 , 318 , etc.
  • the saw streets 292 , 294 , 296 , 298 extend through end portions of the leads 316 , 318 and end portions of the tie bars 314 of each leadframe 302 , 304 , 306 , etc. that is formed.
  • Singulation sawing severs portions of each lead 316 , often creating metal burrs and copper smearing in the process. Such metal burrs and copper smears are undesirable because they may cause shorting of adjacent leads, as well as producing other surface mount (SMT) issues.
  • SMT surface mount
  • a considerable amount of scrap, associated with the support strips 320 , 322 and tie bars 314 is produced by this prior art process.
  • Metal sawing also dulls saw blades more quickly than sawing through mold compound. Thus, sawing operations must be stopped for saw blade replacement much more often during prior art sawing operations than in the sawing operations shown in FIG. 22 . Replacement of saw blades adds to the overall expense of QFN and similar semiconductor package fabrication processes.
  • a die (not shown) is attached to the die pad 312 by an adhesive compound or solder. In either case, heat escaping from the bottom surface of the die must pass through both this attachment layer and the die pad 312 .
  • the die 250 is supported within the QFN or related integrated circuit package 284 without a die pad. Thus heat from the die 250 is dissipated more efficiently than in the prior art embodiments, such as shown in FIG. 21 , because there is nothing positioned between the die backside surface 254 and a printed circuit board (not shown), or the like, on which the die 250 is mounted.
  • a method of making a plated leadframe may include, as shown at block 402 , providing a first dry film layer on a first side of a metal plate.
  • the method may also include, as shown at block 404 providing a second dry film layer on a second side of the metal plate opposite the first side.
  • the method may further include, as shown at block 406 , photo etching the first dry film layer in a predetermined pattern that exposes portions of the first side of the metal plate.
  • a method of making a plurality of integrated circuit packages may include, as shown at block 422 , laminating a first dry film layer on a first side of a metal plate. The method may also include as shown at block 424 , laminating a second dry film layer on an opposite second side of the metal plate and, as shown at block 426 photo etching the first dry film layer in a predetermined pattern.
  • a method of making a flat no lead package may include, as shown at block 442 , attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and, as shown at block 444 , attaching a first die to the tape at a predetermined position within the predetermined lead pattern.

Abstract

A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and attaching a first die to the tape at a predetermined position within the predetermined lead pattern.

Description

  • This application is related to U.S. patent application Ser. No. 14/301,942, filed Jun. 11, 2014, entitled QUAD FLAT NO LEAD PACKAGE AND METHOD OF MAKING of Okamoto, et al., which is hereby incorporated by reference for all that it discloses.
    • BACKGROUND
  • Accompanying the popularization of cell phones, notebook personal computers, and other small electronic devices has been a great demand to reduce the size and thickness of the semiconductor devices carried in them. Together with BGA (Ball Grid Array) packages and SON (Small Outline Non-leaded) packages, QFN (Quad Flat No lead) packages have become a popular configuration for small integrated circuit (“IC”) packages with leadframes.
  • In QFN package formation, a leadframe strip containing multiple connected leadframes has multiple semiconductor dies mounted on it. This assembly is sealed with mold compound resins. The sealed assembly is diced (singulated) to form individual QFN packages. During dicing, a saw with a rotating blade, is moved along preset cutting lines across the sealed assembly. Both mold compound and leadframe metal are cut in the dicing process.
    • SUMMARY
  • A method of making a plated leadframe comprises forming a first film layer on a first side of a metal plate; forming a second film layer on a second side of the metal plate opposite the first side; and etching the first film layer in a predetermined pattern that exposes portions of the first side of the metal plate.
  • A QFN comprises an encapsulant block having opposite top and bottom surfaces and a plurality of side surfaces, wherein only the bottom surface comprises exposed metal surfaces.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic side elevation view of a first assembly created in an initial stage of integrated circuit (“IC”) package formation.
  • FIG. 2 is a side elevation view of the assembly of FIG. 1 showing a photo-mask applied thereto.
  • FIG. 3 is a side elevation view of the assembly of FIG. 2 after photo etching.
  • FIG. 4 is a side elevation view of the assembly of FIG. 3 showing chemical etching of a metal layer.
  • FIG. 5 is a side elevation view of the assembly of FIG. 4 after chemical etching.
  • FIG. 6 is a side elevation view of the assembly FIG. 5 after removal of portions of a first film layer.
  • FIG. 7 is a cross-sectional side elevation view of the assembly FIG. 6 showing metal plating of remaining metal portions thereof.
  • FIG. 8 is a cross-sectional side elevation view of the assembly of FIG. 7 after metal plating.
  • FIG. 9 is a cross-sectional side elevation view of the assembly FIG. 8 after application of a tape player to the plated metal portions thereof.
  • FIG. 10 is a cross-sectional side elevation view of the assembly FIG. 9 after removal of a second film layer there from.
  • FIG. 11 is a cross-sectional side elevation view of the assembly of FIG. 10 illustrating metal plating of unplated surfaces of two metal portions to form two plated leads.
  • FIG. 12 is a cross-sectional side elevation view of the assembly of FIG. 11 illustrating two plated leads formed by the operation of FIG. 11.
  • FIG. 13 is a cross-sectional side elevation view of the assembly of FIG. 12 after mounting of a die thereon.
  • FIG. 14 is an expanded top plan view of the assembly illustrated in FIG. 13 showing additional plated leads.
  • FIG. 15 is a cross-sectional side elevation view of the assembly of FIG. 13 after wire bonding of the die to adjacent plated leads.
  • FIG. 16 is a cross-sectional side elevation view of the assembly of FIG. 15 after encapsulation thereof in mold compound.
  • FIG. 17 is a cross-sectional side elevation view of the assembly FIG. 16 showing removal of a second film layer therefrom.
  • FIG. 18 is a cross-sectional side elevation view of a larger portion of the assembly shown in FIG. 17 after removal of the film layer therefrom and showing dicing cuts made thereto.
  • FIG. 19 is a top plan view of one integrated circuit package singulated from the assembly shown in FIG. 18.
  • FIG. 20 is a bottom plan view of the integrated circuit package illustrated in FIG. 19.
  • FIG. 21 is a top plan view of a prior art leadframe sheet showing the position of saw streets.
  • FIG. 22 is a top plan view of a leadframe sheet of the type illustrated in FIG. 14 showing the position of saw streets.
  • FIG. 23 is a flow chart of an example embodiment of a method of making a plated leadframe.
  • FIG. 24 is a flowchart of an example embodiment of a method of making a plurality of QFN's.
  • FIG. 25 is a flowchart of an example embodiment of a method of making a flat no lead package.
    •  DETAILED DESCRIPTION
  • FIGS. 1-20 schematically illustrate various stages in the formation of a leadless integrated circuit package, such as, for example, a QFN (Quad Flat No Lead integrated circuit package).
  • FIG. 1 is a schematic side elevation view of a first assembly created in an initial stage of integrated circuit package formation. A metal plate 110 has a first dry film 120 and a second dry film 130 laminated to it. The metal plate 110 may be, for example, a thin, e.g. 200 um (100 um˜500 um) copper, gold or aluminum plate 110, from which leads of a leadframe are to be formed. The dry film layers may be thin, for example 25 um, and the films may be made from, for example, binder polymer (acrylic or styrene), monomer and photoinitiator. The film layers may be laminated to the metal layer by conventional lamination processes. The metal plate 110 has a first side 112 and an opposite second side 114. The first dry film layer 120 having a first side 122 and an opposite second side 124 is laminated to the plate 110, with the second side 124 of the first dry film layer 120 in contact with the first side 112 of the plate 110. The second dry film 130 has a first side 132 and an opposite second side 134, with the first side 132 of the second film layer engaging the second side 114 of the metal plate 110.
  • In FIG. 2, a photo-mask 140 having opaque portions 142, 144 is positioned over the first film layer 120. Light 146 is applied to the first film layer 120 through openings 141, 143, 145, etc. in the mask 140 to photo etch exposed portions 152, 154, 156 of the first film layer 120.
  • FIG. 3 illustrates the assembly of FIG. 2 after photo-etching. Only portions 158 and 160 of the first dry film layer 120 remain.
  • FIG. 4 illustrates etching of the metal plate 110 through open portions 162, 164, 166 with etching chemicals 170.
  • FIG. 5 illustrates the assembly of FIG. 4 after chemical etching. All portions of the metal plate 110, FIG. 1, have been etched away except for portions 172 and 174 positioned beneath first film layer portions 158, 160.
  • FIG. 6 illustrates the assembly of FIG. 4 after removal of first film layer portions 158, 160, as by use of conventional film stripping processes. As illustrated by FIG. 6, after removal of the first film layer portions 158, 160, the only portions of the original assembly that remain are the second dry film layer 130 and metal sheet 110 portions 172, 174, which are now referred to as leads 172, 174. The metal portions or leads 172, 174 have first sides 112A and 1126, respectively, corresponding to the first side 112 of the metal plate 110, FIG. 1. The leads 172 and 174 have bottom sides 114A and 1146, respectively, corresponding to the second side 114 of the metal plate 110.
  • As illustrated by FIG. 7, the lead portions of the assembly of FIG. 6 are plated with plating material 176, for example with nickel, lead, gold or some combination thereof. This plating may be performed by conventional plating process, such as by electrolytic Ni/Pd/Au plating or electrolytic tin plating
  • FIG. 8 shows the second film layer 130 with leads 172, 174 having plating layers 178, 180 applied thereto. The plating layer 178 has a (top) surface 182 and two lateral side surfaces 184, 186. The plating layer 180 has a (top) surface 192 and lateral side surfaces 194, 196.
  • As illustrated by FIG. 9, a tape 210 having a first smooth/nonadhesive surface 212 and a second tacky/adhesive surface 214. The tape 210 is attached, adhesive surface 214 down, to the top plated surfaces 182, 192 of the leads 172, 174.
  • Next, as illustrated in FIG. 10, the dry film layer 130 is removed, leaving surfaces 114A of lead 172 and 1146 of the lead 174 exposed.
  • FIG. 11 illustrates the assembly of FIG. 10 in a flipped over position and shows application of a mask 222 to the leads 172, 174. The mask 222 has openings 218 and 220 therein aligned with surfaces 114A and 114B of the leads 172, 174. Plating material 216 is applied through the openings, such that surfaces 114A and 1146 are coated with plating layers 224 and 226, respectively, as shown in FIG. 12. The leads 172, 174, thus plated, are now referred to as plated leads 234, 236. This essentially completes the lead formation process.
  • Next, as illustrated in FIG. 13, an integrated circuit die 250 is mounted on the tape 210 between the plated leads 234, 236. The drawings, to this point have illustrated only a small region of a larger assembly, which comprises a plurality of leadframes. FIG. 14 is a top plan view of a larger portion of this overall assembly. As shown by FIG. 14 the die 250 is positioned at the center of a plurality of surrounding leads designated 230, collectively. In the illustrated embodiment of FIG. 14, only the leads that are directly adjacent to the die 250 form part of the leadframe associated with die 250. In other embodiments other leads positioned outwardly of the leads 230 may be associated with the die 250. In the embodiment of FIG. 14, leads 240 positioned outwardly of the leads 230 are associated with other leadframes which surround other dies that may be identical to die 250.
  • FIG. 15, again, illustrates only a portion of the entire leadframe and die assembly being formed. It may be seen from FIG. 15 that the die 250 has an active circuit side 252 positioned upwardly in the drawing, and a backside 254, which is attached to the adhesive surface 214 of tape 210. In FIG. 15, bond wires 262, 264 attach electrical contacts (not shown) on surface 252 of the die 250 to the plated surfaces 224, 226 of plated leads 234, 236, as by use of conventional wire bonding processes.
  • FIG. 16 is a cross sectional elevation view of the assembly of FIG. 15, after application of a layer of mold compound 270 thereto. Mold compound 270 has a top surface 272 and a bottom surface 274. The bottom surface 274 interfaces with the adhesive side 214 of the tape 210. The mold compound 270 may be applied using conventional processes, such as, for example, through use of a transfer mold.
  • FIG. 18 is a side elevation view of a larger portion of the die/lead/mold block assembly shown in FIG. 17 that illustrates singulated portions 282, 284 and as yet unsingulated portions 286, 288, of the assembly, which are being formed into individual integrated circuit packages 282, 284. As discussed in greater detail with respect to FIG. 22, none of the cuts 281, 283 extend through metal.
  • FIG. 19 is a top plan view and FIG. 20 is a bottom plan view of one integrated circuit package 284 formed by singulating the mold block 270. As illustrated in FIG. 19 no portions of the die 250, leads 230 or bond wires 262, 264, etc., are exposed at the top surface 272. As illustrated in FIG. 20, the bottom surface 254 of the die 250 and the bottom plated portions of the leads 230 are exposed at the bottom surface 274 of the block of mold compound 270.
  • FIG. 22 is a top plan view of a portion of the block of mold compound 270. The mold compound in this view is transparent to show the positions of the die and leads. The portion of the mold compound 270 shown in FIG. 22 corresponds to the portion of the unmolded assembly shown in FIG. 14.
  • As shown by FIG. 22 the cut lines or “saw streets” 281, 283, 285, 287 do not intersect any of the leads 230, 240, although, in the case of saw streets 285, 287, the saw streets pass close to end portions of the leads 230, 240. Since the saw streets do not pass through any metal, no metal is cut during singulation and therefore no metal burrs are created using applicant's IC forming method.
  • FIG. 21 illustrates saw cutting operations of the prior art. A mold compound encapsulated conventional leadframe sheet 290 (in which the mold compound is transparent for illustrative purposes) is severed along a plurality of saw streets 292, 294, 296, 298 to form a plurality integrated circuits having corresponding leadframes 302, 304, 306, etc. Each leadframe 302, 304, 306, etc., comprises a centrally mounted die pad 312 (only one shown) connected by tie bars 314 to support strips 320, 322. Each leadframe also comprises a plurality of leads 317, 316, 318, etc. The saw streets 292, 294, 296, 298 extend through end portions of the leads 316, 318 and end portions of the tie bars 314 of each leadframe 302, 304, 306, etc. that is formed. Singulation sawing severs portions of each lead 316, often creating metal burrs and copper smearing in the process. Such metal burrs and copper smears are undesirable because they may cause shorting of adjacent leads, as well as producing other surface mount (SMT) issues. Also, a considerable amount of scrap, associated with the support strips 320, 322 and tie bars 314, is produced by this prior art process. Metal sawing also dulls saw blades more quickly than sawing through mold compound. Thus, sawing operations must be stopped for saw blade replacement much more often during prior art sawing operations than in the sawing operations shown in FIG. 22. Replacement of saw blades adds to the overall expense of QFN and similar semiconductor package fabrication processes.
  • In QFNs formed as shown in FIG. 21, a die (not shown) is attached to the die pad 312 by an adhesive compound or solder. In either case, heat escaping from the bottom surface of the die must pass through both this attachment layer and the die pad 312. In the integrated circuit packages formed as shown in FIGS. 1-20, the die 250 is supported within the QFN or related integrated circuit package 284 without a die pad. Thus heat from the die 250 is dissipated more efficiently than in the prior art embodiments, such as shown in FIG. 21, because there is nothing positioned between the die backside surface 254 and a printed circuit board (not shown), or the like, on which the die 250 is mounted.
  • As shown by FIG. 23, a method of making a plated leadframe may include, as shown at block 402, providing a first dry film layer on a first side of a metal plate. The method may also include, as shown at block 404 providing a second dry film layer on a second side of the metal plate opposite the first side. The method may further include, as shown at block 406, photo etching the first dry film layer in a predetermined pattern that exposes portions of the first side of the metal plate.
  • As shown by FIG. 24, a method of making a plurality of integrated circuit packages may include, as shown at block 422, laminating a first dry film layer on a first side of a metal plate. The method may also include as shown at block 424, laminating a second dry film layer on an opposite second side of the metal plate and, as shown at block 426 photo etching the first dry film layer in a predetermined pattern.
  • As shown by FIG. 25, a method of making a flat no lead package may include, as shown at block 442, attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and, as shown at block 444, attaching a first die to the tape at a predetermined position within the predetermined lead pattern.
  • Although embodiments of certain example embodiments of methods of making integrated circuit packages and associated leadframes and example embodiments of integrated circuit package devices have been described herein in detail, alternative embodiments of such methods and devices will become obvious to those skilled in the art after reading this disclosure. The language of the appended claims is intended to be broadly construed to cover such alternative embodiments, except as limited by the prior art.

Claims (10)

1. A method of making a plated leadframe comprising:
providing a first film layer on a first side of a metal plate;
providing a second film layer on a second side of the metal plate opposite the first side; and
photo etching the first film layer in a predetermined pattern that exposes portions of the first side of the metal plate.
2. The method of claim 1 further comprising chemical etching the exposed portions of the first side of the metal plate to produce a plurality of leads.
3. The method of claim 2, further comprising:
removing the first film layer from the plurality of leads; and
plating first side surfaces of the plurality of leads.
4. The method of claim 3, further comprising:
applying an adhesive tape to the plated first side surfaces of the plurality of leads;
removing the second film layer from the second side surfaces of the plurality of leads; and
plating the second side surfaces of the plurality of leads.
5-17. (canceled)
18. A QFN comprising:
an encapsulant block having opposite top and bottom surfaces and a plurality of side surfaces, wherein only said bottom surface comprises exposed metal surfaces.
19. The QFN of claim 18 wherein said exposed metal surfaces on said bottom surface of said encapsulant block comprise plated lead surfaces.
20. The QFN of claim 18 wherein said exposed metal surfaces on said bottom surface of said encapsulant block comprise a die backside surface.
21. A QFN comprising:
an encapsulant block having opposite top and bottom surfaces; and
a die having a backside surface exposed at said bottom surface of said encapsulation block.
22. The QFN of claim 21 wherein said encapsulant bottom surface and said die backside surface are coplanar.
US15/194,254 2014-11-07 2016-06-27 Method of making a qfn package Abandoned US20160307831A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/194,254 US20160307831A1 (en) 2014-11-07 2016-06-27 Method of making a qfn package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/535,939 US9379087B2 (en) 2014-11-07 2014-11-07 Method of making a QFN package
US15/194,254 US20160307831A1 (en) 2014-11-07 2016-06-27 Method of making a qfn package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US14/535,939 Continuation US9379087B2 (en) 2014-11-07 2014-11-07 Method of making a QFN package

Publications (1)

Publication Number Publication Date
US20160307831A1 true US20160307831A1 (en) 2016-10-20

Family

ID=55912859

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/535,939 Active 2034-11-22 US9379087B2 (en) 2014-11-07 2014-11-07 Method of making a QFN package
US15/194,254 Abandoned US20160307831A1 (en) 2014-11-07 2016-06-27 Method of making a qfn package

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US14/535,939 Active 2034-11-22 US9379087B2 (en) 2014-11-07 2014-11-07 Method of making a QFN package

Country Status (1)

Country Link
US (2) US9379087B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465418B (en) * 2014-12-24 2017-12-19 通富微电子股份有限公司 A kind of fan-out wafer level packaging methods
US9978613B1 (en) 2017-03-07 2018-05-22 Texas Instruments Incorporated Method for making lead frames for integrated circuit packages
FR3083920A1 (en) * 2018-07-13 2020-01-17 Linxens Holding METHOD FOR MANUFACTURING ELECTRONIC COMPONENT PACKAGES AND ELECTRONIC COMPONENT PACKAGE OBTAINED BY THIS PROCESS

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130241041A1 (en) * 2012-03-15 2013-09-19 Lin-Wang YU Semiconductor packages with lead extensions and related methods
US20140070391A1 (en) * 2012-09-07 2014-03-13 Eoplex Limited Lead carrier with print-formed terminal pads

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG111919A1 (en) * 2001-08-29 2005-06-29 Micron Technology Inc Packaged microelectronic devices and methods of forming same
JP2003078094A (en) * 2001-08-31 2003-03-14 Shinko Electric Ind Co Ltd Lead frame and manufacturing method therefor, and manufacturing method of semiconductor device using the same
US7709935B2 (en) * 2003-08-26 2010-05-04 Unisem (Mauritius) Holdings Limited Reversible leadless package and methods of making and using same
US7169651B2 (en) * 2004-08-11 2007-01-30 Advanced Semiconductor Engineering, Inc. Process and lead frame for making leadless semiconductor packages
US9263315B2 (en) * 2010-03-30 2016-02-16 Dai Nippon Printing Co., Ltd. LED leadframe or LED substrate, semiconductor device, and method for manufacturing LED leadframe or LED substrate
TW201250964A (en) * 2011-01-27 2012-12-16 Dainippon Printing Co Ltd Resin-attached lead frame, method for manufacturing same, and lead frame
ITMI20130654A1 (en) * 2013-04-22 2014-10-23 St Microelectronics Srl ELECTRONIC ASSEMBLY FOR MOUNTING ON ELECTRONIC BOARD

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130241041A1 (en) * 2012-03-15 2013-09-19 Lin-Wang YU Semiconductor packages with lead extensions and related methods
US20140070391A1 (en) * 2012-09-07 2014-03-13 Eoplex Limited Lead carrier with print-formed terminal pads

Also Published As

Publication number Publication date
US20160133599A1 (en) 2016-05-12
US9379087B2 (en) 2016-06-28

Similar Documents

Publication Publication Date Title
US7439097B2 (en) Taped lead frames and methods of making and using the same in semiconductor packaging
TW498443B (en) Singulation method for manufacturing multiple lead-free semiconductor packages
US7790500B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US9136247B2 (en) Resin-encapsulated semiconductor device and method of manufacturing the same
US7972906B2 (en) Semiconductor die package including exposed connections
US20030045032A1 (en) Leadframe, method of manufacturing the same, semiconductor device using the same, and method of manufacturing the device
US20120326288A1 (en) Method of assembling semiconductor device
US9842794B2 (en) Semiconductor package with integrated heatsink
TWI274409B (en) Process for manufacturing sawing type leadless semiconductor packages
US20120043660A1 (en) Thin foil semiconductor package
US9324642B2 (en) Method of electrically isolating shared leads of a lead frame strip
JP2008218469A (en) Manufacturing method of semiconductor device
US11735435B2 (en) Quad flat no lead package and method of making
US20160307831A1 (en) Method of making a qfn package
US11721654B2 (en) Ultra-thin multichip power devices
US9806006B2 (en) Etch isolation LPCC/QFN strip
JP2006245459A (en) Manufacturing method of semiconductor device
JP4418764B2 (en) Manufacturing method of resin-encapsulated semiconductor package
JP2002033345A (en) Method for manufacturing resin-sealed semiconductor device
US9287238B2 (en) Leadless semiconductor package with optical inspection feature
CN110383471B (en) Method for manufacturing lead frame for integrated circuit package
JP3600137B2 (en) Circuit device manufacturing method
TWI237357B (en) Singulation method used in leadless packaging process
JP2004266195A (en) Manufacturing method for semiconductor package
JP2004095936A (en) Manufacturing method of circuit device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION