CN209282194U - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN209282194U
CN209282194U CN201822152564.3U CN201822152564U CN209282194U CN 209282194 U CN209282194 U CN 209282194U CN 201822152564 U CN201822152564 U CN 201822152564U CN 209282194 U CN209282194 U CN 209282194U
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contact
substrate
ridge
semiconductor devices
sealant
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达雷尔·D·楚伊特
詹姆斯·P·小莱特曼
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Semiconductor Components Industries LLC
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Abstract

本实用新型涉及半导体器件。本实用新型提供了一种具有可润湿侧翼的无引线封装,所述无引线封装通过以下方式来形成:提供衬底,并且将金属层镀覆到所述衬底上以在所述衬底上形成触点,所述触点延伸跨过锯道。将密封剂沉积在所述触点上方。移除所述衬底以暴露所述触点和所述密封剂。切割所述密封剂和所述触点。在一些实施方案中,所述衬底包括脊,并且所述触点形成在所述脊上。

Description

半导体器件
本申请是2017年11月15日递交的申请号为201721520684.3,实用新型名称为“半导体器件”的分案申请。
技术领域
本实用新型涉及半导体器件,该半导体器件具有衬底,以及形成在衬底上的触点,该触点延伸跨过衬底的锯道以切割触点。
背景技术
半导体器件在现代电子产品中很常见。电子部件中半导体器件的数量和密度各不相同。半导体器件执行多种多样的功能,诸如模数信号处理、传感器、发送和接收电磁信号、控制电子器件、功率管理以及音频/视频信号处理。分立半导体器件通常包含一种类型的电子部件,例如,发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、二极管、整流器、晶闸管以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包括数百至数百万的电子部件。集成半导体器件的示例包括微控制器、专用集成电路(ASIC)、电源转换、标准逻辑、放大器、时钟管理、存储器、接口电路以及其他信号处理电路。
半导体器件执行多种不同功能,诸如信号处理、高速运算、发送和接收电磁信号、控制电子器件、将太阳光转换成电力以及为电视机显示器生成可视图像。半导体器件存在于娱乐、通信、电源转换、网络、计算机以及消费品领域。半导体器件还存在于军事应用、航空、汽车、工业控制器以及办公设备领域。
半导体器件包含有源电子结构和无源电子结构。有源结构(包括双极和场效应晶体管)控制电流的流动。通过改变掺杂水平以及电场或基极电流的施加,晶体管促进或限制电流的流动。无源结构(包括电阻器、电容器和电感器)产生执行各种电功能所需的电压和电流之间的关系。无源结构和有源结构电连接以形成电路,这使得半导体器件能够执行高速操作和其他有用的功能。
半导体器件一般使用两种复杂的制造工艺来制造,即,前端制造和后端制造,其各自涉及可能数百个步骤。前端制造涉及在半导体晶圆的表面上形成多个管芯。每个半导体管芯通常是相同的并且包含通过电连接有源部件和无源部件而形成的电路。后端制造涉及从成品晶圆切割单独半导体管芯并且封装管芯以提供结构支撑、电互连和环境隔离。如本文使用的术语“半导体管芯”兼指该词语的单数形式和复数形式,并且相应地,可同时涉及单个半导体器件和多个半导体器件。
半导体制造的一个目标是生产较小的半导体器件。较小的设备通常消耗较少的功率,具有更高的性能,并且可以更有效地生产。此外,较小的半导体器件对于使得能够制造较小的最终产品是期望的。通过改进前端工艺可实现较小的半导体器件尺寸,从而产生具有较小、较高密度的有源部件和无源部件的半导体管芯。后端工艺可通过改进电互连和封装材料而产生具有较小占有面积或高度的半导体器件封装。
图1a将常规无引线封装10示为四边扁平无引线(QFN)或双边扁平无引线(DFN)封装。无引线封装10包括设置在引线框26上的半导体管芯24。引线框26由金属衬底形成,其中衬底的材料被移除以产生围绕管芯焊盘26b的多个引线26a。半导体管芯24被设置在管芯焊盘26b上并且包括通过焊丝36耦接到引线26a的接触焊盘。密封剂或模塑化合物40被设置在半导体管芯24和引线框26周围,以用于电隔离并防止污染。
无引线封装10被安装到印刷电路板(PCB)或其他衬底20。焊料50在引线框触点26a和PCB 20上的接触焊盘22之间回流以在无引线封装10和PCB之间形成冶金和电连接。无引线封装10包括用于外部互连的引线26a,其仅仅是从最终封装暴露的金属引线框的部分。使用引线26a代替如在传统半导体封装类型中横向和/或竖直地从封装延伸的引线。在封装10的横向表面上的触点26a的暴露可润湿材料允许焊料50在无引线封装10被安装到PCB 20上之后形成圆角表面52。
圆角52对于电子设备的制造商是有用的,因为半导体管芯24和PCB 20之间的适当互连可由人或者由包括相机和被编程为分析图像的计算机的自动视觉检查设备56视觉地验证。如果视觉检查显示未对引线26a到接触焊盘22的连接之一形成适当的圆角52,则记录特定PCB 20中的错误。如果视觉检查设备56证实无引线封装10和PCB 20之间的每个连接包括适当的圆角52,则制造商可确信封装整体正确地连接到系统。
无引线封装10通过不具有从封装延伸的引线,而是具有保留在封装主体的占有面积内的引线26a来减少在许多现有技术封装上方的PCB 20上所需的占有面积。通过减小引线框的厚度,无引线封装的尺寸已进一步减小。引线框26的衬底材料必须足够厚以在制造工艺期间支撑半导体管芯24。图1b示出具有镀覆引线框66的无引线封装60,该镀覆引线框显著薄于无引线封装10的引线框26。引线框66类似于引线框26,但是通过将引线框镀覆在用于物理支撑的单独牺牲衬底上而形成。
由于来自牺牲衬底的支撑,引线框66不依赖于在形成无引线封装60期间为半导体管芯24提供物理支撑,所以引线框66可被镀覆为相对薄的层。较薄的引线框66产生比无引线封装10更薄的最终无引线封装60。然而,引线框66的减小厚度还导致引线框和密封剂40之间的粘附性的伴随降低。为了增加粘附性,制造商形成不完全延伸到封装60的横向边缘的触点66a。
密封剂40完全围绕镀覆无引线封装中的触点66a,以增加密封剂与无引线触点之间的接触面积和模具锁定。然而,在触点66a没有暴露在无引线封装60的侧翼处的情况下,焊料70不形成当无引线封装被安装在PCB 20上时容易看到的圆角。封装60的侧边不包括用于使焊料70回流到其上的可润湿表面。虽然形成具有镀覆引线框的无引线封装对于可能较小的最终产品产生更薄的半导体封装,但封装的安装不会形成圆角焊料连接。焊料70在无引线封装60和PCB 20之间的所得连接更难以用视觉检查设备56进行验证,并且可能需要诸如x射线设备之类的其他技术来适当地进行验证。
因此,对于使用镀覆引线框来形成无引线封装的方法存在需要,该镀覆引线框也具有可润湿侧翼以形成圆角焊料连接。
实用新型内容
在一个实施方案中,本实用新型是半导体器件,该半导体器件包括衬底,以及形成在衬底上的触点,该触点延伸跨过衬底的锯道以切割触点。
在另一个实施方案中,本实用新型是半导体器件,该半导体器件包括镀覆触点,以及沉积在镀覆触点上方的密封剂,其中镀覆触点暴露在密封剂的侧表面处。
附图说明
图1a-图1b示出无引线半导体封装;
图2a-图2g示出形成具有镀覆引线框和可润湿侧翼的无引线封装;
图3a-图3b示出具有安装在印刷电路板上的可润湿侧翼的无引线封装以及形成圆角的焊料连接;
图4示出适用于无引线封装的各种引线配置;
图5a-图5h示出使用脊状衬底来形成可润湿侧翼;
图6a-图6b示出使用安装在具有圆角焊料连接的PCB上的脊状衬底形成的封装;
图7a-图7b示出形成具有脊状衬底以及在封装的侧表面处暴露的引线的无引线封装;
图8a-图8b示出形成具有衬底的无引线封装,该衬底具有倒圆脊;
图9a-图9b示出形成具有衬底的无引线封装,该衬底具有矩形脊;
图10示出具有用于形成具有可润湿侧翼的无引线封装的蚀刻脊的衬底;并且
图11示出具有用于形成具有可润湿侧翼的无引线封装的沉积脊的衬底。
具体实施方式
下文参照附图描述了一个或多个实施方案,其中类似的数字表示相同或相似的元件。虽然按照实现某些目标的最佳模式描述了附图,但描述旨在涵盖可包括在本公开的实质和范围内的替代形式、修改形式和等同形式。
图2a示出包含牺牲基极材料的载体或牺牲衬底100的一部分的剖视图,该牺牲基极材料诸如硅(Si)、聚合物、氧化铍、玻璃、铜(Cu)、铝(Al)、或用于结构支撑的其他合适的刚性材料。在其他实施方案中,衬底100包括足以支撑引线框的镀覆的柔性材料。衬底100可以是具有用于多个半导体管芯24的容量的圆形或矩形面板。
在图2b中,使用PVD、CVD、电解电镀、化学电镀、或其他合适的金属沉积工艺在衬底100上方形成包括管芯焊盘102和触点104的导电层。导电层102-104包括一层或多层Al、Cu、锡(Sn)、镍(Ni)、金(Au)、银(Ag)、或其他合适的导电材料。在一些实施方案中,掩模层沉积在衬底100上方并且在沉积用于导电层102-104的金属之前使用光刻法进行图案化。在其他实施方案中,金属沉积在衬底100的整个表面上方,然后图案化成触点104和管芯焊盘102。根据需要可使用用于形成管芯焊盘102和触点104的其他添加、半添加减除方法。在一个实施方案中,管芯焊盘102和触点104通过以下方式而形成:沉积薄的Au层,该Au层将在衬底100被移除时暴露;在Au层上方沉积较厚的Ni层;最后在Ni上方沉积薄的Ag层以用于焊线接合。管芯焊盘102和触点104可由可焊接并且能够承受衬底100的移除过程的任何材料或镀覆堆叠形成。在一些实施方案中,将管芯焊盘102和触点104镀覆到60μm的厚度。在其他实施方案中,管芯焊盘102和触点104被镀覆得更厚,例如100μm,以增加与密封剂40的模具锁定并提供增加厚度的可润湿侧翼。
每个接触焊盘104延伸跨过管芯间区域或锯道106。图2c示出作为接触焊盘104a的接触焊盘104的一个实施方案的平面图。每个接触焊盘104a包括由颈部部分110附接的两个接合焊盘108。图2c中的每个接合焊盘108与将设置在两个相邻管芯焊盘102上的不同半导体管芯24相关联。当通过锯道106切割时,每个触点104a的颈部110的一部分在通过切割产生的设备的作为可润湿侧翼的侧边处暴露。肩部112保持嵌入在密封剂40中以增加密封剂40和触点104a之间的模具锁定。
图2d中的触点104b是矩形的,其中触点沿着接触点的长度(包括通过锯道106)具有均匀的宽度。触点104b产生具有与接合焊盘108基本上相同的宽度的可润湿侧翼,而图2c中的触点104a包括减小宽度的可润湿侧翼,因为颈部110通过锯道106比接合焊盘108的宽度更薄。触点104的其他形状用于其他实施方案中。
在图2e中,半导体管芯24使用例如拾取和放置操作设置在管芯焊盘102上。半导体管芯24设置在管芯焊盘102上,其中有源表面30远离载体100取向。接触焊盘32暴露以用于焊线接合到触点104。多个焊丝36形成在衬底100上的触点104与半导体管芯24的接触焊盘32之间。焊丝36通过热压接合、超声波接合、楔形接合、针脚接合、球接合、或其他合适的接合技术而机械耦接和电耦接到触点104和接触焊盘32。焊丝36包括导电材料,诸如Cu、Al、Au、Ag或它们的组合。焊丝36表示将触点104电连接到接触焊盘32的一种类型的互连结构。在另一个实施方案中,导电凸块形成在接触焊盘32上,并且半导体管芯24被倒装芯片接合到不具有管芯焊盘102的触点104上。半导体管芯24可包括二端设备诸如二极管,三端设备诸如晶体管,或具有更多端子的设备。在其他实施方案中,代替或除了半导体管芯24之外,使用分立无源设备或形成在衬底上方的多个集成无源设备。
在图2f中,使用糊剂印刷、压缩模制、传递模制、液体密封剂模制、真空层压、旋涂或其他合适的涂覆器将密封剂或模塑化合物40沉积在半导体管芯24、焊丝36和衬底100上方作为绝缘材料。密封剂40覆盖半导体管芯24的侧表面和有源表面30。密封剂40可为聚合物复合材料,诸如环氧树脂与填料、环氧丙烯酸酯与填料,或者聚合物与合适填料。密封剂40不导电,并且在环境中保护半导体器件免受外部元件和污染物影响。密封剂40还保护半导体管芯24免受因曝光所致的降解的影响。密封剂40、半导体管芯24、管芯焊盘102、触点104和焊丝36组合以形成重构晶圆或面板116。面板116在二维栅格中可包括任何期望数量的半导体管芯24。每个半导体管芯24设置在类似管芯焊盘102上,并且类似触点104在每对相邻的半导体管芯之间延伸。
在图2g中,使用锯片或激光切割工具120通过锯道106切割面板116以形成多个镀覆的无引线封装122。切割通过锯道106暴露触点104的侧表面作为可润湿侧翼124。图3a示出在衬底100通过化学蚀刻、机械剥离、化学机械平面化(CMP)、机械研磨、热烘烤、UV光、激光扫描或湿法脱模移除之后的无引线封装122。在一些实施方案中,将衬底100从密封剂40、管芯焊盘102和触点104移除,然后用切割工具120切割面板。在一个实施方案中,封装122使用Maxell工艺制成,其中衬底100由Al形成并从面板116剥离。在另一个实施方案中,封装122使用LLGA工艺制成,其中衬底100由Cu形成并且通过化学蚀刻移除。
因为每个触点104在面板116中的两个相邻半导体管芯24之间延伸跨过锯道106,所以切割成单独的无引线封装122对于无引线封装的每个触点产生暴露的可润湿侧翼124。移除衬底100暴露每个触点104的底部表面126。在图3b中,无引线封装122设置在PCB 20上方。无引线封装122通过焊料130机械连接和电连接到PCB 20的接触焊盘22。在一个实施方案中,使用蒸发、电解电镀、化学电镀、焊球滴落或丝网印刷工艺通过在无引线封装122的触点104或PCB 20的接触焊盘22上方沉积导电材料来形成焊料130。焊料130的材料可为Al、Sn、Ni、Au、Ag、铅(Pb)、铋(Bi)、Cu、焊料以及它们的组合,且具有任选的焊剂溶体。例如,焊料130可为共熔Sn/Pb、高铅焊料或无铅焊料。
焊料130在无引线封装122的触点104与PCB 20的接触焊盘22之间回流以将半导体管芯24电连接和机械连接到PCB 20。使焊料130回流产生焊料到触点104和接触焊盘22两者的良好连接。当焊料130回流时,将焊料材料润湿到暴露在无引线封装122的横向表面处的触点104的侧翼124上。焊料130的圆角132延伸到封装122的占有面积之外,并且对于视觉检查设备56是可见的。视觉检查设备56用于通过目视检查圆角132来验证焊料130对于每个触点104在封装122和PCB 20之间形成良好的连接。封装122通过使用镀覆引线框而允许相对薄的封装高度,同时还提供用于可目视验证的焊料圆角的可润湿侧翼124。
图4示出无引线封装150的底部表面。无引线封装150类似于无引线封装122,但是包括各种示例性触点配置。封装150包括具有来自图2c的多个触点104a的第一侧表面152。每个触点104a包括从封装150的底部暴露的接合焊盘108,以及从封装150的底部和作为可润湿侧翼的侧表面152暴露的颈部部分110。密封剂40在侧表面152和肩部112之间围绕接合焊盘108延伸以提供触点104a的附加模具锁定,同时仍允许触点的一部分延伸到侧表面152作为可润湿侧翼。虽然示出了触点104a,其中每个触点的中心部分延伸到封装150的侧表面152,但在其他实施方案中,触点104形成有在颈部110的一侧上形成的单个肩部112,或者有围绕单个肩部112的两个颈部110。在其他实施方案中使用具有仅具有延伸到封装的侧表面的焊线接合焊盘的一部分的接合焊盘108的其他配置。
封装150的第二侧表面154包括来自图2d的矩形触点104b。每个触点104b从侧表面154向内朝向管芯焊盘102延伸。尽管无引线封装150的侧边152和154分别被示为具有两个触点104,但是在其他实施方案中,根据需要,在无引线封装的特定侧边上形成零个、一个或多于两个触点。例如,无引线封装150的侧表面156不包括任何引线。在一些实施方案中,通过使无引线封装的两个相对侧边包括具有可润湿侧翼的镀覆引线,而其余两个侧边不包括引线来形成双边扁平无引线封装。在其他实施方案中,通过使具有可润湿侧翼的镀覆引线在封装的四个侧边上,来形成四边扁平无引线封装。镀覆引线104形成在期望的任何形状的半导体封装上的任何数量的侧边上。管芯焊盘102的每个侧边可具有相同或不同的引线配置。
无引线封装150的侧表面158包括单个较大的镀覆引线160。引线160包括三个颈部164,其各自延伸到侧表面158。颈部164允许密封剂40流动到颈部之间的空间中,以改善密封剂到引线160的粘附性。引线160在引线的每个端部处包括肩部168,但是在其他实施方案中,颈部164形成在引线160的端部处。触点160在无引线封装150的侧表面158处产生三个圆角焊料连接,以用于一个电连接。视觉检查设备56是可编程的,以验证在封装150的任何数量的侧边处的任何数量的焊料圆角。
图5a-图5h示出通过使用脊状衬底200形成无引线半导体封装。衬底200类似于来自图2a的衬底100,并且在一些实施方案中由Al或Cu形成。在图5a中,衬底200被放置在压机202中。压机202包括具有凹形凹槽204的上板202a,以及具有对应凸形脊206的下板202b。在图5b中,压机202在衬底200上关闭,并施加力以将衬底的部分成形为脊210。脊210通过在板202a和202b之间按压衬底而被压印到衬底200中。在一些实施方案中,施加热量以有助于在衬底200中形成脊210。
引线框的触点将形成在脊210上,因此脊210形成在其中管芯焊盘将形成在衬底200上的位置的每个侧边上。图5c示出具有围绕每个管芯附接区域216形成的水平和竖直脊210的衬底200a。管芯附接区域216指示衬底200上的管芯焊盘将被镀覆的位置。焊线接合焊盘将部分地形成在区域216中并且延伸到脊210上。如图5c所示,设置在区域216中的半导体管芯24将由脊210包围在四个侧边上,从而导致可润湿侧翼形成在管芯的四个侧边上。图5d示出具有仅以单个方向取向的脊210的衬底200b。设置在衬底200b的区域216中的半导体管芯将在管芯的两个相对侧边上具有脊210,从而产生在管芯的两个侧边上的可润湿侧翼。在另一个实施方案中,两个管芯设置在图5d的脊210之间,并且每个管芯在仅一个侧边上具有脊。虽然脊210被示为延伸衬底200的整个长度或宽度,但其他实施方案在其中期望具有可润湿侧翼的引线的特定位置处具有多个脊210。
图5e示出具有形成在衬底上方的触点220和管芯焊盘222的衬底200的一部分的剖视图。管芯焊盘222和触点220类似于管芯焊盘102和触点104。管芯焊盘222形成在衬底200的管芯附接区域216内。每个触点220部分地在脊210之上延伸到侧翼锯道212。在图5f中,半导体管芯24设置在管芯焊盘222上,并且接触焊盘32通过焊线接合36耦接到触点220。密封剂40沉积在图5g中的衬底200上方以产生面板。
在图5h中,例如通过化学蚀刻或机械剥离将衬底200从面板移除,并且将面板切割成多个单独的无引线设备236。在衬底200被移除的情况下,每个触点220包括可润湿侧翼232和暴露的底部部分234。虽然图5h示出在切割之前移除的衬底200,但是衬底可在切割单独设备236之后移除。
图6a示出在切割之后的单独无引线封装236。在图6b中,使用焊料240将无引线封装236安装到PCB 20以用于电连接和机械连接。焊料240在触点220和接触焊盘22之间回流,并且在接触焊盘22和可润湿侧翼232之间形成圆角表面242。衬底200的脊210修改触点220和密封剂40的形状以提供封装236的底部表面,其在封装的形成触点的边缘处凸起。封装236的凸起边缘为焊料240提供用以填充的附加空间,并且视觉检查设备56能够可视地验证对于每个触点220,焊料240在无引线封装236和PCB 20之间适当地延伸。脊210的倾斜侧边的角度可定制成在使用更陡的脊时提供更大的圆角,或者在对于脊210使用更渐进的斜率时制造具有更少圆角的较薄封装。
使用脊状衬底200来提供圆角242允许在镀覆引线框上形成焊料圆角,同时仍然使密封剂40完全围绕触点220的边缘,以便增加触点到封装的粘附性。然而,图7a示出另一个实施方案,其中触点250在两个管芯附接区域216之间跨过锯道212设置。触点250类似于触点104,并且可类似地呈现各种形状。如图7b所示,形成有触点250的切割设备256产生倾斜的侧翼232,正如无引线封装236,另外每个触点的侧表面从密封剂40暴露作为可润湿侧翼258。当无引线封装256被安装在PCB 20或另一个衬底上时,用于安装封装的焊料在倾斜侧翼232处的倾斜边缘之上回流,并且回流到在横向侧翼258处的封装的侧表面上。具有在封装的侧表面处暴露的触点250的封装256增加了焊料圆角的总尺寸,从而允许以较小的斜率形成脊210。脊210的较小斜率允许较薄的最终产品。
在其他实施方案中使用脊状衬底的其他形状。图8a示出具有按压到衬底中的倒圆脊262的衬底260。在图8b中,倒圆脊262产生具有弯曲触点264的无引线封装,其具有可润湿侧翼265。焊料266填充可润湿侧翼265和接触焊盘22之间的空间以形成圆角268。虽然图8b的无引线封装形成有完全在脊262上方延伸的触点264,但类似于图7a中的触点250,倒圆脊262还可与镀覆触点一起使用,该镀覆触点不延伸跨过锯道,类似于图5e中的触点220。
图9a示出具有按压到衬底中的矩形脊282的衬底280。脊282产生图9b中的设备284,该设备具有带有约90度角弯曲的触点286以及正方形或矩形的可润湿侧翼288。焊料290填充可润湿侧翼288和接触焊盘22之间的空间以形成圆角292。虽然无引线封装284形成有完全在脊282上方延伸的触点286,但类似于图7a中的触点250,矩形脊282还可与镀覆触点一起使用,该镀覆触点不延伸跨过锯道,类似于图5e中的触点220。
除了以各种可能的形状形成之外,脊状衬底可以各种方法形成。图10示出具有脊302的蚀刻衬底300。通过提供具有均匀厚度的衬底,并且使衬底的部分蚀刻远离脊302的期望位置来形成衬底300。在衬底300被蚀刻以形成脊302之后,衬底包括脊302所在位置的附加材料。因此,通过蚀刻从包封的引线框移除衬底300可能在脊302上花费额外的蚀刻时间。
在其他实施方案中,脊302的形成包括衬底300的底部上的蚀刻步骤以移除脊302下面的材料,从而产生具有更均匀材料分布的衬底300。脊302可被蚀刻成任何期望的形状以定制所得可润湿侧翼的形状,例如,圆形、矩形或倾斜的。脊302也可仅在要形成封装触点的特定位置处形成,而不是均匀地延伸跨过衬底300。脊302可以上文公开的形状中的任一种蚀刻,并且上文公开的触点配置中的任一种可与引线框300一起使用。
图11示出衬底310,其包括在顶部和底部上完全延伸跨过衬底的平坦表面。脊312通过将材料沉积在衬底310上方而形成。脊312的材料可为与衬底310的材料相同或不同的材料。在一个实施方案中,脊312使用光致抗蚀剂层形成。在一些实施方案中,使用从衬底310分离的蚀刻步骤从包封设备中移除脊312,以便留下具有呈脊形状的可润湿侧翼的设备。脊312的材料可以任何期望的形状沉积以形成具有任何期望形状的可润湿侧翼的设备,并且可仅在要形成封装触点的位置处形成。
虽然已详细示出并描述了一个或多个实施方案,但技术人员将认识到,在不脱离本公开的范围的情况下,可对这些实施方案作出修改和变更。
在第一实施方案中,制备半导体器件的方法包括以下步骤:提供衬底,在衬底上形成延伸跨过衬底的锯道的触点,以及切割该触点。
在第二实施方案中,第一实施方案的方法还包括通过将金属层镀覆到衬底上来形成触点。
在第三实施方案中,第一实施方案的方法还包括在衬底中形成脊,以及在脊上方形成触点。
在第四实施方案中,第三实施方案的方法还包括使用压机形成脊。
在第五实施方案中,第一实施方案的方法还包括将触点形成为在锯道上包括颈部。
在第六实施方案中,第一实施方案的方法还包括使焊料在触点上方回流以形成从触点的侧表面延伸的焊料圆角。
在第七实施方案中,第一实施方案的方法还包括将密封剂沉积在触点上方,以及移除衬底以暴露触点和密封剂。
在第八实施方案中,第七实施方案的方法,其中通过切割触点而暴露触点的侧表面,并且通过移除衬底而暴露触点的底部表面。
在第九实施方案中,制备半导体器件的方法包括以下步骤:提供包括脊的衬底,在脊上方形成第一触点,以及移除衬底。
在第十实施方案中,第九实施方案的方法还包括使用压机形成脊。
在第十一实施方案中,第九实施方案的方法还包括通过将材料沉积在衬底上方而形成脊。
在第十二实施方案中,第九实施方案的方法还包括在脊上方形成与第一触点相邻的第二触点,将密封剂沉积在第一触点和第二触点上方,以及在第一触点和第二触点之间切割密封剂。
在第十三实施方案中,第九实施方案的方法还包括形成完全在脊上方延伸的触点。
在第十四实施方案中,第九实施方案的方法还包括将触点形成为包括颈部。
在第十五实施方案中,第九实施方案的方法还包括通过机械剥离或化学蚀刻来移除衬底。
在第十六实施方案中,半导体器件包括镀覆触点,以及沉积在镀覆触点上方的密封剂。镀覆触点暴露在密封剂的侧表面处。
在第十七实施方案中,第十六实施方案的半导体器件,其中镀覆触点包括斜坡。
在第十八实施方案中,第十六实施方案的半导体器件还包括从镀覆触点延伸到密封剂的占有面积之外的焊料圆角。
在第十九实施方案中,第十八实施方案的半导体器件还包括具有接触焊盘的衬底,其中焊料圆角从镀覆触点延伸到衬底的接触焊盘。
在第二十实施方案中,第十六实施方案的半导体器件,其中镀覆触点包括颈部。

Claims (10)

1.一种半导体器件,其特征在于,所述半导体器件包括:
衬底,所述衬底包括在其上的脊;
触点,所述触点设置在所述衬底的脊上;以及
密封剂,所述密封剂设置在所述触点和所述衬底上;
其中,当所述触点和所述衬底被切割时,所述触点的表面通过所述密封剂暴露。
2.根据权利要求1所述的半导体器件,其特征在于,所述半导体器件还包括在所述触点上的镀覆层。
3.根据权利要求1所述的半导体器件,其中所述触点的表面从所述半导体器件的侧面可见。
4.一种半导体器件,其特征在于,所述半导体器件包括:
衬底,所述衬底包括在其上的脊;
触点,所述触点设置在所述衬底的脊上;以及
密封剂,所述密封剂设置在所述触点和所述衬底上;
其中,所述触点通过在所述脊处的密封剂暴露。
5.根据权利要求4所述的半导体器件,其中所述触点包括斜坡。
6.根据权利要求4所述的半导体器件,其特征在于,所述半导体器件还包括从所述触点延伸到所述密封剂之外的焊料圆角。
7.根据权利要求6所述的半导体器件,其中所述衬底包括接触焊盘,并且其中所述焊料圆角从所述触点延伸到所述衬底的所述接触焊盘。
8.根据权利要求4所述的半导体器件,其中所述触点包括颈部。
9.一种半导体器件,其特征在于,所述半导体器件包括:
衬底,所述衬底包括在其上的脊;
触点,所述触点设置在所述衬底的脊上;以及
密封剂,所述密封剂设置在所述触点和所述衬底上;
其中,所述触点的底部表面通过在所述脊处的密封剂暴露。
10.根据权利要求9所述的半导体器件,其中所述触点包括斜坡。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035722A (zh) * 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 具有选择性模制的用于镀覆的封装工艺
US11876003B2 (en) 2019-12-24 2024-01-16 Vishay General Semiconductor, Llc Semiconductor package and packaging process for side-wall plating with a conductive film

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10636729B2 (en) * 2017-06-19 2020-04-28 Texas Instruments Incorporated Integrated circuit package with pre-wetted contact sidewall surfaces
US20190013214A1 (en) * 2017-07-10 2019-01-10 Powertech Technology Inc. Package structure and manufacturing method thereof
US11127660B2 (en) * 2018-12-31 2021-09-21 Microchip Technology Incorporated Surface-mount integrated circuit package with coated surfaces for improved solder connection
JP7114537B2 (ja) * 2019-09-13 2022-08-08 株式会社東芝 半導体検査装置及び半導体装置の検査方法
US20210376563A1 (en) * 2020-05-26 2021-12-02 Excelitas Canada, Inc. Semiconductor Side Emitting Laser Leadframe Package and Method of Producing Same

Family Cites Families (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327008A (en) 1993-03-22 1994-07-05 Motorola Inc. Semiconductor device having universal low-stress die support and method for making the same
EP1213756A3 (en) 1994-03-18 2005-05-25 Hitachi Chemical Co., Ltd. Fabrication process of semiconductor package and semiconductor package
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5866939A (en) 1996-01-21 1999-02-02 Anam Semiconductor Inc. Lead end grid array semiconductor package
JPH09260568A (ja) * 1996-03-27 1997-10-03 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
JP3870301B2 (ja) 1996-06-11 2007-01-17 ヤマハ株式会社 半導体装置の組立法、半導体装置及び半導体装置の連続組立システム
KR0185512B1 (ko) 1996-08-19 1999-03-20 김광호 칼럼리드구조를갖는패키지및그의제조방법
US6193858B1 (en) 1997-12-22 2001-02-27 George Hradil Spouted bed apparatus for contacting objects with a fluid
US6130473A (en) 1998-04-02 2000-10-10 National Semiconductor Corporation Lead frame chip scale package
US7247526B1 (en) 1998-06-10 2007-07-24 Asat Ltd. Process for fabricating an integrated circuit package
US6498099B1 (en) 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6229200B1 (en) 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US6294100B1 (en) 1998-06-10 2001-09-25 Asat Ltd Exposed die leadless plastic chip carrier
US6585905B1 (en) 1998-06-10 2003-07-01 Asat Ltd. Leadless plastic chip carrier with partial etch die attach pad
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6208020B1 (en) 1999-02-24 2001-03-27 Matsushita Electronics Corporation Leadframe for use in manufacturing a resin-molded semiconductor device
WO2000062341A1 (fr) 1999-04-08 2000-10-19 Shinko Electric Industries Co., Ltd. Grille de connexion pour dispositif semi-conducteur
JP3062192B1 (ja) 1999-09-01 2000-07-10 松下電子工業株式会社 リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
US20020067486A1 (en) 2000-09-25 2002-06-06 S. Forney Leroy Solderability assessment
US6545347B2 (en) 2001-03-06 2003-04-08 Asat, Limited Enhanced leadless chip carrier
JP4034073B2 (ja) 2001-05-11 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3537417B2 (ja) 2001-12-25 2004-06-14 株式会社東芝 半導体装置およびその製造方法
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
CN100380614C (zh) 2002-04-29 2008-04-09 先进互联技术有限公司 部分构图的引线框架及其制造方法以及在半导体封装中的使用
KR100993277B1 (ko) * 2002-04-30 2010-11-10 르네사스 일렉트로닉스 가부시키가이샤 반도체장치 및 전자 장치
US6734044B1 (en) 2002-06-10 2004-05-11 Asat Ltd. Multiple leadframe laminated IC package
US6841414B1 (en) 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6940154B2 (en) 2002-06-24 2005-09-06 Asat Limited Integrated circuit package and method of manufacturing the integrated circuit package
US6872599B1 (en) 2002-12-10 2005-03-29 National Semiconductor Corporation Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP)
JP4073308B2 (ja) 2002-12-20 2008-04-09 三洋電機株式会社 回路装置の製造方法
US7071545B1 (en) 2002-12-20 2006-07-04 Asat Ltd. Shielded integrated circuit package
TWI241000B (en) * 2003-01-21 2005-10-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabricating method thereof
US7405468B2 (en) * 2003-04-11 2008-07-29 Dai Nippon Printing Co., Ltd. Plastic package and method of fabricating the same
JP2005191240A (ja) 2003-12-25 2005-07-14 Renesas Technology Corp 半導体装置及びその製造方法
US7154186B2 (en) 2004-03-18 2006-12-26 Fairchild Semiconductor Corporation Multi-flip chip on lead frame on over molded IC package and method of assembly
TWI272683B (en) * 2004-05-24 2007-02-01 Sanyo Electric Co Semiconductor device and manufacturing method thereof
US7091581B1 (en) 2004-06-14 2006-08-15 Asat Limited Integrated circuit package and process for fabricating the same
CN100576524C (zh) 2005-01-20 2009-12-30 英飞凌科技股份公司 引线框架、半导体封装及其制造方法
US20080285251A1 (en) 2005-04-07 2008-11-20 Jiangsu Changiang Electronics Technology Co., Ltd. Packaging Substrate with Flat Bumps for Electronic Devices and Method of Manufacturing the Same
US8334583B2 (en) 2005-07-20 2012-12-18 Infineon Technologies Ag Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component
US7262491B2 (en) 2005-09-06 2007-08-28 Advanced Interconnect Technologies Limited Die pad for semiconductor packages and methods of making and using same
US7943431B2 (en) 2005-12-02 2011-05-17 Unisem (Mauritius) Holdings Limited Leadless semiconductor package and method of manufacture
US7608916B2 (en) 2006-02-02 2009-10-27 Texas Instruments Incorporated Aluminum leadframes for semiconductor QFN/SON devices
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
MY142210A (en) 2006-06-05 2010-11-15 Carsem M Sdn Bhd Multiple row exposed leads for mlp high density packages
US7556987B2 (en) 2006-06-30 2009-07-07 Stats Chippac Ltd. Method of fabricating an integrated circuit with etched ring and die paddle
DE602007004516D1 (de) 2006-11-01 2010-03-11 Eveready Battery Inc Alkali-batteriezelle mit verminderter gasung und verminderter entfärbung
US20080226976A1 (en) 2006-11-01 2008-09-18 Eveready Battery Company, Inc. Alkaline Electrochemical Cell with Reduced Gassing
US8089166B2 (en) 2006-12-30 2012-01-03 Stats Chippac Ltd. Integrated circuit package with top pad
US7612435B2 (en) 2007-12-21 2009-11-03 National Semiconductor Corporation Method of packaging integrated circuits
US7786557B2 (en) 2008-05-19 2010-08-31 Mediatek Inc. QFN Semiconductor package
US8072047B2 (en) 2008-05-21 2011-12-06 Stats Chippac Ltd. Integrated circuit package system with shield and tie bar
US8021907B2 (en) * 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US8071427B2 (en) 2009-01-29 2011-12-06 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component and structure therefor
MY171813A (en) 2009-11-13 2019-10-31 Semiconductor Components Ind Llc Electronic device including a packaging substrate having a trench
US8329509B2 (en) 2010-04-01 2012-12-11 Freescale Semiconductor, Inc. Packaging process to create wettable lead flank during board assembly
US8389334B2 (en) * 2010-08-17 2013-03-05 National Semiconductor Corporation Foil-based method for packaging intergrated circuits
CN102468258A (zh) 2010-11-05 2012-05-23 飞思卡尔半导体公司 具有嵌套成排的接点的半导体器件
WO2012108469A1 (ja) * 2011-02-08 2012-08-16 ローム株式会社 半導体装置および半導体装置の製造方法
US20120306065A1 (en) * 2011-06-02 2012-12-06 Texas Instruments Incorporated Semiconductor package with pre-soldered grooves in leads
JP5959386B2 (ja) * 2012-09-24 2016-08-02 エスアイアイ・セミコンダクタ株式会社 樹脂封止型半導体装置およびその製造方法
US8535982B1 (en) * 2012-11-29 2013-09-17 Freescale Semiconductor, Inc. Providing an automatic optical inspection feature for solder joints on semiconductor packages
US20140151865A1 (en) * 2012-11-30 2014-06-05 Thomas H. Koschmieder Semiconductor device packages providing enhanced exposed toe fillets
US9576884B2 (en) * 2013-03-09 2017-02-21 Adventive Ipbank Low profile leaded semiconductor package
US9601415B2 (en) * 2014-03-27 2017-03-21 Renesas Electronics Corporation Method of manufacturing semiconductor device and semiconductor device
CN105405823A (zh) * 2014-08-20 2016-03-16 飞思卡尔半导体公司 具有可检查的焊接点的半导体装置
CN105990265B (zh) * 2015-02-26 2019-04-05 台达电子工业股份有限公司 功率转换电路的封装模块及其制造方法
JP6840466B2 (ja) 2016-03-08 2021-03-10 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及び半導体パッケージの製造方法
US10083866B2 (en) * 2016-07-27 2018-09-25 Texas Instruments Incorporated Sawn leadless package having wettable flank leads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035722A (zh) * 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 具有选择性模制的用于镀覆的封装工艺
US11876003B2 (en) 2019-12-24 2024-01-16 Vishay General Semiconductor, Llc Semiconductor package and packaging process for side-wall plating with a conductive film

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US11145581B2 (en) 2021-10-12
US20190088579A1 (en) 2019-03-21

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