CN103594388A - 具有侧壁间隔物的接触垫及其制作方法 - Google Patents

具有侧壁间隔物的接触垫及其制作方法 Download PDF

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CN103594388A
CN103594388A CN201310357770.7A CN201310357770A CN103594388A CN 103594388 A CN103594388 A CN 103594388A CN 201310357770 A CN201310357770 A CN 201310357770A CN 103594388 A CN103594388 A CN 103594388A
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contact pad
chip
carrier
positive photoresist
photoresist
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CN103594388B (zh
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J.加特鲍尔
B.魏德甘斯
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及具有侧壁间隔物的接触垫及其制作方法。公开了一种芯片接触垫和一种制作芯片接触垫的方法。本发明的实施例包括：在工件上形成多个接触垫，每个接触垫具有下侧壁和上侧壁；以及减小每个接触垫的下宽度，使得每个接触垫的上宽度大于下宽度。方法进一步包括在多个接触垫上形成光刻胶以及去除光刻胶的部分从而沿下侧壁形成侧壁间隔物。

Description

具有侧壁间隔物的接触垫及其制作方法
技术领域
本发明一般地涉及半导体器件和制作半导体器件的方法。具体地说，本发明的实施例涉及具有侧壁间隔物的芯片接触垫和制作具有侧壁间隔物的芯片接触垫的方法。
背景技术
功率半导体器件是在功率电子电路中用作开关或整流器的半导体器件。
功率器件领域被划分成两个主要类别：两端器件（二极管），其状态完全依赖于它们连接到的外部功率电路；和三端器件，其状态不仅依赖于它们的外部功率电路，而且还依赖于在它们的驱动端（栅极或基极）上的信号。晶体管和晶闸管属于那个类别。
第二种分类是不太明显的，但是对器件性能具有强烈影响：一些器件是多数载流子器件诸如肖特基二极管和MOSFET，而另一些是少数载流子器件诸如晶闸管、双极晶体管、和IGBT。前者仅使用一种类型的电荷载流子，而后者使用两者（即电子和空穴）。多数载流子器件更快，但少数载流子器件的电荷注入允许更好的导通状态性能。
发明内容
根据本发明的实施例，制作半导体器件的方法包括在工件上形成多个接触垫，每个接触垫具有下侧壁和上侧壁并且减少每个接触垫的下宽度以便每个接触垫的上宽度比下宽度大。方法进一步包括在多个接触垫上形成光刻胶并且去除光刻胶的部分从而沿下侧壁形成侧壁间隔物。
根据本发明的实施例，制作半导体器件的方法包括在工件上形成多个芯片接触垫，其中每个芯片接触垫具有上部分和下部分，上部分横向突出下部分，并且其中每个芯片接触垫包括沿着上部分的上侧壁和沿着下部分的下侧壁。方法进一步包括：在多个芯片接触垫的下侧壁上形成光刻胶间隔物；通过切割工件形成多个芯片，每个芯片具有接合接触垫；和在载体上放置多个芯片中的一个芯片。方法最后包括将芯片接触垫接合到载体的载体接触垫和用封装材料封装芯片。
根据本发明的实施例，半导体器件包括载体、布置在载体上的芯片和设置在芯片上的第一芯片接触垫，第一芯片接触垫具有下侧壁和上侧壁，第一芯片接触垫的下宽度小于第一芯片接触垫的上宽度，下宽度对应于下侧壁而上宽度对应于上侧壁。半导体器件进一步包括沿第一芯片接触垫的下侧壁布置的光刻胶侧壁间隔物和封装该芯片的封装材料。
附图说明
为了更完全地理解本发明及其优点，现在参考连同附图进行的后面的描述，其中：
图1图示常规芯片接触垫；
图2a图示在芯片接触垫上具有侧壁间隔物的包装半导体器件的实施例；
图2b图示在芯片接触垫上具有侧壁间隔物的包装半导体器件的进一步实施例；
图3图示芯片顶面的部分的详细视图的实施例；以及
图4图示制造具有带有侧壁间隔物的芯片接触垫的半导体器件的方法的实施例的流程图。
具体实施方式
下面详细地讨论目前优选实施例的制作和使用。然而应当理解的是，本发明提供了许多可应用的创造性构思，其可以体现于广泛的各种具体背景中。所讨论的具体实施例仅仅说明用于制作和使用本发明的具体方式并且不限制本发明的范围。
将在具体背景中关于实施例（即功率接触元件的光刻胶侧壁间隔物）描述本发明。然而，本发明也可以应用到其它接触元件的其它类型的侧壁间隔物。
图1图示常规功率接触垫120。常规功率接触垫120被封装在模制化合物140中。常规功率接触垫120的问题是模制化合物不适当地附着到钝化层110以及功率接触垫的顶面和侧壁上的氧化钯。常规功率接触垫120的进一步的问题是模制化合物的粗粒子不适当地填充紧密间隔的邻近功率接触垫120之间的空间125。最后，常规功率接触垫120的问题是围绕常规功率接触垫120所使用的聚酰亚胺130的量产生显著的晶片弯曲。
因此，在侧壁间隔物提供到钝化层和芯片接触垫的侧壁的适当附着并且进一步在邻近芯片接触垫之间提供适当介电强度（击穿每单位厚度的绝缘体所需要的电势）的领域中需要包装的功率半导体器件。
本发明的实施例提供一种具有底切并且因此具有较小下宽度和较大上宽度的芯片接触垫。本发明的实施例沿较小下宽度的侧壁而不沿较大上宽度的侧壁提供侧壁间隔物。本发明进一步的实施例在紧密间隔的芯片接触垫的相对侧壁上提供侧壁间隔物，其中芯片接触垫之间的空间的大部分用封装材料填充。
本发明的实施例提供一种通过在芯片接触垫上沉积正性光刻胶并且在不使用光刻掩膜的情况下曝光正性光刻胶而在芯片接触垫上形成光刻胶侧壁间隔物的方法。
优点是可以通过在没有光刻掩膜的情况下曝光正性光刻胶或以伪光刻掩膜曝光正性光刻胶来形成芯片接触垫的侧壁间隔物。进一步的优点是介电强度被增加并且因为使用了更少的光刻胶，晶片弯曲被减小。最后的优点是在不使用光刻掩膜的情况下很好地限定了侧壁间隔物。
图2a示出了封装功率半导体器件200的实施例。芯片210布置在载体220上。芯片210具有第一主表面211和第二主表面212。芯片接触垫215布置在第一主表面212上。侧壁间隔物217布置在芯片接触垫215的侧壁上。芯片接触垫215经由接合引线230电连接到载体接触垫225。芯片210用封装材料240诸如模制化合物进行封装。
芯片210包括半导体衬底。半导体衬底可以是单晶体衬底诸如硅或锗，或者化合物衬底诸如SiGe、GaAs、InP或SiC。一个或多个互连金属化层可以设置在衬底上。钝化层布置在金属化层的顶面上以便密封芯片。芯片的顶面是第一主表面211。衬底的底部是芯片的第二主表面212。芯片接触垫215布置在芯片210的顶面211上。
芯片210可以包括集成电路（IC）或分立器件诸如单个晶体管。例如，芯片210可以包括功率半导体器件诸如双极晶体管、绝缘栅双极晶体管（IGBT）、功率MOSFET、晶闸管或二极管。
载体220可以包括衬底、引线框架或印刷电路板（PCB）。载体220可以包括载体接触垫225。载体接触垫225包括导电材料诸如金属。例如，载体接触垫225包括铜和镍。
芯片210通过粘合或焊接而附着到载体220。例如，芯片210的第二主表面212用胶带接合或粘合到载体220的顶面。可替代地，芯片210的第二主表面212使用电绝缘粘合剂诸如树脂接合或粘合到载体220的顶面。
芯片接触垫215经由接合引线230电连接到载体接触垫225。接合引线230可以包括铜（Cu）、金（Au）或铝（Al）。接合引线230经由球形接合工艺或楔形接合工艺可以连接到芯片接触垫215和/或载体接触垫225。下面关于图3讨论芯片接触垫215的实施例。
封装材料240封装芯片210并且覆在载体220的顶面上。封装材料240可以是模制化合物。模制化合物240可以包括热固性材料或热塑性材料。模制化合物可以包括粗粒的材料粒子。
在一个实施例中，芯片210可以附着到散热器。散热器可以设置在芯片210和载体220之间。在一个实施例中，载体220可以包括散热器。包装和散热器提供了用于通过将热量传导到外部环境而从半导体器件去除热量的装置。大电流器件通常具有大管芯和包装表面积以及较低的热阻。
图2b示出包装功率半导体器件250的另一个实施例。芯片260布置在载体270上。芯片260具有第一主表面261和第二主表面262。芯片接触垫265设置在第二主表面262上。侧壁间隔物267布置在芯片接触垫265的侧壁上。芯片接触垫265经由焊球280电连接到载体接触垫275。芯片260用封装材料290诸如模制化合物进行封装。
图2b的实施例可以包括与关于图2a描述的类似或相同的材料和元件，除了芯片260和载体270之间的电连接。例如，芯片260可以是集成电路（IC）或分立器件。在图2b的实施例中，芯片260使用焊料凸起电连接到载体270。可替代地，可以使用金凸起、模制突起（stud）或导电聚合物。芯片260以倒装芯片设置的方式放置在载体270上以便第一主表面261面对载体270的顶面并且第二主表面262背向载体顶面。焊料凸起可以是铅基焊料凸起或无铅（lead less）焊料凸起。
图3图示图2a和2b的实施例的芯片210的顶面211部分的详细视图的实施例。芯片接触垫320布置在钝化层312上。钝化层312可以包括例如SiN。芯片接触垫320通过接触通孔可以电连接到金属化层堆叠的顶部金属。
芯片接触垫320可以由导电材料诸如金属制成。例如，芯片接触垫320可以包括铜（Cu）层321。可替代地，芯片接触垫320可以包括包含预先确定比例的Cr、Al、Si、Ti、Fe、Ag、Pd和/或它们的组合的铜合金层321。芯片接触垫320进一步包括金属材料层堆叠322。金属材料层堆叠322可以包括至少一种金属材料。例如，金属材料层堆叠322的第一层可以是Ni或Ni合金层323。金属材料层堆叠的第二层可以是可选的钯（Pd）或钯合金层324。金属材料层堆叠322的第三层可以是可选的金（Au）层或金合金层325。金属材料层堆叠322可以包括多余三个的金属层。
铜层321可以包括第一侧壁或下侧壁326并且金属材料层堆叠322可以包括第二侧壁或上侧壁327。第一侧壁326的高度h可以是大约1μm到大约50μm。可替代地，第一侧壁326的高度h可以是大约6μm到大约20μm。第二侧壁327的高度可以是大约1μm到大约10μm。芯片接触垫可以包括蘑菇状拓扑结构。铜层321具有第一宽度d1并且金属材料层堆叠322具有第二宽度d2。第一宽度d1不同于第二宽度d2。具体地说，第二宽度d2大于第一宽度d1。芯片接触垫320的金属材料层堆叠322可以横向突出或伸出芯片接触垫320的铜层321。例如，铜层321的宽度d1为大约20μm到大约500μm。伸出部在芯片接触垫320的每侧伸出铜层321大约0.5μm到大约1μm。
侧壁间隔物332沿第一侧壁326布置并且可以不沿第二侧壁327布置。侧壁间隔物332可以包括绝缘体材料。绝缘体材料可以包括比封装材料更高的介电强度。绝缘体材料可以是正性光刻胶，例如PBO（聚苯并恶唑）或聚酰亚胺。侧壁间隔物332主要位于伸出部以下，此处曝光的光不曝光正性光刻胶或仅有限地曝光正性光刻胶。
封装材料340包围接触芯片接触垫320和侧壁间隔物332。封装材料340可以是模制化合物。模制化合物340可以填充紧密间隔的接触芯片垫320之间的空间的大部分。模制化合物340可以填充紧密间隔的接触芯片垫之间的空间的中心部分。
图4示出制造具有带有侧壁间隔物的芯片接触垫的半导体器件的方法的实施例的流程图400。在第一步骤410中，在工件上形成多个芯片接触垫。工件可以是衬底、晶片或印刷电路板（PCB）。在一个实施例中衬底可以包括半导体材料或化合物材料以及布置在其上的一个或多个互连金属化层。钝化层布置在互连金属化层上并且芯片接触垫布置在钝化层上。芯片接触垫通过接触通孔连接到互连金属化层的最上金属层。在另一个实施例中，衬底可以包括：由薄金属箔制成的导电层，嵌入在用例如环氧树脂预浸渍制品层叠在一起的绝缘层中。
在实施例中，在钝化层上遮蔽铜层或铜合金层。例如，通过首先形成种子层并且然后用电化学电镀工艺或电流（electro galvanic）电镀来沉积铜/铜合金，形成铜或铜合金层。芯片接触垫可以进一步包含金属材料层堆叠。金属材料层堆叠也可以通过电化学电镀或电流电镀来形成。金属材料层堆叠可以包括镍（Ni）层或镍合金层。金属层堆叠可以进一步包括可选的钯（Pd）或钯合金层。最后，金属层堆叠可以包括可选的金或金合金层。可替代地，芯片接触垫可以通过其它沉积工艺诸如无电电镀或PVD工艺来形成。
接着，在412处，在形成芯片接触垫之后可以刻蚀铜层。刻蚀是各向同性化学湿法刻蚀。湿法化学刻蚀对于钝化层和金属材料层堆叠是选择性的。湿法化学刻蚀相对于金属材料层堆叠的宽度减小铜层的宽度。金属材料层堆叠横向突出或伸出铜层。金属材料层堆叠的伸出部在每侧伸出铜或铜合金层大约0.5μm到大约1μm。
光刻胶可以布置在接触垫上（步骤414）。光刻胶可以布置或旋压（spin）在芯片接触垫上。光刻胶可以是正性光刻胶。正性光刻胶是其中被曝光的光刻胶部分变得可溶的一种类型的光刻胶。
光刻胶可以被曝光、显影和固化（步骤416）。在不使用光刻掩膜的情况下，可以使光刻胶曝光。可替代地，使用在其上不具有任何结构的伪光刻掩膜，可以曝光光刻胶。光使光刻胶曝光，除了在伸出部以下。当曝光光刻胶时，在伸出部以下的光刻胶在阴影区中。光可能不足够曝光芯片接触垫附近的光刻胶。在一个实施例中，当两个芯片接触垫从彼此紧密间隔时，光可能不足够曝光在两个邻近芯片接触垫之间的光刻胶，以便在这些位置中的光刻胶不变得可溶。在一个实施例中，光刻胶可能仅保持在芯片接触垫的顶面以下的区域中。
在进一步的实施例中，用散焦光曝光正性光刻胶。曝光光的焦点可以设定在芯片接触垫的顶面的水平。光可能不足够曝光芯片接触垫底部附近的光刻胶，以便在后来的工艺步骤中光刻胶不被去除。然后正性光刻胶被显影和固化。在铜层刻蚀期间产生的底切建立起对这些侧壁的良好保护。在一个实施例中，侧壁间隔物不布置在金属材料层堆叠的侧壁上。
在下一个步骤418中，工件单颗化或切割成多个芯片或管芯。每个芯片包括至少一个包含光刻胶侧壁间隔物的芯片接触垫。例如，二极管可以包括单个芯片接触垫而其它器件可以包括两个或多个芯片接触垫。
在下一个步骤420中，多个芯片的一个芯片放置在载体（诸如引线框架或印刷电路板（PCB））上。芯片可以通过粘合或接合而附着到载体。例如，芯片可应用胶带附着到载体。在一个实施例中，芯片以芯片接触垫背向载体的方式接合到载体。在另一个实施例中，芯片以芯片接触垫面向载体的方式接合到载体。
然后，芯片接触垫可以接合到载体的载体接触垫（步骤422）。例如，芯片的芯片接触垫引线接合到载体的载体接触垫。可替代地，芯片的芯片接触垫焊接到载体的载体接触垫。在一个实施例中，使用铝引线而引线接合到载体接触垫的芯片的芯片接触垫在金属材料层堆叠中包括钯层，而使用铜引线而引线接合到载体接触垫的芯片接触垫在金属材料层堆叠中不包括钯层。
最后，在步骤424，芯片用封装材料进行封装。封装材料可以是模制化合物。模制化合物可以包括热固性材料或热塑性材料。模制化合物可以包括粗粒的材料。
尽管已经详细地描述了本发明及其优点，但应当理解的是，在不脱离如由附加的权利要求限定的本发明的精神和范围的情况下，在这里可以进行各种变化、替代和更改。
此外，本申请的范围不旨在限制于说明书中描述的工艺、机器、制造、物质的组成、装置、方法和步骤的特定实施例。作为本领域的一个普通技术人员将容易地从本发明的公开中理解到：根据本发明可以利用与这里描述的对应的实施例执行基本上相同功能或达到基本上相同结果的现存的或后来要发展的工艺、机器、制造、物质的组成、装置、方法或步骤。因此，附加的权利要求旨在在其范围内包含这样的工艺、机器、制造、物质的组成、装置、方法或步骤。

Claims (21)

1.一种制作半导体器件的方法，该方法包括：
在工件上形成多个接触垫，每个接触垫具有下侧壁和上侧壁；
减小每个接触垫的下宽度，使得每个接触垫的上宽度大于下宽度；
在多个接触垫上形成光刻胶；以及
去除光刻胶的部分从而沿下侧壁形成侧壁间隔物。
2.根据权利要求1的方法，其中形成光刻胶包括形成正性光刻胶。
3.根据权利要求2的方法，其中去除正性光刻胶包括曝光正性光刻胶和显影正性光刻胶。
4.根据权利要求3的方法，其中曝光正性光刻胶包括在不使用光刻掩膜的情况下曝光正性光刻胶。
5.根据权利要求3的方法，其中曝光正性光刻胶包括以伪光刻掩膜曝光正性光刻胶。
6.根据权利要求1的方法，其中光刻胶是聚酰亚胺或PBO（聚苯并恶唑）。
7.根据权利要求1的方法，其中形成多个接触垫包括形成铜层或铜合金层以及然后形成金属材料层堆叠，其中金属材料层堆叠包括镍（Ni）和金（Au）。
8.根据权利要求7的方法，其中形成铜层包括电化学电镀铜，并且其中形成金属材料层堆叠包括电化学电镀镍（Ni），然后电化学电镀钯（Pd），以及然后电镀金（Au）。
9.一种制作半导体器件的方法：
在工件上形成多个芯片接触垫，其中每个芯片接触垫具有上部分和下部分，上部分横向突出下部分，并且其中每个芯片接触垫包括沿着上部分的上侧壁和沿着下部分的下侧壁；
在多个芯片接触垫的下侧壁上形成光刻胶间隔物；
通过切割工件形成多个芯片，每个芯片具有芯片接触垫；
在载体上放置多个芯片中的一个芯片；
将芯片接触垫接合到载体的载体接触垫；以及
用封装材料来封装芯片。
10.根据权利要求9的方法，其中形成光刻胶间隔物包括在工件上形成正性光刻胶以及从工件上去除正性光刻胶的部分从而形成正性光刻胶间隔物。
11.根据权利要求10的方法，其中去除正性光刻胶包括使正性光刻胶曝光，显影正性光刻胶，以及固化正性光刻胶。
12.根据权利要求11的方法，其中使正性光刻胶曝光包括在不使用光刻掩膜的情况下曝光正性光刻胶或以伪光刻掩膜曝光正性光刻胶。
13.根据权利要求9的方法，其中芯片接触垫的下部分包括铜或铜合金，其中芯片接触垫的上部分包括金属材料层堆叠，并且其中金属材料层堆叠包括镍层和金（Au）层。
14.根据权利要求13的方法，其中金属材料层堆叠进一步包括钯（Pd）层。
15.一种半导体器件，包括：
载体；
布置在载体上的芯片；
设置在芯片上的第一芯片接触垫，第一芯片接触垫具有下侧壁和上侧壁，第一芯片接触垫的下宽度小于第一芯片接触垫的上宽度，下宽度对应于下侧壁而上宽度对应于上侧壁；
沿第一芯片接触垫的下侧壁布置的光刻胶侧壁间隔物；和
封装芯片的封装材料。
16.根据权利要求15的半导体器件，其中第一芯片接触垫包括具有下侧壁的铜层或铜合金层。
17.根据权利要求16的半导体器件，其中第一芯片接触垫包括上侧壁之间的金属材料层堆叠，金属材料层堆叠包括镍（Ni）层和金（Au）层。
18.根据权利要求17的半导体器件，其中光刻胶侧壁间隔物是正性光刻胶侧壁间隔物。
19.根据权利要求15的半导体器件，其中载体包括第一载体接触垫，并且其中第一芯片接触垫电连接到第一载体接触垫。
20.根据权利要求19的半导体器件，其中芯片包括第二芯片接触垫并且载体包括第二载体接触垫，其中第二芯片接触垫电连接到第二载体接触垫，并且其中第一和第二芯片接触垫经由引线电连接到第一和第二载体接触垫。
21.根据权利要求19的半导体器件，其中芯片包括第二芯片接触垫并且载体包括第二载体接触垫，其中第二芯片接触垫电连接到第二载体接触垫，并且其中第一和第二芯片接触垫经由焊料电连接到第一和第二载体接触垫。
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