TWI395277B - 晶圓水準的晶片級封裝 - Google Patents

晶圓水準的晶片級封裝 Download PDF

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TWI395277B
TWI395277B TW097148322A TW97148322A TWI395277B TW I395277 B TWI395277 B TW I395277B TW 097148322 A TW097148322 A TW 097148322A TW 97148322 A TW97148322 A TW 97148322A TW I395277 B TWI395277 B TW I395277B
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wafer
semiconductor
semiconductor wafer
conductor material
semiconductor wafers
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TW097148322A
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TW200929408A (en
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Sun Ming
Feng Tao
Hebert Francois
Se Ho Yueh
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Alpha & Omega Semiconductor
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Description

晶圓水準的晶片級封裝
本發明涉及半導體封裝領域，更特別的是涉及低成本的晶圓水準晶片級封裝工藝。
低封裝電阻Rds-on 和好的性能是半導體器件所追求的。尤其是在金屬氧化矽場效應電晶體(MOSFET)的情況中，特別的，垂直導通功率MOSFET器件具有位於同一個表面上的柵極和源極以及位於相反表面上的漏極。通常也希望具有簡單、快速、高效的半導體器件封裝方法。因此，現有技術中已經提出了許多封裝的概念和方法。
在過去的十年間矽制程技術取得了顯著的進步，而在同樣的十年間，封裝技術仍然沿用原先的封裝方法。環氧樹脂或焊料晶片沿鋁或金鍵合線附貼到引線框架上仍然是優選的半導體封裝方法。然而，在改進的半導體制程技術中，產生了許多與常見封裝相關的寄生物(如電阻、電容和電感)，從而成為性能限制因素。在現有的倒裝晶片技術中，眾多缺點之中，熱耗散受限於晶尺寸，而且晶片背面的連接(通常需要鍵合線)是難以達到的。這些限制(散熱困難和連接背面的阻力)在例如功率開關器件這樣的高電流的應用中變得十分明顯。
美國專利6,767,820公開了一種半導體MOS柵極器件的規模封裝工藝。MOS柵極器件晶圓的源極側覆蓋有一鈍化層，優選感光液體環氧樹脂，或氮化矽層，或其他類似 的材料。材料乾燥後，使用標準光刻技術圖案化有覆蓋層的晶圓，在鈍化層上形成若干開口，從而在晶圓上的每一個晶片上的源極金屬的下面產生若干個相互分離暴露表面區域，還形成類似的開口用以暴露每個晶片的柵極下部。鈍化層上的開口通常設置為穿過普通的下部可焊頂部金屬層，例如鈦、鎢、鎳或銀。在開口形成後，晶圓被鋸開或以別的方式分割為獨立晶片。然後將獨立晶片的源極側朝下，U型或杯型的部分電鍍的漏極夾片通過導電環氧樹脂或焊料連接到晶片的可焊漏極側，或類似地連接漏極夾片到晶片的底部漏極。漏極夾片引腳的底部與源極側表面(為連接突出物的頂部)處於同一平面。然而，U型夾片通常使用銅合金製成，並至少帶有部分鍍銀表面，而且實際上非常薄。因此，此類U型夾片相當昂貴。另外，不同的晶片尺寸需要不同的U型夾片，又或者較小的晶片使用了較大的U型夾，這就佔據了更多的積體電路板空間。
美國公開號為2003/0052405的美國專利公開了一種垂直功率MOSFET器件，該器件具有通過例如焊料這樣的鍵合材料連接到引線框架的源極和柵極，而位於整個晶片底部表面之下的漏極則直接連接到其所在的襯底。該垂直MOSFET器件其上部朝下設置，從而形成於矽襯底底部表面上的漏極會連接到其上的引線框架，而柵極和源極則開設在器件的底部。MOSFET器件由例如環氧樹脂或矽的樹脂封口，這樣可以覆蓋MOSFET器件和引線框架的內部部分。在MOSFET器件的底部表面上，樹脂表面大致充滿引 線框架和漏極表面。在半導體器件的底部表面上暴露出引線框架外部引腳部分的底部表面以及底部表面漏極用以連接所在襯底的導電部分(置於表面)，隨後，漏極的周圍就被樹脂覆蓋。
美國專利號為6,133,634的美國專利公開了一種功率MOSFET器件的覆晶封裝結構，包括一漏極端，一源極端和一柵極端。漏極端連接導電載體和一系列外部焊球。源極端和柵極端連接一系列內部焊球。導電載體和外部焊球系列提供印刷電路板與漏極端之間的電連接。
專利號為6,469,384的美國專利公開了一種封裝例如MOSFET器件這樣的半導體器件的方法，其不需要模體(molded body)。MOSFET器件與襯底連接，從而使晶片的源極與柵極區域與襯底連接。MOSFET器件置於一印刷電路板(PCB)上，晶片表面通過焊膏或合適的導電內連接直接連接PCB，這也就可以作為漏極連接。連接到襯底的晶片表面包括晶片的柵極區域和源極區域。從而，在襯墊柵極區域中的焊球將晶片柵極區域耦合到PCB，而剩餘的焊球將晶片的源極區域通過襯底耦合到PCB。
現有的垂直MOSFET器件的封裝設計每次僅能提供一個獨立MOSFET上源極，柵極和漏極的內部電連接，這是昂貴且耗時的。另外，可用的晶片空間也會減少。因此需要提供一種製造的封裝設計及方法，其可以批量處理從而減少生產線的設備需求也可以降低成本。
本文中將提供本發明的具體實施方式。
本發明的目的在於公開了一種在晶圓水準晶片級封裝工藝中製造背部與前部之間的電連接的方法，包括：a)在封裝襯底上安裝包括兩個或多個半導體晶片的晶圓，其中每一個半導體晶片都包括一個或多個位於暴露的背部的電極；b)去除相鄰兩個或多個半導體晶片之間的劃線部分，以在其間形成相對寬的溝槽；c)在半導體晶片的背側及溝槽中設置導電材料；d)以及切割位於相鄰兩個或多個半導體晶片之間的溝槽中的導電材料，只將導電材料留在兩個或多個半導體晶片的背部及側壁上。以此，導電材料就提供了從半導體晶片背部上的電極到半導體晶片前部的電連接。
所述的多個半導體晶片中的每一個都包括圖案化為基板柵格陣列(LGA)的前表面。
其中步驟a)包括使用厚刃晶圓鋸去除相鄰兩個或多個半導體晶片之間的劃線部分。其中所述的厚刃晶圓鋸的刃的厚度為80μm至100μm。
所述的導體材料包括導電環氧樹脂或導電填充材料。
所述的步驟d)包括使用薄刃晶圓鋸切割相鄰兩個或多個半導體晶片之間的導體材料；其中薄刃晶圓鋸的刃的厚度為20μm至30μm。
所述的數個半導體晶片包括一個或多個垂直金屬氧化矽場效應電晶體(MOSFET)，所述的一個或多個垂直金屬氧化矽場效應電晶體包括一個或多個溝槽MOSFET，其中一個或多個位於暴露背側的電極包括一個或多個漏極。
所述的一個或多個位於暴露背側的電極組成一標準背側金屬或晶圓襯底上的暴露的背側部分。
還包括在去除所述劃線部分之前，對暴露的背側部分進行摻雜及退火，以及還包括在應用導體材料之前，清潔晶圓表面。
一種晶片級半導體封裝結構，包括：一功率半導體晶片，包括一個或多個位於其背部及其前部的電極；一層覆蓋於所述半導體晶片背側和所述半導體晶片側壁上的導體材料，以形成封裝的最外層表面，其中導體材料層的側面還延伸到所述晶片前側的邊緣。
所述的導體材料層覆蓋所述半導體晶片的四個側壁。
其中所述的前側面圖案化為基板柵格陣列。
所述的半導體晶片包括垂直MOSFET。
所述的半導體晶片包括橫向MOSFET晶片，其具有底部柵極和漏極以及開設於頂部的源極。
所述的半導體晶片包括絕緣柵雙極型電晶體(IGBT)。
本發明的優點在於提供了一種製造的封裝設計及方法，允許真正的晶圓層級的半導體器件晶片規模封裝工藝，並具有最小附加成本，從而可以批量處理而且減少生產線的設備需求也可以降低成本。
儘管後續的詳細敍述包括許多意在解釋本發明的特殊細節，任何本領域的普通技術人員都會認識到許多對於所述細節的變化和代替都屬於本發明的範圍。相應的，下文 中所敍述的本發明的具體實施例對所要求的發明內容概要沒有任何的缺失，也沒有對其強加任何限制。
依照本發明的一個具體實施例的製作內部電連接的方法如第1A至1E圖及第2圖所示。第1A至1E圖一系列圖示，其用於說明第2圖所示的流程圖中描述的方法200。在本例中，內部電連接形成于以晶圓水準晶片級封裝工藝(CSP)封裝的溝槽MOSFET的漏極側。
參考第2圖，方法200開始於步驟202，將器件安裝在封裝襯底上。舉例來說，如第1A圖所示，半導體晶圓100包括若干個圖案化於其表面的半導體晶片102，例如垂直MOSFET，該半導體晶片由晶圓製作過程製備。每一個半導體晶片包括一個暴露於頂部的背面漏極107。背面漏極107可以由標準背面材料構成，例如鈦鎳銀合金、鉻金合金、鈦金合金等。也可以選擇不使用金屬，而使用晶圓100的襯底的背面暴露部分作為電極107。暴露的背面晶圓襯底也可以進行摻雜和退火，以減少與後續制程中加入的導電材料層110之間的連接電阻。劃線104部分將半導體晶圓100分割為若干個半導體晶片102。晶圓100安裝在封裝襯底101上。例如，當晶圓100被安裝到載體上時，可以採用帶狀安裝。如果晶圓100安裝在一真空卡盤上，則可選擇通過真空安裝。半導體晶片102可以包括一圖案化為基板柵格陣列(LGA)的前表面。如第2圖中所示的步驟204，晶圓可以通過在器件之間形成比較寬的溝道來分隔成各個部分。舉例來說，在兩個半導體晶片102之間的劃線104 可以通過使用如第1B圖中所示的厚刀片狀晶圓鋸106去除，以形成位於兩個半導體晶片102之間的溝槽108。厚刀片狀晶圓鋸106的刀刃厚度大約為80μm至100μm。
如第2圖中所述的步驟206，導體材料110可以覆蓋在器件上並填充器件間的溝槽。導體材料110覆蓋半導體晶片102的四個側壁。例如，如第1C圖所示，用形成導體材料110的導體環氧樹脂填入溝槽108並覆蓋漏極107的頂部和半導體晶片102的側面。舉例來說，導體材料110可以是碳材料，如納米碳或碳納米管。導體材料110也可以選擇導體粘合劑、導體環氧樹脂、焊錫及其它類似的物質。導體材料110設置於半導體晶片102的背面及側壁，以而提供從晶片102背面上的漏極107到晶圓正面的電連接。在本例中，背部電極107由晶圓襯底而非金屬構成，所以需要在沉積導體金屬110之前進行清潔步驟，以此來減少有可能會形成在晶圓表面的任何雜質或氧化物，從而確保背部電極107與導體材料110之間具有較好的連接。清潔溶液可以包括稀釋氫氟、溶劑、蒸汽氫氟等。
如第2圖中步驟206所述，通過切割位於器件之間相對較寬的溝槽108中的導體材料110來實現器件的彼此分離。舉例來說，半導體晶片的獨立可以通過使用薄刃鋸112切割位於晶片間的固化的導電材料實現，以此將晶圓100分割成如第1E圖所示的獨立半導體器件116。優選的，薄刃鋸112的刃的厚度小於溝槽108的寬度，例如，如果溝槽的寬度大約為80至100微米，則薄刃鋸112的刃的寬度 大約為20至30微米。其結果是，覆蓋於背部表面和側壁表面的導電材料層不僅實現了從背部電極到前表面的電連接，也保護了晶片的側面在成品電測試、封裝、電路板層級設置及運輸過程中免受刮傷、破損及其它化學危害。
第3圖所示為使用第1A-1E圖中的工藝製作的獨立半導體器件116安裝到印刷電路板(PCB)113上的電路連接。如第3圖所示，半導體器件116包括半導體晶片102，所述的半導體晶片102包括源極103，柵極105和漏極107，導電環氧樹脂或導電填充材料109沉積到漏極107的頂部及劃線槽108中。導電填充材料109可以覆蓋半導體晶片102的四壁。源極103和柵極105通過焊料連接物111電連接到位於PCB113上的銅墊115。鈍化或絕緣物質填充到電極103和105之間的溝槽中。焊料掩模117沉積到銅墊115之間。
本發明的具體實施方式允許真正的晶圓層級的半導體器件晶片規模封裝工藝(CSP)，該封裝的器件背部與前部連接，並具有最小附加成本。常見的CSP系統也可以經過相對最少的修改後使用，例如，更厚的鋸刃可以提供臨近晶片與裝置之間的溝槽，用於應用覆蓋及位於晶片之間的導電材料。在本發明的具體實施方式中，通過設置開口從而在漏極連接處使用納米碳或碳納米管。
沒有與本發明的具體實施方式相關聯的最小CSP尺寸。本發明的具體實施方式中的製作工藝與晶片尺寸完全無關，也沒有必要準備任何預製的導電蓋或薄膜。另外， 也不需要如其它技術中所要求的預刻的金屬框架或用於CSP的襯底和焊料突起。
本發明的具體實施方式允許在很簡單的晶圓層級CSP制程中提供背部與前面的電連接。該制程不需要背部到前面的漏極連接的裝配步驟。作為比較，在現有技術的制程中，所使用的裝配步驟需要更多的材料消耗及裝置。
另外，所述的制程可以相當靈活的應用於任何晶片尺寸，對於不同尺寸的晶片無需作出加工變化。作為比較，現有技術中對不同尺寸的晶片，不是要求加工新的金屬框架，就是要改變球柵陣列封裝(BGA)掩模，另外設備轉換裝置也需要變化，所有這些都耗費巨大。此外，在現有技術中許多晶圓水準晶片級封裝工藝的結構與制程中，由於晶圓與晶圓背部覆蓋材料之間的熱漲不吻合而造成的晶圓翹曲的難題在這裏就不再需要關注了，因為在上述的制程中，將晶圓切割為小晶片之後才將其用導電材料進行覆蓋。這大大降低了晶圓和覆蓋材料之間熱漲不吻合的可能性。
在此所述的制程可以應用於任何垂直半導體器件。這也應用於任何在頂部及底部開設有導電區域的橫向半導體器件，例如絕緣柵雙極型電晶體(IGBT)或底部源極橫向雙擴散MOSFET(BS-LDMOSFET)。BS-LDMOSFET具有位於底部的柵極和漏極以及可設於頂部的源極(襯底)。
由於上述是對於本發明的優選實施方式的完整敍述，其可以做出各種各樣的選擇，修改和等價替換。因此，本 發明的範圍不應取決於上述的內容，而應當取決於附後的權利要求及其所有等價的範圍。任何優選或非優選的特徵都可以與其他優選或非優選的特徵組合。在後附的權利要求中，除非有其他明確的說明，定冠詞“一”指的是一個或更多的所述物件的數量。權利要求不能被解釋為包括方法加功能的限制，除非在所給出的權利要求中以“其方法為”作出明確的敍述。
100 ‧‧‧晶圓
102 ‧‧‧半導體晶片
101 ‧‧‧封裝襯底
103 ‧‧‧源極
104 ‧‧‧劃線
105 ‧‧‧柵極
106 ‧‧‧厚刀片狀晶圓鋸
107 ‧‧‧漏極
108 ‧‧‧劃線槽
109 ‧‧‧導電填充材料
110 ‧‧‧導體材料
111 ‧‧‧焊料連接物
112 ‧‧‧薄刃鋸
113 ‧‧‧印刷電路板
115 ‧‧‧銅墊
116 ‧‧‧半導體器件
117 ‧‧‧焊料掩模
本發明的其他內容及優點在閱讀了後續的具體實施方式並參考下列相應附圖後得以體現：第1A-1E圖所示為一種晶圓水準晶片級封裝工藝，其中，在溝槽MOSFET的漏極側具有電連接。
第2圖是第1A-1E圖中所示的晶圓水準晶片級封裝工藝的流程圖。
第3圖所示為使用第1A-1E圖中的工藝製作的具有漏極電連接的溝槽MOSFET的側視圖。

Claims (21)

  1. 一種在晶圓水準級封裝工藝中製造背部與前部之間的電連接的方法，包括：a)在封裝襯底上安裝包括兩個或多個半導體晶片的晶圓，其中每一個半導體晶片都包括一個或多個位於暴露的背部的電極；b)去除相鄰兩個或多個半導體晶片之間的劃線部分，以在其間形成相對寬的溝槽；c)在半導體晶片的背側及溝槽中設置導電材料；以及d)切割位於相鄰兩個或多個半導體晶片之間的溝槽中的導電材料，只將導電材料留在相鄰兩個或多個半導體晶片的背部及側壁上，其中導體材料的側面還延伸到所述半導體晶片前側的邊緣；以此，導電材料就提供了從半導體晶片背部上的電極到半導體晶片前部的電連接。
  2. 如申請專利範圍第1項所述的方法，其特徵在於，其中所述的兩個或多個半導體晶片中的每一個都包括圖案化為基板柵格陣列的前表面。
  3. 如申請專利範圍第1項所述的方法，其特徵在於，其中步驟a)包括使用厚刃晶圓鋸去除相鄰兩個或多個半導體晶片之間的劃線部分。
  4. 如申請專利範圍第3項所述的方法，其特徵在於，其中厚刃晶圓鋸的刃的厚度為80μm至100μm。
  5. 如申請專利範圍第1項所述的方法，其特徵在於，其中 導體材料包括導電環氧樹脂。
  6. 如申請專利範圍第1項所述的方法，其特徵在於，其中導體材料包括導電填充材料。
  7. 如申請專利範圍第1項所述的方法，其特徵在於，其中步驟d)包括使用薄刃晶圓鋸切割相鄰兩個或多個半導體晶片之間的導體材料。
  8. 如申請專利範圍第7項所述的方法，其特徵在於，其中薄刃晶圓鋸的刃的厚度為20μm至30μm。
  9. 如申請專利範圍第1項所述的方法，其特徵在於，其中數個半導體晶片包括一個或多個垂直金屬氧化矽場效應電晶體。
  10. 如申請專利範圍第9項所述的方法，其特徵在於，其中所述的一個或多個垂直金屬氧化矽場效應電晶體包括一個或多個溝槽金屬氧化矽場效應電晶體。
  11. 如申請專利範圍第9項所述的方法，其特徵在於，其中一個或多個位於暴露背側的電極包括一個或多個漏極。
  12. 如申請專利範圍第1項所述的方法，其特徵在於，其中一個或多個位於暴露背側的電極組成一標準背側金屬。
  13. 如申請專利範圍第1項所述的方法，其特徵在於，其中一個或多個位於暴露背側的電極組成晶圓襯底上的暴露的背側部分。
  14. 如申請專利範圍第13項所述的方法，其特徵在於，還包括在去除所述劃線部分之前，對暴露的背側部分進行摻雜及退火。
  15. 如申請專利範圍第13項所述的方法，其特徵在於，還包括在應用導體材料之前，清潔晶圓表面。
  16. 一種晶片級半導體封裝結構，包括：一功率半導體晶片，包括一個或多個位於其背部及其前部的電極；一層覆蓋於所述半導體晶片背側和所述半導體晶片側壁上的導體材料，以形成封裝的最外層表面，其中導體材料層的側面還延伸到所述半導體晶片前側的邊緣。
  17. 如申請專利範圍第16項所述的封裝結構，其特徵在於，其中所述的導體材料層覆蓋所述半導體晶片的四個側壁。
  18. 如申請專利範圍第16項所述的封裝結構，其特徵在於，其中所述的前側面圖案化為基板柵格陣列。
  19. 如申請專利範圍第16項所述的封裝結構，其特徵在於，其中所述的半導體晶片包括垂直金屬氧化矽場效應電晶體。
  20. 如申請專利範圍第16項所述的封裝結構，其特徵在於，其中所述的半導體晶片包括橫向金屬氧化矽場效應電晶體晶片，其具有底部柵極和漏極以及開設於頂部的源極。
  21. 如申請專利範圍第16項所述的封裝結構，其特徵在於，其中所述的半導體晶片包括絕緣柵雙極型電晶體。
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