CN103681468A - 在Fo-WLCSP中形成双面互连结构的半导体器件和方法 - Google Patents

在Fo-WLCSP中形成双面互连结构的半导体器件和方法 Download PDF

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CN103681468A
CN103681468A CN201310155410.9A CN201310155410A CN103681468A CN 103681468 A CN103681468 A CN 103681468A CN 201310155410 A CN201310155410 A CN 201310155410A CN 103681468 A CN103681468 A CN 103681468A
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substrate
semiconductor element
conductive layer
sealant
semiconductor
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CN103681468B (zh
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林耀剑
陈康
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及在Fo-WLCSP中形成双面互连结构的半导体器件和方法。半导体器件具有基板，该基板具有在基板的相对的第一和第二表面上方形成的第一和第二导电层。多个凸块在基板上方形成。半导体管芯在凸块之间安装到基板。密封剂沉积在基板和半导体管芯上方。凸块的一部分从密封剂延伸出来。密封剂的一部分被移除以露出基板。互连结构在密封剂和半导体管芯上方形成并且电耦合到凸块。基板的一部分可以被移除以露出第一或第二导电层。基板的一部分可以被移除以露出凸块。基板可以被移除并且保护层可以在密封剂和半导体管芯上方形成。半导体封装布置在基板上方并且电连接到基板。

Description

在Fo-WLCSP中形成双面互连结构的半导体器件和方法
主张国内优先权
本专利申请主张2012年9月14日提交的美国临时申请No.61/701,366的利益，该美国临时申请通过引用接合于此。
相关申请的交叉引用
本申请涉及律师案卷号为2515.0424，名称为“Semiconductor Device and Method of Forming Build-up Interconnect Structure over Carrier for Testing at Interim stages”的美国专利申请序号(TBD)。本申请还涉及律师案卷号为2515.0427，名称为“Semiconductor Device and Method of Forming Build-up Interconnect Structure over Carrier for Testing at Interim stages”的美国专利申请序号(TBD)。
技术领域
本发明一般涉及半导体器件，且更具体地涉及一种在Fo-WLCSP中形成双面互连结构的半导体器件和方法。
背景技术
常常在现代电子产品中发现半导体器件。半导体器件在电部件的数目和密度方面变化。分立的半导体器件一般包含一种类型的电部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件典型地包含几百个到数以百万的电部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池以及数字微镜器件(DMD)。
半导体器件执行各种的功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将太阳光转变为电力以及产生用于电视显示的视觉投影。在娱乐、通信、功率转换、网络、计算机以及消费产品的领域中发现半导体器件。还在军事应用、航空、汽车、工业控制器和办公设备中发现半导体器件。
半导体器件利用半导体材料的电属性。半导体材料的结构允许通过施加电场或基电流(base current)或通过掺杂工艺而操纵其导电性。掺杂向半导体材料引入杂质以操纵和控制半导体器件的导电性。
半导体器件包含有源和无源电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和施加电场或基电流，晶体管要么促进要么限制电流的流动。包括电阻器、电容器和电感器的无源结构创建为执行各种电功能所必须的电压和电流之间的关系。无源和有源结构电连接以形成电路，这使得半导体器件能够执行高速操作和其它有用功能。
半导体器件一般使用两个复杂的制造工艺来制造，即，前端制造和和后端制造，每一个可能涉及成百个步骤。前端制造涉及在半导体晶片的表面上形成多个管芯。每个半导体管芯典型地是相同的且包含通过电连接有源和无源部件而形成的电路。后端制造涉及从完成的晶片分割(singulate)各个半导体管芯且封装管芯以提供结构支撑和环境隔离。此处使用的术语“半导体管芯”指该措词的单数和复数形式，并且相应地可以指单个半导体器件和多个半导体器件。
半导体制造的一个目的是生产较小的半导体器件。较小的器件典型地消耗较少的功率、具有较高的性能且可以更高效地生产。另外，较小的半导体器件具有较小的覆盖区(footprint)，这对于较小的终端产品而言是希望的。较小的半导体管芯尺寸可以通过前端工艺中的改进来获得，该前端工艺中的改进导致半导体管芯具有较小、较高密度的有源和无源部件。后端工艺可以通过电互联和封装材料中的改进而导致具有较小覆盖区的半导体器件封装。
半导体管芯在扇出晶片级芯片规模封装(Fo-WLCSP)中经常需要顶部和底部堆积互连结构以用于电连接到外部器件。堆积互连结构典型地逐层形成于Fo-WLCSP的两侧上。由于工业标准临时接合工艺的原因，堆积互连结构的逐层形成需要长的循环时间和高的制造成本。临时接合可能降低制造良率并且增加缺陷。
发明内容
对于一种简单和成本有效的Fo-WLCSP中的双面互连结构存在需求。因此，在一个实施例中，本发明为一种制作半导体器件的方法，该方法包括步骤：提供基板，该基板包括在基板的相对的第一和第二表面上方形成的第一和第二导电层；在基板上方形成多个凸块；在凸块之间将半导体管芯安装到基板；在基板和半导体管芯上方沉积密封剂；以及形成位于密封剂和半导体管芯上方并且电耦合到凸块的互连结构。
在另一实施例中，本发明为一种制作半导体器件的方法，该方法包括步骤：提供基板；在基板上方形成垂直互连结构；将半导体管芯安装到基板；在基板和半导体管芯上方沉积密封剂；以及在密封剂和半导体管芯上方形成第一互连结构。
在另一实施例中，本发明为一种半导体器件，其包括基板和在基板上方形成的垂直互连结构。半导体管芯安装到基板。密封剂沉积在基板和半导体管芯上方。第一互连结构在密封剂和半导体管芯上方形成。
在另一实施例中，本发明为一种半导体器件，其包括基板和安装到基板的半导体管芯。密封剂沉积在基板和半导体管芯上方。第一互连结构在密封剂和半导体管芯上方形成。
附图说明
图1说明不同类型的封装安装到其表面的印刷电路板(PCB)；
图2a-2c说明安装到PCB的代表性半导体封装的另外细节；
图3a-3e说明具有通过锯道分离的多个半导体管芯的半导体晶片；
图4a-4d说明形成内插层基板的工艺，半导体管芯安装到该基板；
图5a-5i说明在Fo-WLCSP中形成内插层基板和堆积互连结构作为双面互连结构的工艺；
图6a-6b说明安装到具有双面互连结构的Fo-WLCSP的半导体封装；
图7说明内插层基板，其中导电层仅仅位于该基板的一侧上；
图8说明内插层基板，其中掩模层位于该基板的一侧上；
图9说明内插层基板，其中凸块的侧表面露出；以及
图10说明具有层叠保护层的内插层基板。
具体实施方式
在下面的描述中，参考图以一个或更多实施例描述本发明，在这些图中相似的标号代表相同或类似的元件。尽管就用于实现本发明目的的最佳模式描述本发明，但是本领域技术人员应当理解，其旨在覆盖可以包括在如下面的公开和图支持的所附权利要求及其等价物限定的本发明的精神和范围内的替换、修改和等价物。
半导体器件一般使用两个复杂制造工艺来制造：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电部件，它们电连接以形成功能电路。诸如晶体管和二极管的有源电部件具有控制电流流动的能力。诸如电容器、电感器和电阻器的无源电部件创建为执行电路功能所必须的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻和平坦化的一系列工艺步骤在半导体晶片的表面上方形成无源和有源部件。掺杂通过诸如离子注入或热扩散的技术将杂质引入到半导体材料中。通过响应于电场或基电流而动态地改变半导体材料的导电性，掺杂工艺修改了有源器件中半导体材料的导电性。晶体管包含不同类型和掺杂程度的区域，其按照需要被布置为使得当施加电场或基电流时晶体管能够促进或限制电流的流动。
通过具有不同电属性的材料层形成有源和无源部件。层可以通过部分由被沉积的材料类型确定的各种沉积技术来形成。例如，薄膜沉积可以涉及化学汽相沉积(CVD)、物理汽相沉积(PVD)、电解镀覆和化学镀覆工艺。每一层一般被图案化以形成有源部件、无源部件或部件之间的电连接的部分。
后端制造指将完成的晶片切割或分割为各个半导体管芯且然后封装半导体管芯以用于结构支撑和环境隔离。为了分割半导体管芯，晶片沿着称为锯道或划线的晶片的非功能区域被划片且折断。使用激光切割工具或锯条来分割晶片。在分割之后，各个半导体管芯被安装到封装基板，该封装基板包括引脚或接触焊盘以用于与其它系统部件互连。在半导体管芯上方形成的接触焊盘然后连接到封装内的接触焊盘。电连接可以使用焊料凸块、柱形凸块、导电膏料或引线接合来制成。密封剂或其它成型材料沉积在封装上方以提供物理支撑和电隔离。完成的封装然后被插入到电系统中且使得半导体器件的功能性对于其它系统部件可用。
图1说明具有芯片载体基板或印刷电路板(PCB)52的电子器件50，该芯片载体基板或印刷电路板(PCB)52具有安装在其表面上的多个半导体封装。取决于应用，电子器件50可以具有一种类型的半导体封装或多种类型的半导体封装。用于说明性目的，在图1中示出了不同类型的半导体封装。
电子器件50可以是使用半导体封装以执行一个或更多电功能的独立系统。替换地，电子器件50可以是较大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理(PDA)、数码摄像机(DVC)或其它电子通信器件的一部分。替换地，电子器件50可以是图形卡、网络接口卡或可以被插入到计算机中的其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件或其它半导体管芯或电部件。微型化和重量减小对于该产品被市场接受是至关重要的。半导体器件之间的距离必须减小以实现更高的密度。
在图1中，PCB 52提供用于安装到PCB上的半导体封装的结构支撑和电互连的一般性基板。使用蒸发、电解镀覆、化学镀覆、丝网印刷或者其它合适的金属沉积工艺，导电信号迹线54在PCB 52的表面上方或其层内形成。信号迹线54提供半导体封装、安装的部件以及其它外部系统部件中的每一个之间的电通信。迹线54还向半导体封装中的每一个提供功率和接地连接。
在一些实施例中，半导体器件具有两个封装级别。第一级封装是用于机械和电附着半导体管芯到中间载体的技术。第二级封装涉及机械和电附着中间载体到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被直接机械和电地安装到PCB。
用于说明目的，在PCB 52上示出包括接合引线封装56和倒装芯片58的若干类型的第一级封装。另外，示出在PCB 52上安装的若干类型的第二级封装，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、岸面栅格阵列(LGA)66、多芯片模块(MCM)68、四方扁平无引脚封装(QFN)70以及方形扁平封装72。取决于系统需求，使用第一和第二级封装类型的任何组合配置的半导体封装以及其它电子部件的任何组合可以连接到PCB 52。在一些实施例中，电子器件50包括单一附着的半导体封装，而其它实施例需要多个互连封装。通过在单个基板上方组合一个或更多半导体封装，制造商可以将预制部件接合到电子器件和系统中。因为半导体封装包括复杂的功能性，可以使用较不昂贵的部件和流水线制造工艺来制造电子器件。所得到的器件较不倾向于发生故障且对于制造而言较不昂贵，导致针对消费者的较少的成本。
图2a-2c示出示例性半导体封装。图2a说明安装在PCB 52上的DIP 64的进一步细节。半导体管芯74包括有源区域，该有源区域包含实现为根据管芯的电设计而在管芯内形成且电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及在半导体管芯74的有源区域内形成的其它电路元件。接触焊盘76是诸如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag)的一层或多层导电材料，且电连接到半导体管芯74内形成的电路元件。在DIP 64的组装期间，半导体管芯74使用金-硅共熔层或者诸如热环氧物或环氧树脂的粘合剂材料而安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导线80和接合引线82提供半导体管芯74和PCB 52之间的电互连。密封剂84沉积在封装上方，以通过防止湿气和颗粒进入封装且污染半导体管芯74或接合引线82而进行环境保护。
图2b说明安装在PCB 52上的BCC 62的进一步细节。半导体管芯88使用底层填料或者环氧树脂粘合剂材料92而安装在载体90上方。接合引线94提供接触焊盘96和98之间的第一级封装互连。模塑料或密封剂100沉积在半导体管芯88和接合引线94上方，从而为器件提供物理支撑和电隔离。接触焊盘102使用诸如电解镀覆或化学镀覆之类的合适的金属沉积工艺而在PCB 52的表面上方形成以防止氧化。接触焊盘102电连接到PCB 52中的一个或更多导电信号迹线54。凸块104在BCC 62的接触焊盘98和PCB 52的接触焊盘102之间形成。
在图2c中，使用倒装芯片类型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区域108包含实现为根据管芯的电设计而形成的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及有源区域108内的其它电路元件。半导体管芯58通过凸块110电和机械连接到载体106。
使用利用凸块112的BGA类型第二级封装，BGA 60电且机械连接到PCB 52。半导体管芯58通过凸块110、信号线114和凸块112电连接到PCB 52中的导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上方以为器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容且改善整体电路性能。在另一实施例中，半导体管芯58可以使用倒装芯片类型第一级封装来直接机械和电地连接到PCB 52而不使用中间载体106。
图3a示出具有用于结构支撑的基底基板材料122的半导体晶片120，该基底基板材料诸如是硅、锗、砷化镓、磷化铟或者碳化硅。如上所述，在晶片120上形成通过非有源的管芯间晶片区域或锯道126分离的多个半导体管芯或组件124。锯道126提供切割区域以将半导体晶片120分割成各个半导体管芯124。
图3b示出半导体晶片120的一部分的剖面图。每个半导体管芯124具有背表面128和有源表面130，该有源表面包含实现为根据管芯的电设计和功能而在管芯内形成且电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多个晶体管、二极管以及在有源表面130内形成的其它电路元件以实现诸如数字信号处理器(DSP)、ASIC、存储器或其它信号处理电路之类的模拟电路或数字电路。半导体管芯124还可以包含诸如电感器、电容器和电阻器的集成无源器件(IPD)以用于RF信号处理。
使用PVD、CVD、电解镀覆、化学镀覆工艺或其它合适的金属沉积工艺而在有源表面130上方形成导电层132。导电层132可以是Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料的一层或更多层。导电层132操作为电连接到有源表面130上的电路的接触焊盘。导电层132可以形成为这样的接触焊盘，其距半导体管芯124的边缘第一距离而并排布置，如图3b所示。替换地，导电层132可以形成为这样的接触焊盘，其在多个行中偏移，使得接触焊盘的第一行距管芯边缘第一距离布置，并且接触焊盘的与第一行交替的第二行距管芯边缘第二距离布置。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化，在有源表面130和导电层132上方形成绝缘或钝化层134。绝缘层134包含二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)或具有相似结构和绝缘属性的其它材料的一个或更多个层。使用激光器136通过激光直接消融(LDA)移除绝缘层134的一部分以露出导电层132。替换地，利用蚀刻工艺通过图案化光致抗蚀剂层移除绝缘层134的一部分以露出导电层132。
在图3c中，半导体晶片120的后表面128经历使用研磨器137的背部研磨操作，接着是抛光步骤以减小晶片的厚度。在图3d中，在分割之前，管芯附着粘合膜或带138被层叠到经抛光的后表面128。
在图3e中，使用锯条或激光切割工具139通过锯道126将半导体晶片120分割为单独的半导体管芯124。
图4a-4d说明内插层基板的形成，其中半导体管芯安装到该基板。图4a示出核心基板140，其包括聚四氟乙烯预浸渍(预浸料)、FR-4、FR-1、CEM-1或CEM-3的一个或更多个层叠的层与酚醛棉纸、环氧物、树脂、织物玻璃、毛玻璃、聚酯以及其它增强纤维或纺织品的组合。替换地，核心基板140包含一个或更多个绝缘或电介质层。
使用激光钻孔、机械钻孔或深反应离子蚀刻(DRIE)，形成穿过核心基板140的多个穿通孔。使用电解镀覆、化学镀覆工艺或其它合适沉积工艺，用Al、Cu、Sn、Ni、Au、Ag、钛(Ti)、钨(W)或其它合适导电材料填充通孔以形成z方向垂直互连导电通孔144。在一个实施例中，通过化学镀覆和电解镀覆在穿通孔的侧壁上方沉积Cu。使用具有填料的导电膏或堵漏树脂填充穿通孔。
使用诸如Cu箔层叠、印刷、PVD、CVD、溅射、电解镀覆和化学镀覆的图案化和金属沉积工艺,在核心基板140的第一表面和导电通孔144上方形成导电层或再分配层(RDL)146。导电层146包括Al、Cu、Sn、Ni、Au、Ag或其它合适导电材料的一个或更多个层。导电层146电连接到导电通孔144。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化，在核心基板140的第一表面和导电层146上方形成绝缘或钝化层148。绝缘层148包含具有或不具有填料或纤维的SiO2、Si3N4、SiON、Ta2O5、Al2O3、二氧化铪(HfO2)、苯并环丁烯(BCB)、聚酰亚胺(PI)、聚苯并恶唑(PBO)、聚合物电介质抗蚀剂或具有相似结构和电介质属性的其它材料的一个或更多个层。
使用诸如Cu箔层叠、印刷、PVD、CVD、溅射、电解镀覆和化学镀覆的图案化和金属沉积工艺，在导电通孔144上方以及核心基板140的与第一表面相对的第二表面上方形成导电层或RDL 150。导电层150包括Al、Cu、Sn、Ni、Au、Ag或其它合适导电材料的一个或更多个层。导电层150电连接到导电通孔144和导电层146。在另一实施例中，在形成导电层146和/或导电层150之后，形成穿过核心基板140的导电通孔144。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化，在核心基板140的第二表面和导电层150上方形成绝缘或钝化层152。绝缘层152包含具有或不具有填料或纤维的SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、聚合物电介质抗蚀剂或具有相似结构和电介质属性的其它材料的一个或更多个层。使用激光器154通过LDA移除绝缘层152的一部分以露出导电层150。替换地，利用蚀刻工艺通过图案化光致抗蚀剂层移除绝缘层152的一部分以露出导电层150。
得到的内插层基板155根据半导体管芯124的电功能提供垂直和横向跨过基板穿过导电层146和150以及导电通孔144的电互连。在中期阶段，即在安装半导体管芯124之前，通过开路/短路探针或自动范围检查来检测和测试基板155是已知良好的。根据半导体管芯124的设计和功能，导电层146和150以及导电通孔144的其它部分是电共同的或电隔离的。
基板155也可以是多层柔性层叠、陶瓷、铜箔、玻璃或包括有源表面的半导体晶片，该有源表面包含一个或更多个晶体管、二极管和其它电路元件以实施模拟电路或数字电路。
在图4b中，使用蒸发、电解镀覆、化学镀覆、球滴或丝网印刷工艺，在导电层150上方沉积导电凸块材料。凸块材料可以是具有可选的助焊剂溶液的Al、Sn、Ni、Au、Ag、铅(Pb)、Bi、Cu、焊料以及其组合。例如凸块材料可以是共晶Sn/Pb、高铅焊料、Cu核心焊球、在球安装中具有焊膏的Cu球、或者无铅焊料。使用合适的附着或接合工艺，将凸块材料接合到导电层150。在一个实施例中，凸块材料通过将材料加热到其熔点之上而进行回流以形成圆球或凸块156。在一些应用中，凸块156被二次回流以改善与导电层150的电接触。在一个实施例中，凸块156形成于具有润湿层、阻挡层和粘合层的UBM上方。凸块156也可以被压缩接合或热压接合到导电层150。凸块156代表可以在导电层150上方形成的一种类型的互连结构。该互连结构也可以使用接合引线、导电膏、柱形凸块、微凸块或其它电互连。
在图4c中，来自图3c的半导体管芯124使用例如拾放操作以后表面128朝向基板取向的方式安装到内插层基板155。半导体管芯124利用管芯附着粘合剂或膜138被紧固到基板155。图4d示出半导体管芯124，其安装到基板155并且布置在凸块156之间以及至少部分在凸块156的高度之内。半导体管芯124为在安装到基板155之前已经被测试的已知良好的管芯(KGD)。基板155具有足够尺寸以容纳多个半导体管芯。基板155被分割为单独的半导体管芯124，每个半导体管芯具有关联的内插层基板155和凸块156。不需要附加的抛光以节省成本并且减小循环时间。
与图1和2a-2c相关联，图5a-5i说明在Fo-WLCSP中形成内插层基板和堆积互连结构作为双面互连结构的工艺。图5a示出载体或临时基板160，其包含诸如硅、聚合物、氧化铍、玻璃或其它合适的低成本刚性材料的可重复使用或牺牲基底材料以用于结构支撑。包括可选的附加粘合剂或可压缩释放层164的界面层或双面胶带162形成于载体160上方作为临时粘合接合膜、蚀刻停止层或热释放层。以凸块156朝向载体取向的方式，基板155安装到载体160上的可压缩释放膜164。图5b示出基板155，其中半导体管芯124安装到载体160。半导体管芯124的导电层132和绝缘层134以及凸块156的可选部分被嵌入载体160上的可压缩释放膜164。
在图5c中，使用膏料印刷、压缩成形、转移成形、液体密封剂成形、真空层叠、旋涂或其它合适涂料器，将密封剂或模塑料168沉积在载体160、基板155和半导体管芯124上方。密封剂168可以是聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙稀酸脂或者具有适当填料的聚合物。在一个实施例中，密封剂168配给在四个相邻基板155的相交处。密封剂168不导电并且在环境上保护半导体器件免受外部要素和污染。特别地，密封剂168的填料和热膨胀系数(CTE)被选择以辅助间隙填充、翘曲控制和可靠性。
在图5d中，通过化学蚀刻、机械剥离、化学机械平坦化(CMP)、机械研磨、热焙、UV光、激光扫描或湿法剥落，移除载体160、界面层162和可压缩释放膜164，留下半导体管芯124的导电层132和绝缘层134以及从密封剂168露出的凸块156的一部分。可以应用附加的背部研磨以控制翘曲。可以应用可选的激光阴影钻孔或清洗从而露出凸块156用于互连或良好接触电阻。
在图5e中，使用PVD、CVD、印刷、狭缝涂布、旋涂、喷涂、层叠、烧结或热氧化，在半导体管芯124、凸块156和密封剂168上方形成绝缘或钝化层170。绝缘层170包含具有或不具有填料或纤维的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物电介质抗蚀剂或具有相似结构和绝缘属性的其它材料的一个或更多个层。通过LDA移除绝缘层170的一部分以露出导电层132和凸块156。替换地，通过图案化的光致抗蚀剂层移除绝缘层170的一部分以露出导电层132和凸块156。
使用PVD、CVD、电解镀覆、化学镀覆工艺或其它合适金属沉积工艺，在导电层132、凸块156和绝缘层170上方形成导电层172。导电层172可以是Al、Ti、TiW、Cu、Sn、Ni、Au、Ag或其它合适导电材料的一个或更多个层。导电层172的一个部分电连接到导电层132。导电层172的另一部分电连接到凸块156。导电层172的其它部分可以是电共同的或电隔离的，取决于半导体管芯124的设计和功能。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝涂布、层叠、烧结或热氧化，在绝缘层170和导电层172上方形成绝缘或钝化层174。绝缘层174包含具有或不具有填料或纤维的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物电介质抗蚀剂或具有相似结构和绝缘属性的其它材料的一个或更多个层。通过LDA或者利用蚀刻工艺通过图案化光致抗蚀剂层，移除绝缘层174的一部分以露出导电层172。
使用PVD、CVD、电解镀覆、化学镀覆工艺或其它合适金属沉积工艺，在导电层172和绝缘层174上方形成导电层176。导电层176可以是Al、Ti、TiW、Cu、Sn、Ni、Au、Ag或其它合适导电材料的一个或更多个层。导电层176的一部分电连接到导电层172。导电层176的其余部分可以是电共同的或电隔离的，取决于半导体管芯124的设计和功能。
使用PVD、CVD、印刷、旋涂、喷涂、狭缝涂布、层叠、烧结或热氧化，在绝缘层174和导电层176上方形成绝缘或钝化层178。绝缘层178包含具有或不具有填料或纤维的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物电介质抗蚀剂或具有相似结构和绝缘属性的其它材料的一个或更多个层。使用激光器180通过LDA移除绝缘层178的一部分以露出导电层176。替换地，利用蚀刻工艺通过图案化光致抗蚀剂层移除绝缘层178的一部分以露出导电层176。
在图5f中，使用蒸发、电解镀覆、化学镀覆、球滴或丝网印刷工艺，在露出的导电层176上方沉积导电凸块材料。凸块材料可以是具有可选的助焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及其组合。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适附着或接合工艺，将凸块材料接合到导电层176。在一个实施例中，凸块材料通过将材料加热到其熔点之上而进行回流以形成圆球或凸块182。在一些应用中，凸块182被二次回流以改善与导电层176的电接触。在一个实施例中，凸块182形成于具有润湿层、阻挡层和粘合层的UBM上方。凸块182也可以被压缩接合或热压接合到导电层176。凸块182代表可以在导电层172上方形成的一种类型的互连结构。该互连结构也可以使用接合引线、导电膏、柱形凸块、微凸块或其它电互连。
绝缘层170、174和178，导电层172和176以及凸块182的组合构成堆积互连结构184。在附加器件集成之前，检测和测试该堆积互连结构184是已知良好。
在图5g中，背部研磨或支撑带186被应用在绝缘层178和凸块182上方。在利用研磨器188的研磨操作中移除密封剂168的一部分，从而平坦化表面并露出基板155的绝缘层148。化学蚀刻或CMP工艺也可以用于移除由于研磨操作引起的机械损伤并且平坦化密封剂168。
在图5h中，使用激光器190通过LDA移除绝缘层148的一部分，从而露出基板155的导电层146用于电互连到外部半导体器件。
在图5i中，基板155被层叠并且背部研磨或支撑带186被移除。使用锯条或激光切割工具196，穿过密封剂168和堆积互连结构184将半导体管芯124分割为单独的双面Fo-WLCSP 198。图6a示出分割之后的Fo-WLCSP 198。半导体管芯124通过堆积互连结构184和凸块156电连接到基板155，以用于连接到外部器件。基板155和堆积互连结构184提供用于Fo-WLCSP 198的相对侧(双侧)上的半导体管芯124的垂直和横向互连。基板155在不同时间形成并且与堆积互连结构184分离。在管芯安装之前的基板155的形成和测试简化了制造工艺并且降低成本。后来形成堆积互连结构184连同提供基板155和堆积互连结构之间的垂直互连的凸块156，这完成了用于Fo-WLCSP 198的相对侧上的半导体管芯124的垂直和横向互连。
图6a还包括半导体封装200，其包括具有有源表面204的半导体管芯202，该有源表面包含实现为根据管芯的电设计和功能而在管芯中形成且电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可包括一个或更多个晶体管、二极管以及在有源表面204内形成的其它电路元件以实现诸如DSP、ASIC、存储器或其它信号处理电路之类的模拟电路或数字电路。半导体管芯202还可以包含诸如电感器、电容器和电阻器的IPD以用于RF信号处理。在一个实施例中，半导体管芯202为球栅阵列(BGA)类型器件。
半导体管芯202安装到包括导电迹线208的基板206。接合引线210在半导体管芯202的有源表面204上形成于导电迹线208和接触焊盘212之间。密封剂214沉积在半导体管芯202、基板206和接合引线210上方。凸块216形成于与半导体管芯202相对的基板206的导电迹线208上方。基板206以凸块216朝向Fo-WLCSP取向的方式安装到Fo-WLCSP 198。图6b示出安装到Fo-WLCSP 198的基板206，其中凸块216机械和电连接到导电层146。
图7说明Fo-WLCSP 220的实施例，类似于图5a-5i，其具有核心基板140、导电层150和绝缘层152。类似于图5g，密封剂168和核心基板140的一部分在研磨操作中被移除从而平坦化表面。使用激光器222通过LDA移除核心基板140的一部分，从而露出导电层150用于电互连到外部半导体器件。
在一个实施例中，核心基板140、导电层150和绝缘层152堆积在诸如Si、低CTE玻璃(小于8ppm)的低CTE基板上，并且为了处理和翘曲控制目的，在封装工艺期间与低CTE基板一起嵌在密封剂168中。在形成凸块182之后，低CTE基板部分通过背部研磨被移除以露出核心基板140和导电层150。
图8说明Fo-WLCSP 230的实施例，类似于图5a-5i，其具有核心基板140和导电层150。掩模层232在核心基板140和导电层150上方形成。类似于图5g，在研磨操作中移除密封剂168和核心基板140的一部分从而平坦化表面。使用激光器234通过LDA移除核心基板140的一部分，从而露出导电层150用于电互连到外部半导体器件。
在一个实施例中，核心基板140、导电层150和掩模层232堆积在诸如Si、低CTE玻璃(小于8ppm)的低CTE基板上，并且为了处理和翘曲控制目的，在封装工艺期间与低CTE基板一起嵌在密封剂168中。在形成凸块182之后，低CTE基板部分通过背部研磨被移除以露出核心基板140和导电层150。
图9说明Fo-WLCSP 240的实施例，类似于图5a-5i，其具有在核心基板140上方形成的掩模层242。类似于图5g，密封剂168和核心基板140的一部分在研磨操作中被移除从而平坦化表面。使用激光器244通过LDA移除核心基板140的一部分，从而露出凸块156的侧表面用于电互连到外部半导体器件。选择具有恰当CTE和机械属性的核心基板140和掩模层242从而平衡Fo-WLCSP 240翘曲，并且增大增强最终封装的机械强度。
在一个实施例中，核心基板140和掩模层242堆积在诸如Si、低CTE玻璃(小于8ppm)的低CTE基板上，并且为了处理和翘曲控制目的，在封装工艺期间与低CTE基板一起嵌在密封剂168中。在形成凸块182之后，低CTE基板部分通过背部研磨被移除以露出核心基板140。
图10说明Fo-WLCSP 250的实施例，类似于图5a-5i，其具有在密封剂168和半导体管芯124上方形成的层叠保护层252。使用激光器254通过LDA移除层叠保护层252的一部分，从而露出凸块156的侧表面用于电互连到外部半导体器件。选择具有恰当CTE、厚度和机械强度的层叠保护层252以平衡Fo-WLCSP 250的翘曲和支撑。
在一个实施例中，层叠保护层252堆积在诸如Si、低CTE玻璃(小于8ppm)的低CTE基板上，并且为了处理和翘曲控制目的，在封装工艺期间与低CTE基板一起嵌在密封剂168中。在形成凸块182之后，低CTE基板部分通过背部研磨被移除。
尽管已经详细说明了本发明的一个或更多实施例，但是本领域技术人员应当意识到，可以在不偏离如随后的权利要求提及的本发明的范围的情况下对那些实施例做出修改和改写。

Claims (15)

1.一种制作半导体器件的方法，包括：
提供基板，该基板包括在基板的相对的第一和第二表面上方形成的第一和第二导电层；
在基板上方形成多个凸块；
在凸块之间将半导体管芯安装到基板；
在基板和半导体管芯上方沉积密封剂；以及
形成位于密封剂和半导体管芯上方并且电耦合到凸块的互连结构。
2.权利要求1的方法，还包括：
在基板的第一表面和第一导电层上方形成第一绝缘层；以及
在基板的第二表面和第二导电层上方形成第二绝缘层。
3.权利要求1的方法，还包括移除密封剂的一部分以露出基板。
4.权利要求1的方法，其中凸块的一部分从密封剂延伸出来。
5.一种制作半导体器件的方法，包括：
提供基板；
在基板上方形成垂直互连结构；
将半导体管芯安装到基板；
在基板和半导体管芯上方沉积密封剂；以及
在密封剂和半导体管芯上方形成第一互连结构。
6.权利要求5的方法，其中基板包括在基板的相对的第一和第二表面上方形成的第一和第二导电层。
7.权利要求6的方法，还包括：
在基板的第一表面和第一导电层上方形成第一绝缘层；以及
在基板的第二表面和第二导电层上方形成第二绝缘层。
8.权利要求7的方法，还包括通过激光直接消融移除第一绝缘层或第二绝缘层的一部分。
9.权利要求5的方法，还包括：
移除基板；
在密封剂和半导体管芯上方形成保护层；以及
移除保护层的一部分以露出垂直互连结构。
10.一种半导体器件，包括：
基板；
在基板上方形成的垂直互连结构；
安装到基板的半导体管芯；
沉积在基板和半导体管芯上方的密封剂；以及
在密封剂和半导体管芯上方形成的第一互连结构。
11.权利要求10的半导体器件，其中该基板包括在基板的相对的第一和第二表面上方形成的第一和第二导电层。
12.权利要求11的半导体器件，还包括：
在基板的第一表面和第一导电层上方形成的第一绝缘层；以及
在基板的第二表面和第二导电层上方形成的第二绝缘层。
13.权利要求10的半导体器件，其中垂直互连结构的一部分从密封剂延伸出来。
14.权利要求10的半导体器件，其中垂直互连结构包括多个凸块。
15.权利要求10的半导体器件，还包括布置在基板上方并且电连接到基板的半导体封装。
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