CN111627867A - 芯片封装结构及其制作方法 - Google Patents

芯片封装结构及其制作方法 Download PDF

Info

Publication number
CN111627867A
CN111627867A CN201910153370.1A CN201910153370A CN111627867A CN 111627867 A CN111627867 A CN 111627867A CN 201910153370 A CN201910153370 A CN 201910153370A CN 111627867 A CN111627867 A CN 111627867A
Authority
CN
China
Prior art keywords
layer
protective layer
chip
openings
circuit resetting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910153370.1A
Other languages
English (en)
Inventor
倪庆羽
呂香桦
刘扬伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qingdao New Core Technology Co ltd
Futaihua Industry Shenzhen Co Ltd
Original Assignee
Futaihua Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Futaihua Industry Shenzhen Co Ltd, Hon Hai Precision Industry Co Ltd filed Critical Futaihua Industry Shenzhen Co Ltd
Priority to CN201910153370.1A priority Critical patent/CN111627867A/zh
Priority to US16/398,746 priority patent/US11056411B2/en
Publication of CN111627867A publication Critical patent/CN111627867A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种芯片封装结构，包括一第一防护层、一形成在所述第一防护层上的线路重置层、一与所述线路重置层电连接的芯片及一包覆所述线路重置层及所述芯片的封胶体，所述第一防护层包括一外露表面及与所述外露表面相连接的至少四个侧边，所述封胶体包括一封胶表面；所述封胶体还包覆所述第一防护层的至少四个侧边。本发明提供的芯片封装结构能够避免所述线路重置层及第一防护层被外力破坏，增强所述芯片封装结构的可靠性。

Description

芯片封装结构及其制作方法
技术领域
本发明涉及芯片封装领域，尤其涉及一种芯片封装结构及其制作方法。
背景技术
随着集成电路的功能越来越强，集成度越来越高，封装技术在集成电路产品中扮演着越来越重要的角色，在整个电子系统的价值中所占的比例也越来越大。同时，随着集成电路特征尺寸达到纳米级，芯片向更高密度、更高时钟频率发展，封装也向更高密度的方向发展。
由于扇出晶圆级封装(flow)技术具有小型化、低成本、高集成度及具有更好的性能和更高的能源效率等优点，因此，扇出晶圆级封装技术已成为高要求的移动/无线网络等电子设备的重要封装方法，是目前最具有发展前景的封装技术之一。
然而，现有的芯片封装结构的封胶体仅包覆芯片的四周，重新布线层及防护层(常用的为polyimide，PI层)则裸露在所述封胶体外，使得所述封胶体的侧边与重新布线层及覆盖膜层的侧边之间出现高低差，从而导致所述重新布线层及覆盖膜层容易被外力破坏，造成所述芯片封装结构的可靠性变差。
发明内容
有鉴于此，本发明提供一种能够防止重新布线层及防护层被外力破坏、增强可靠性的芯片封装结构。
还有必要提供一种防止重新布线层及防护层被外力破坏、增强可靠性的芯片封装结构的制作方法。
一种芯片封装结构，包括一第一防护层、一形成在所述第一防护层上的线路重置层、一与所述线路重置层电连接的芯片及一包覆所述线路重置层及所述芯片的封胶体，所述第一防护层包括一外露表面及与所述外露表面相连接的至少四个侧边，所述封胶体包括一封胶表面；所述封胶体还包覆所述第一防护层的至少四个侧边。
进一步地，所述第一防护层上形成有多个第一开口，部分所述线路重置层从所述第一开口内裸露出来，一个所述第一开口内形成有一个焊球，所述焊球与所述线路重置层电连接。
进一步地，所述芯片封装结构还包括一第二防护层，所述第二防护层形成在所述线路重置层上且包覆所述线路重置层，所述第二防护层上形成有多个第二开口，部分所述线路重置层从所述第二开口内裸露出来，所述第二开口内形成有电接触垫。
进一步地，每一个第二开口内形成有一个电接触垫，每一个所述芯片还形成有多个导电凸块，所述导电凸块固接在所述电接触垫上，一个所述导电凸块对应一个所述电接触垫。
进一步地，所述第一防护层的外露表面与所述封胶体的封胶表面平齐。
进一步地，所述封胶体的材质为环氧塑封料。
一种芯片封装结构的制作方法，包括如下步骤：提供一承载基板；在所述承载基板的表面上形成一第一防护层及在所述第一防护层上形成一线路重置层，所述第一防护层包括一与所述承载基板相贴的外露表面；提供至少一芯片，并将所述芯片与所述线路重置层电性连接；形成一封胶体并使得所述封胶体包覆所述第一防护层、所述线路重置层及所述芯片，所述封胶体包括一与所述承载基板相贴的封胶表面；及移除所述承载基板，得到所述芯片封装结构。
进一步地，所述第一防护层上形成有多个第一开口，部分所述线路重置层从所述第一开口内裸露出来，在移除所述承载基板的步骤之后还包括步骤：在每一个所述第一开口内形成一个焊球，所述焊球与所述线路重置层电连接。
进一步地，在形成线路重置层之后，还包括步骤：形成一包覆所述线路重置层的第二防护层，所述第二防护层上形成有多个第二开口，部分所述线路重置层分别从所述第二开口内裸露出来；及在所述第二开口内形成电接触垫，一个第二开口内形成一个电接触垫；一个所述芯片上还形成有多个导电凸块，所述导电凸块固接在所述电接触垫上，一个所述导电凸块对应一个所述电接触垫。
进一步地，所述封胶体的封胶表面与所述第一防护层的外露表面相平齐。
本发明提供的芯片封装结构及其制作方法，将所述线路重置层及形成在所述线路重置层上的所述第一防护层的至少四个侧边包覆在所述封胶体内，从而能够避免所述线路重置层及第一防护层被外力破坏，进而增强所述芯片封装结构的可靠性。
附图说明
图1为本发明一实施例提供的一承载基板的剖面示意图。
图2为在图1所示的承载基板的表面形成一第一防护层、一线路重置层及一第二防护层后的剖面示意图。
图3为在图2所示的第二防护层的表面贴附一芯片后的剖面示意图。
图4为将图3所示的芯片、线路重置层、第一防护层及第二防护层包覆在一封胶体内之后的剖面示意图。
图5为去除图4所示的承载基板，得到一封装中间体之后的剖面示意图。
图6为在图5所示的第一防护层表面形成焊球，得到一芯片封装结构后的剖面示意图。
主要元件符号说明
Figure BDA0001982132910000031
Figure BDA0001982132910000041
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅是本发明一部分实施方式，而不是全部的实施方式。基于本发明中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本发明保护的范围。
需要说明的是，当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中设置的元件。当一个元件被认为是“设置于”另一个元件，它可以是直接设置在另一个元件上或者可能同时存在居中设置的元件。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本发明。
请参阅图1-6，本发明较佳实施方式提供一种芯片封装结构的制作方法，包括如下步骤：
第一步，请参阅图1，提供一承载基板10。所述承载基板10包括一承载板11及一形成在所述承载板11上的离型膜层12。
所述承载板11的材质为任何一种绝缘的具有承载作用的材料。在本实施例中，所述承载板11的材质为聚酰亚胺(polyimide，PI)。在其他实施例中，所述承载板11的材质还可以为聚对苯二甲酸乙二醇酯(Polyethylene Terephthalate，PET)、聚萘二甲酸乙二醇酯(Polyethylene Naphthalate，PEN)或其他树脂硬质材料或陶瓷板、金属板等。
所述离型膜层12包括一第一表面121，所述第一表面121与所述承载板11相背。
所述离型膜层12的材质可以为聚乙烯(polyethylene，PE)、聚对苯二甲酸乙二醇酯(polyethylene terephthalate，PET)、定向聚丙烯(oriented polypropylene，OPP)、聚碳酸酯(Polycarbonate，PC)、聚苯乙烯(polystyrene，PS)、聚甲基丙烯酸甲脂(polymethylmethacrylate，PMMA)、双轴向聚丙烯(Biaxially-oriented Polypropylene，BOPP)、聚甲基戊(Poly-4-methyl-1-pentene，TPX)、聚氯乙烯(polyvinyl chloride，PVC)、聚四氟乙烯(polytetrafluoroethylene，PTFE)、单硅或聚脂中任意一种或至少两种的组合。在本实施方式中，所述离型膜层12优选为PET离型膜。
第二步，请参阅图2，在所述离型膜层12的第一表面121上形成一第一防护层20、在所述第一防护层20上形成一线路重置层(redistribution layer，RDL)30及形成一包覆所述线路重置层30的第二防护层40。
所述第一防护层20上形成有多个第一开口21，所述第二防护层40上形成有多个第二开口41，部分所述线路重置层30分别从所述第一开口21及所述第二开口41内裸露出来。
所述第一防护层20可以为覆盖膜层，也可以为防焊层。在本实施方式中，所述第一防护层20为覆盖膜层。优选地，所述第一防护层20为聚酰亚胺(polyimide，PI)覆盖膜层。
所述第一防护层20包括一外露表面22及与所述外露表面22相连接的至少四个侧边23，所述外露表面22与所述第一表面121相接触。
所述线路重置层30可以通过电镀或影像转移制程制作而成。所述线路重置层30用于安装外部电子元件或与外部电子元件通信连接。
所述第二防护层40用于保护所述线路重置层30。
所述第二防护层40可以为覆盖膜层，也可以为防焊层。在本实施方式中，所述第二防护层40为覆盖膜层。优选地，所述第二防护层40为聚酰亚胺(polyimide，PI)覆盖膜层。
第三步，请参阅图3，在所述第二开口41内形成电接触垫50，提供至少一芯片60并将所述芯片60通过所述电接触垫50固接在所述第二防护层40上，所述芯片60与所述线路重置层30通过所述电接触垫50电性连接。
所述芯片60包括一第二表面61，所述第二表面61面向所述第二防护层40且平行于所述第二防护层40。所述第二表面61上还形成有多个导电凸块62，所述导电凸块62固接在所述电接触垫50上。一个所述导电凸块62对应一个所述电接触垫50。
第四步，请参阅图4，在所述承载基板10的形成有线路重置层30及芯片60的一侧形成一封胶体70并使得所述封胶体70包覆所述第一防护层20、所述线路重置层30、所述第二防护层40及所述芯片60。
所述封胶体70包括一封胶表面71。所述封胶表面71与所述第一表面121相接触。
在本实施方式中，通过注塑成型的方式形成所述封胶体70。具体地，首先提供一模具(图未示)，所述模具包括一模穴及一注胶通道，将包含有所述第一防护层20、所述线路重置层30及所述芯片60的承载基板10收容于所述模穴内；然后，通过所述注胶通道向所述模穴内注入胶体，使胶体包覆所述第一防护层20、所述线路重置层30及所述芯片60；接着，固化所述胶体，从而形成所述封胶体70；之后，将形成有所述封胶体70的所述承载基板10从所述模穴中取出来。
在本实施方式中，所述封胶体70的材质为环氧塑封料(epoxy molding compound，EMC)。在其他实施方式中，所述封胶体70的材质并不局限于EMC材料，还可以为其他的适应于塑封的材料。
第五步，请参阅图5，移除所述承载基板10，得到一封装中间体110。
所述封装中间体110包括一第一防护层20、一形成在所述第一防护层20上的线路重置层30、一包覆所述线路重置层30的第二防护层40、一芯片60及一包覆所述第一防护层20、所述线路重置层30、所述第二防护层40及所述芯片60的封胶体70。其中，所述第一防护层20包括一外露表面22及与所述外露表面22相连接的至少四个侧边23，所述外露表面22远离所述线路重置层30，所述第一防护层20上形成有多个第一开口21，所述第二防护层40上形成有多个第二开口41，部分所述线路重置层30分别从所述第一开口21及所述第二开口41内裸露出来。一个所述第二开口41内形成有一个电接触垫50。所述芯片60包括一第二表面61，所述第二表面61面向所述第二防护层40且平行于所述第二防护层40。所述第二表面61上还形成有多个导电凸块62，所述导电凸块62固接在所述电接触垫50上。一个所述导电凸块62对应一个所述电接触垫50。所述封胶体70包括一封胶表面71。所述封胶体70完全包括所述线路重置层30、所述第二防护层40及所述芯片60并包覆所述第一防护层20的至少四个侧边23，所述封胶体70的封胶表面71与所述第一防护层20的外露表面22相平齐。
第六步，请参阅图6，在多个所述第一开口21内填充导电材料并形成多个焊球80，进而形成一芯片封装结构100。
多个所述焊球80用于电连接外部电子元件(图未示)，所述外部电子元件可以为芯片、电路板等。
本发明还提供一种芯片封装结构100，所述芯片封装结构100包括一第一防护层20、一形成在所述第一防护层20上的线路重置层30、一包覆所述线路重置层30的第二防护层40、一与所述线路重置层30电连接的芯片60及一包覆所述第一防护层20、所述线路重置层30、所述第二防护层40及所述芯片60的封胶体70。其中，所述第一防护层20包括一外露表面22，所述外露表面22远离所述线路重置层30，所述第一防护层20上形成有多个第一开口21，所述第二防护层40上形成有多个第二开口41，部分所述线路重置层30分别从所述第一开口21及所述第二开口41内裸露出来。一个所述第二开口41内形成有一个电接触垫50。所述第一防护层20还包括一与所述线路重置层30相背的外露表面22及与所述外露表面22相连接的至少四个侧边23，所述封胶体70包覆所述第一防护层20的至少四个侧边23。所述芯片60包括一第二表面61，所述第二表面61面向所述第二防护层40且平行于所述第二防护层40。所述第二表面61上还形成有多个导电凸块62，所述导电凸块62固接在所述电接触垫50上。一个所述导电凸块62对应一个所述电接触垫50。所述封胶体70包括一封胶表面71。所述封胶表面71与所述第一防护层20的外露表面22相平齐。
所述芯片封装结构100还包括多个焊球80，一个所述焊球80形成在一个所述第一开口21内，多个所述焊球80分别与所述线路重置层30电连接，用以电连接外部电子元件。
本发明提供的芯片封装结构及其制作方法，将所述线路重置层30及形成在所述线路重置层30上的所述第一防护层20的至少四个侧边23也包覆在所述封胶体70内，从而能够避免所述线路重置层30及第一防护层20被外力破坏，进而增强所述芯片封装结构100的可靠性。
以上所述，仅是本发明的较佳实施方式而已，并非对本发明任何形式上的限制，虽然本发明已是较佳实施方式揭露如上，并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施方式，但凡是未脱离本发明技术方案内容，依据本发明的技术实质对以上实施方式所做的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (10)

1.一种芯片封装结构，包括一第一防护层、一形成在所述第一防护层上的线路重置层、一与所述线路重置层电连接的芯片及一包覆所述线路重置层及所述芯片的封胶体，所述第一防护层包括一外露表面及与所述外露表面相连接的至少四个侧边，所述封胶体包括一封胶表面；其特征在于，所述封胶体还包覆所述第一防护层的至少四个侧边。
2.如权利要求1所述的芯片封装结构，其特征在于，所述第一防护层上形成有多个第一开口，部分所述线路重置层从所述第一开口内裸露出来，一个所述第一开口内形成有一个焊球，所述焊球与所述线路重置层电连接。
3.如权利要求1所述的芯片封装结构，其特征在于，所述芯片封装结构还包括一第二防护层，所述第二防护层形成在所述线路重置层上且包覆所述线路重置层，所述第二防护层上形成有多个第二开口，部分所述线路重置层从所述第二开口内裸露出来，所述第二开口内形成有电接触垫。
4.如权利要求3所述的芯片封装结构，其特征在于，每一个第二开口内形成有一个电接触垫，每一个所述芯片还形成有多个导电凸块，所述导电凸块固接在所述电接触垫上，一个所述导电凸块对应一个所述电接触垫。
5.如权利要求1所述的芯片封装结构，其特征在于，所述第一防护层的外露表面与所述封胶体的封胶表面平齐。
6.如权利要求1所述的芯片封装结构，其特征在于，所述封胶体的材质为环氧塑封料。
7.一种芯片封装结构的制作方法，包括如下步骤：
提供一承载基板；
在所述承载基板的表面上形成一第一防护层及在所述第一防护层上形成一线路重置层，所述第一防护层包括一与所述承载基板相贴的外露表面；
提供至少一芯片，并将所述芯片与所述线路重置层电性连接；
形成一封胶体并使得所述封胶体包覆所述第一防护层、所述线路重置层及所述芯片，所述封胶体包括一与所述承载基板相贴的封胶表面；及
移除所述承载基板，得到所述芯片封装结构。
8.如权利要求7所述的芯片封装结构的制作方法，其特征在于，所述第一防护层上形成有多个第一开口，部分所述线路重置层从所述第一开口内裸露出来，在移除所述承载基板的步骤之后还包括步骤：
在每一个所述第一开口内形成一个焊球，所述焊球与所述线路重置层电连接。
9.如权利要求7所述的芯片封装结构的制作方法，其特征在于，在形成线路重置层之后，还包括步骤：
形成一包覆所述线路重置层的第二防护层，所述第二防护层上形成有多个第二开口，部分所述线路重置层分别从所述第二开口内裸露出来；及
在所述第二开口内形成电接触垫，一个第二开口内形成一个电接触垫；一个所述芯片上还形成有多个导电凸块，所述导电凸块固接在所述电接触垫上，一个所述导电凸块对应一个所述电接触垫。
10.如权利要求7所述的芯片封装结构的制作方法，其特征在于，所述封胶体的封胶表面与所述第一防护层的外露表面相平齐。
CN201910153370.1A 2019-02-28 2019-02-28 芯片封装结构及其制作方法 Pending CN111627867A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201910153370.1A CN111627867A (zh) 2019-02-28 2019-02-28 芯片封装结构及其制作方法
US16/398,746 US11056411B2 (en) 2019-02-28 2019-04-30 Chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910153370.1A CN111627867A (zh) 2019-02-28 2019-02-28 芯片封装结构及其制作方法

Publications (1)

Publication Number Publication Date
CN111627867A true CN111627867A (zh) 2020-09-04

Family

ID=72236435

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910153370.1A Pending CN111627867A (zh) 2019-02-28 2019-02-28 芯片封装结构及其制作方法

Country Status (2)

Country Link
US (1) US11056411B2 (zh)
CN (1) CN111627867A (zh)

Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050017374A1 (en) * 2003-07-24 2005-01-27 Helmut Kiendl Semiconductor component of semiconductor chip size with flip-chip-like external contacts, and method of producing the same
CN1953152A (zh) * 2005-10-18 2007-04-25 恩益禧电子股份有限公司 一种利用互连结构制造半导体模块的方法
US20070114661A1 (en) * 2005-11-23 2007-05-24 Choi Seung-Yong Semiconductor package and method of fabricating the same
CN101154641A (zh) * 2006-09-26 2008-04-02 新光电气工业株式会社 半导体器件及其制造方法
CN102280426A (zh) * 2010-06-11 2011-12-14 卡西欧计算机株式会社 半导体器件及其制造方法
CN102403239A (zh) * 2010-09-13 2012-04-04 新科金朋有限公司 半导体器件及形成用于在Fo-WLCSP中安装半导体小片的引线上键合互连的方法
US8338231B2 (en) * 2010-03-29 2012-12-25 Infineon Technologies Ag Encapsulated semiconductor chip with external contact pads and manufacturing method thereof
CN102842546A (zh) * 2011-06-23 2012-12-26 矽品精密工业股份有限公司 半导体封装件及其制法
CN103579197A (zh) * 2012-07-19 2014-02-12 矽品精密工业股份有限公司 具有防电磁波干扰的半导体组件
CN104217967A (zh) * 2013-05-31 2014-12-17 宏启胜精密电子(秦皇岛)有限公司 半导体器件及其制作方法
CN105097757A (zh) * 2014-04-21 2015-11-25 富葵精密组件(深圳)有限公司 芯片封装基板、芯片封装结构及制作方法
CN105304584A (zh) * 2014-07-31 2016-02-03 恒劲科技股份有限公司 中介基板及其制造方法
US20160155680A1 (en) * 2014-12-01 2016-06-02 Infineon Technologies Ag Semiconductor Package and Method of Fabrication Thereof
CN105762132A (zh) * 2014-12-04 2016-07-13 矽品精密工业股份有限公司 单层线路式封装基板及制法、单层线路式封装结构及制法
US20160240466A1 (en) * 2015-02-13 2016-08-18 Siliconware Precision Industries Co., Ltd. Electronic package and fabrication method thereof
US20160284620A1 (en) * 2015-03-26 2016-09-29 Dyi-chung Hu Low profile ic package
WO2016164119A1 (en) * 2015-04-07 2016-10-13 Apple Inc. Double side mounting memory integration in thin low warpage fanout package
CN106783776A (zh) * 2016-12-26 2017-05-31 华进半导体封装先导技术研发中心有限公司 芯片封装结构及方法
CN107195594A (zh) * 2016-03-14 2017-09-22 美光科技公司 具有侧壁保护重布层中介层的半导体封装及其制造方法
CN107591381A (zh) * 2016-07-06 2018-01-16 欣兴电子股份有限公司 线路重分布结构的制造方法与线路重分布结构单元
CN107680912A (zh) * 2017-10-13 2018-02-09 中芯长电半导体（江阴）有限公司 Emi防护的芯片封装结构及封装方法
TW201824404A (zh) * 2016-12-27 2018-07-01 冠寶科技股份有限公司 一種無基板半導體封裝製造方法
CN108400119A (zh) * 2017-02-08 2018-08-14 美光科技公司 半导体封装及其制造方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5324191B2 (ja) * 2008-11-07 2013-10-23 ルネサスエレクトロニクス株式会社 半導体装置
JP5463173B2 (ja) * 2010-03-12 2014-04-09 日立オートモティブシステムズ株式会社 角速度検出装置
JP5732884B2 (ja) * 2011-02-09 2015-06-10 富士通株式会社 半導体装置及びその製造方法、電源装置
US8828848B2 (en) * 2011-12-16 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Die structure and method of fabrication thereof
US9385052B2 (en) * 2012-09-14 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages
US9209156B2 (en) * 2012-09-28 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuits stacking approach
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9018045B2 (en) * 2013-07-15 2015-04-28 Freescale Semiconductor Inc. Microelectronic packages and methods for the fabrication thereof
JP6418625B2 (ja) * 2013-12-13 2018-11-07 東芝メモリ株式会社 半導体装置の製造方法
US9502364B2 (en) * 2014-08-28 2016-11-22 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package and method of forming the same
US9589903B2 (en) * 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
US9472425B2 (en) * 2015-03-19 2016-10-18 Qualcomm Incorporated Power distribution improvement using pseudo-ESR control of an embedded passive capacitor
US9704808B2 (en) * 2015-03-20 2017-07-11 Mediatek Inc. Semiconductor device and wafer level package including such semiconductor device
TWI570842B (zh) * 2015-07-03 2017-02-11 矽品精密工業股份有限公司 電子封裝件及其製法
TWI590392B (zh) * 2015-08-03 2017-07-01 矽品精密工業股份有限公司 電子封裝件及其製法
JP6397806B2 (ja) * 2015-09-11 2018-09-26 東芝メモリ株式会社 半導体装置の製造方法および半導体装置
US9941260B2 (en) * 2015-09-16 2018-04-10 Mediatek Inc. Fan-out package structure having embedded package substrate
KR101858952B1 (ko) * 2016-05-13 2018-05-18 주식회사 네패스 반도체 패키지 및 이의 제조 방법
US10797025B2 (en) * 2016-05-17 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced INFO POP and method of forming thereof
US20180005916A1 (en) * 2016-06-30 2018-01-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9825007B1 (en) * 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
TWI676259B (zh) * 2016-09-02 2019-11-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10529698B2 (en) * 2017-03-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same
US20190067145A1 (en) * 2017-08-22 2019-02-28 Micron Technology, Inc. Semiconductor device
US10276508B2 (en) * 2017-09-28 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages and methods of forming the same
US10714403B2 (en) * 2017-11-03 2020-07-14 Advanced Semiconductor Engineering, Inc. Semiconductor device package with patterned conductive layers and an interconnecting structure
US10515922B2 (en) * 2017-11-15 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip integrated fan-out package
US10734323B2 (en) * 2017-11-22 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures
US10879220B2 (en) * 2018-06-15 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and manufacturing method thereof
US10879224B2 (en) * 2018-10-30 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure, die and method of manufacturing the same

Patent Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050017374A1 (en) * 2003-07-24 2005-01-27 Helmut Kiendl Semiconductor component of semiconductor chip size with flip-chip-like external contacts, and method of producing the same
CN1953152A (zh) * 2005-10-18 2007-04-25 恩益禧电子股份有限公司 一种利用互连结构制造半导体模块的方法
US20070114661A1 (en) * 2005-11-23 2007-05-24 Choi Seung-Yong Semiconductor package and method of fabricating the same
CN101154641A (zh) * 2006-09-26 2008-04-02 新光电气工业株式会社 半导体器件及其制造方法
US8338231B2 (en) * 2010-03-29 2012-12-25 Infineon Technologies Ag Encapsulated semiconductor chip with external contact pads and manufacturing method thereof
CN102280426A (zh) * 2010-06-11 2011-12-14 卡西欧计算机株式会社 半导体器件及其制造方法
CN102403239A (zh) * 2010-09-13 2012-04-04 新科金朋有限公司 半导体器件及形成用于在Fo-WLCSP中安装半导体小片的引线上键合互连的方法
CN102842546A (zh) * 2011-06-23 2012-12-26 矽品精密工业股份有限公司 半导体封装件及其制法
CN103579197A (zh) * 2012-07-19 2014-02-12 矽品精密工业股份有限公司 具有防电磁波干扰的半导体组件
CN104217967A (zh) * 2013-05-31 2014-12-17 宏启胜精密电子(秦皇岛)有限公司 半导体器件及其制作方法
CN105097757A (zh) * 2014-04-21 2015-11-25 富葵精密组件(深圳)有限公司 芯片封装基板、芯片封装结构及制作方法
CN105304584A (zh) * 2014-07-31 2016-02-03 恒劲科技股份有限公司 中介基板及其制造方法
US20160155680A1 (en) * 2014-12-01 2016-06-02 Infineon Technologies Ag Semiconductor Package and Method of Fabrication Thereof
CN105655305A (zh) * 2014-12-01 2016-06-08 英飞凌科技股份有限公司 半导体封装及其制备方法
CN105762132A (zh) * 2014-12-04 2016-07-13 矽品精密工业股份有限公司 单层线路式封装基板及制法、单层线路式封装结构及制法
US20160240466A1 (en) * 2015-02-13 2016-08-18 Siliconware Precision Industries Co., Ltd. Electronic package and fabrication method thereof
CN105990270A (zh) * 2015-02-13 2016-10-05 矽品精密工业股份有限公司 电子封装件及其制法
US20160284620A1 (en) * 2015-03-26 2016-09-29 Dyi-chung Hu Low profile ic package
WO2016164119A1 (en) * 2015-04-07 2016-10-13 Apple Inc. Double side mounting memory integration in thin low warpage fanout package
CN107195594A (zh) * 2016-03-14 2017-09-22 美光科技公司 具有侧壁保护重布层中介层的半导体封装及其制造方法
CN107591381A (zh) * 2016-07-06 2018-01-16 欣兴电子股份有限公司 线路重分布结构的制造方法与线路重分布结构单元
CN106783776A (zh) * 2016-12-26 2017-05-31 华进半导体封装先导技术研发中心有限公司 芯片封装结构及方法
TW201824404A (zh) * 2016-12-27 2018-07-01 冠寶科技股份有限公司 一種無基板半導體封裝製造方法
CN108400119A (zh) * 2017-02-08 2018-08-14 美光科技公司 半导体封装及其制造方法
CN107680912A (zh) * 2017-10-13 2018-02-09 中芯长电半导体（江阴）有限公司 Emi防护的芯片封装结构及封装方法

Also Published As

Publication number Publication date
US11056411B2 (en) 2021-07-06
US20200279786A1 (en) 2020-09-03

Similar Documents

Publication Publication Date Title
US8378477B2 (en) Integrated circuit packaging system with film encapsulation and method of manufacture thereof
KR101805114B1 (ko) 이중 측부 연결부를 구비한 집적회로 패키징 시스템 및 이의 제조 방법
US8241968B2 (en) Printed circuit board (PCB) including a wire pattern, semiconductor package including the PCB, electrical and electronic apparatus including the semiconductor package, method of fabricating the PCB, and method of fabricating the semiconductor package
US6492726B1 (en) Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US7618849B2 (en) Integrated circuit package with etched leadframe for package-on-package interconnects
US11908779B2 (en) Land structure for semiconductor package and method therefor
US11309255B2 (en) Very thin embedded trace substrate-system in package (SIP)
CN109216335B (zh) 扇出型半导体封装模块
US8536718B2 (en) Integrated circuit packaging system with trenches and method of manufacture thereof
KR101863850B1 (ko) 이중 측부 연결부를 구비한 집적회로 패키징 시스템 및 이의 제조 방법
KR101964389B1 (ko) 수직 상호연결들을 갖는 집적 회로 패키징 시스템 및 그 제조 방법
CN110970399A (zh) 半导体封装件
US9711444B2 (en) Packaging module and substrate structure thereof
CN101286503A (zh) 具有多晶粒并排配置的半导体组件封装结构及其方法
TW202127601A (zh) 封裝結構及其製造方法
US9293398B2 (en) Land structure for semiconductor package and method therefor
US10431535B2 (en) Electronic package and method for fabricating the same
CN107527928B (zh) 光学组件封装结构
KR102532081B1 (ko) 강화된 속성들을 가진 플립 칩 모듈
TWI694555B (zh) 晶片封裝結構及其製作方法
US10461044B2 (en) Wafer level fan-out package and method of manufacturing the same
US20100327425A1 (en) Flat chip package and fabrication method thereof
CN111627867A (zh) 芯片封装结构及其制作方法
US9589935B2 (en) Package apparatus and manufacturing method thereof
CN111987062A (zh) 半导体封装结构及其制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20201112

Address after: 518109 Four, Six, Seven and Thirteen Workshops in Area B of Foxconn Guanlan Science Park, Dasan Community, Guanlan Street, Longhua New District, Shenzhen City, Guangdong Province (Section I)

Applicant after: FuTaiHua Industry (Shenzhen) Co.,Ltd.

Applicant after: SOCLETECHNOLOGY Corp.

Address before: 518109 Four, Six, Seven and Thirteen Workshops in Area B of Foxconn Guanlan Science Park, Dasan Community, Guanlan Street, Longhua New District, Shenzhen City, Guangdong Province (Section I)

Applicant before: FuTaiHua Industry (Shenzhen) Co.,Ltd.

Applicant before: HON HAI PRECISION INDUSTRY Co.,Ltd.

TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20220517

Address after: 518109 building 4, building 6, building 7, building 13 (section I) of Foxconn Guanlan science and Technology Park Area B plant, Dashan community, Guanlan street, Longhua New District, Shenzhen City, Guangdong Province

Applicant after: FuTaiHua Industry (Shenzhen) Co.,Ltd.

Applicant after: Qingdao new core technology Co.,Ltd.

Address before: 518109 building 4, building 6, building 7, building 13 (section I) of Foxconn Guanlan science and Technology Park Area B plant, Dashan community, Guanlan street, Longhua New District, Shenzhen City, Guangdong Province

Applicant before: FuTaiHua Industry (Shenzhen) Co.,Ltd.

Applicant before: SOCLETECHNOLOGY Corp.

RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20200904