CN108400119A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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Publication number
CN108400119A
CN108400119A CN201710130042.0A CN201710130042A CN108400119A CN 108400119 A CN108400119 A CN 108400119A CN 201710130042 A CN201710130042 A CN 201710130042A CN 108400119 A CN108400119 A CN 108400119A
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Prior art keywords
redistribution layer
casting mold
mold compound
semiconductor
semiconductor element
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CN201710130042.0A
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CN108400119B (zh
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施信益
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明公开了一种半导体封装及其制造方法，半导体封装包含至少一个半导体元件、第一重分布层、第一铸型化合物、第二铸型化合物、导电通孔以及第二重分布层。第一重分布层设置于半导体元件下方，且电性连接至半导体元件。第一铸型化合物设置于第一重分布层上方并环绕半导体元件。第二铸型化合物环绕第一重分布层与第一铸型化合物的至少一个部分。多个导电通孔延伸过第二铸型化合物。第二重分布层设置于第二铸型化合物远离第一重分布层的表面。第二重分布层经由多个导电通孔电性连接至第一重分布层。通过此半导体封装，半导体产品可更兼容的整合，并在更微型化下提供更佳的效能。

Description

半导体封装及其制造方法
技术领域
本发明是有关于一种半导体封装及其制造方法。
背景技术
通过半导体封装，半导体产品可更兼容的整合，并在更微型化下提供更佳的效能。因此，发展制造半导体封装的方法，诸如引线接合、覆晶封装、晶圆级封装以及面板级封装以满足不同要求。一些制造半导体封装的方法可采用重布层以组装半导体封装的元件并扇出埋于半导体封装内的半导体元件。然而，采用的重布层的连接配置难以适应于由不同封装技术所制成的半导体封装，且可能大幅地降低传输信号或能量进入封装的半导体元件的效率；且更进一步来说，失效的传输可能进一步产生累积于半导体封装内的热能。因此，半导体封装可能会运作的更没效率。因此，如上所述的现行半导体封装结构与其制造方法，明显存在不便与缺陷，需要进一步的改善。为解决上述问题，此领域中的一般技术人员已致力于找出解答，而问题仍缺少合适的解答。因此，有效处理上述问题为重要的研发课题，且也为此领域中所期望的进步。
发明内容
本发明的目的在于提供一种可更兼容的整合，并在更微型化下提供更佳的效能半导体封装及其制造方法。
为实现上述目的，本发明提供一种半导体封装。半导体封装包含至少一个半导体元件、第一重分布层、第一铸型化合物、第二铸型化合物、导电通孔以及第二重分布层。第一重分布层设置于半导体元件下方，且电性连接至半导体元件。第一铸型化合物设置于第一重分布层上方且环绕半导体元件。第二铸型化合物环绕第一重分布层与第一铸型化合物的至少一个部份。导电通孔延伸过第二铸型化合物。第二重分布层设置于第二铸型化合物远离第一重分布层的表面。第二重分布层经由导电通孔电性连接至第一重分布层。
本发明提供一种用于制造半导体封装的方法。此方法包含：提供工件，其包含第一重分布层、导电通孔以及第一基材，其中导电通孔延伸进第一基材，第一重分布层设置于第一基材上并电性连接至导电通孔；随后，在第一重分布层远离导电通孔侧设置至少一个半导体元件，且此半导体元件连接至第一重分布层；随后，形成第一铸型化合物以环绕半导体元件；随后，移除第一基材；随后，形成第二铸型化合物以环绕第一重分布层与第一铸型化合物的至少一部分，其中导电通孔暴露于第二铸型化合物远离介电层的表面上；然后在第二铸型化合物远离第一重分布层的表面上形成第二重分布层并经由导电通孔电性连接至第一重分布层。
本发明的半导体封装及其制造方法，其半导体封装可更兼容的整合，并在更微型化下提供更佳的效能。
应了解后续的整体详述与下文中的实施细节，系举例并旨为提供所请求发明的深入解释。
附图说明
图1为绘示本发明一实施方式的半导体封装的剖面图。
图2为绘示本发明一实施方式的半导体封装制造法的流程图。
图3至图15为绘示本发明一实施方式的半导体封装在不同阶段的简化片段剖面图。
具体实施方式
以下将以附图公开本发明的多个实施方式，为明确说明起见，许多实务上的细节将在以下叙述中一并说明。然而，应了解到，这些实务上的细节不应用以限制本发明。也就是说，在本发明部分实施方式中，这些实务上的细节是非必要的。此外，为简化附图起见，一些公知惯用的结构与元件在附图中将以简单示意的方式绘示。并且，除非有其他表示，在不同附图中相同的元件符号可视为相对应的元件。这些附图的绘示是为了清楚表达这些实施方式中各元件之间的连接关系，并非绘示各元件的实际尺寸。
参照图1。依据本发明的一些实施方式，图1为半导体封装100的剖面图。如图1所示，在一些实施方式中，半导体封装100可具有至少一个半导体元件200、第一重分布层110、第一铸型化合物120、第二铸型化合物130、导电通孔140以及第二重分布层150。第一重分布层110可设置于半导体元件200下并电性连接至半导体元件200。更精确而言，在一些实施方式中，第一重分布层110可具有第一介电层114以及埋于第一介电层114中的第一导通路径112。在一些实施方式中，第一介电层114的材料可为无机介电材料，诸如氮化硅(SiN)、二氧化硅(SiO2)…等等。在其他实施方式中，第一介电层114的材料可为有机介电材料，诸如苯并环丁烯(benzocyclobutene,BCB)、该聚酰亚胺(polyimide,PI)、聚苯并(polybenzimidazoles,PBO)…等等。第一导通路径112连接至半导体元件200中的至少一个。在一些实施方式中。半导体元件200可具有活性表面210，且第一导通路径112电性连接至活性表面210中的至少一个。在一些实施方式中，半导体封装100可具有二个或更多个半导体元件200。半导体元件200可经由第一导通路径112于内部连接，举例而言，第一导通路径112A内连两个半导体元件200。
在一些实施方式中，第一铸型化合物120设置于第一重分布层110上方，且环绕半导体元件200。更精确而言，第一铸型化合物120环绕一个或更多个半导体元件200以形成单芯片模块或多芯片模块，且第一重分布层110可在单芯片模块或多芯片模块内连接至一个或更多个半导体元件200。在一些实施方式中，在第一重分布层110与半导体元件200夹住的间隔可填充第一铸型化合物120。在其他实施方式中，在第一重分布层110与半导体元件200间可形成接合材料(未绘制)以增加接合强度。
在一些实施方式中，第二铸型化合物130环绕第一重分布层110与第一铸型化合物120的至少一部分。换句话说，第一铸型化合物120与第二铸型化合物130完整地包覆第一重分布层110。在一些实施方式中，第二铸型化合物130的材料不同于第一铸型化合物120的材料。在一些实施方式中，可在第一铸型化合物120成形后形成第二铸型化合物130，使得第一铸型化合物120的玻璃转换温度(Tg)大于第二铸型化合物130的玻璃转换温度。
在一些实施方式中，在第二铸型化合物130背对第一重分布层110的表面上设置第二重分布层150，且导电通孔140延伸过第二铸型化合物130并连接第二重分布层150与第一重分布层110。因此，第二重分布层150可经由导电通孔140电性连接至第一重分布层110与半导体元件200。在一些实施方式中，第二重分布层150可具有第二介电层154与埋于第二介电层154内的第二导通路径152。第二导通路径152各别连接至导电通孔140。在一些实施方式中，第二介电层154的材料可为有机介电材料，诸如苯并环丁烯(BCB)、该聚酰亚胺(PI)、聚苯并(PBO)…等等。
因为半导体元件200可在晶圆级芯片尺寸封装(wafer-level chip-scalepackging,WL-CSP)中组装至第一重分布层110，且第二重分布层150可在面板级封装(panellevel packaging,PLP)中组装至第二铸型化合物130，因此可由两不同级的封装制造半导体封装100。因此，由第一重分布层110、导电通孔140以及第二重分布层150所组装成的半导体封装100的扇出(fan-out)结构，可链接两个不同级的封装技术，如晶圆级芯片级封装与面板级封装，半导体封装100则可享有较大的兼容性与可行性，可轻易适应至多种连接配置，诸如多种半导体元件200及与其他元件或I/O接头连接的扇出接头。
此外，半导体封装100的介电特性可由第一重分布层110与第二重分布层150的组成材料调整，借使用不同有机或无机材料形成第一重分布层110与第二重分布层150改变介电特性，半导体封装100可在介电特性上具有更佳的弹性与能力。
在一些实施方式中，第一重分布层110的最小节宽可不同于第二重分布层150的最小节宽。举例而言，第一重分布层110与精细节距半导体元件200连接时可具有较小的最小节宽。举例而言，第二重分布层150与I/O扇出连接时可具有较大的最小节宽。在一些实施方式中，第二重分布层150的最小节宽大于或等于第一重分布层110的最小节宽。因此，半导体封装100可适应于多种尺寸的电子接头。
在一些实施方式中，半导体封装100可进一步包含第三介电层170。第三介电层170设置于第一重分布层110远离第一铸型化合物120的表面上，且导电通孔140进一步延伸过第三介电层170。在一些实施方式中，第三介电层170、第一重分布层110以及第二重分布层150的介电系数可依实际需求调整。举例而言，第三介电层170的介电系数、第一重分布层110的介电系数以及第二重分布层150的介电系数中的至少一个可与他者不同。
在一些实施方式中，半导体封装100可进一步包含焊接球160。焊接球160各自连接与设置于第二导通路径152。在一些实施方式中，半导体封装100可进一步包含导电凸块180。导电凸块180延伸过第一铸型化合物120，以将第一重分布层110，尤其第一导通路径112，电性连接至半导体元件200。
参照图2。依据本发明的一实施方式，图2为一流程图，说明半导体封装制造方法300。如图2所示，半导体封装制造方法300由步骤S301开始，其中提供工件(参照图6)。工件包含第一重分布层110、导电通孔140以及第一基材400。导电通孔140延伸进第一基材400。第一重分布层110设置于第一基材400上并连接至导电通孔140。随后，半导体封装制造方法300接续进行步骤S302，其中在第一重分布层110远离导电通孔140的侧面上设置至少一个半导体元件200。半导体元件200连接至第一重分布层110。随后，半导体封装制造方法300接续进行步骤S303，其中第一铸型化合物120形成于第一重分布层110上方以环绕半导体元件200。随后，半导体封装制造方法300接续进行步骤S304，其中移除第一基材400以暴露出每个导电通孔140的末端142。
随后，半导体封装制造方法300接续进行步骤S305，其中形成第二铸型化合物130以环绕第一重分布层110与第一铸型化合物120的至少一部分。导电通孔140暴露于第二铸型化合物130远离第一重分布层110的第一介电层114的表面上。随后，半导体封装制造方法300接续进行步骤S306，其中在第二铸型化合物130远离第一重分布层110的表面上形成第二重分布层150。第二重分布层150经由暴露的导电通孔140电性连接至第一重分布层110。
由于半导体封装制造方法300中包含第一重分布层110与第二重分布层150以适应多种连接配置，诸如精细间距半导体元件200、大尺寸I/O扇出接头，可建立半导体元件200与其他元件的导电通路。进一步来说，半导体封装100可在两个不同级别的封装中成形，举例来说，半导体元件200可连接至晶圆级芯片尺寸封装(WL-CSP)或扇出型晶圆级封装(fan-out wafer level packaging,FO-WLP)中的工件，且于面板级封装(PLP)中可在第二铸型化合物130的上方形成第二重分布层150。因此，半导体封装100的成形可连结两个不同层级的封装技术，诸如晶圆级芯片尺寸封装与面板级封装，以此使半导体封装100的制造享有更多的弹性与兼容性。
请参照图3至图15。依据本发明的一实施方式，图3至图15说明了半导体封装100在不同阶段的简化片段剖面图。如图3所示，提供第一基材400。第三介电层170可成形于第一基材400上。在一些实施方式中，第一基材400可为芯片。第三介电层170沉积于第一基材400上。随后，参照图4，可形成沟槽420。沟槽420延伸过第三介电层170并进一步延伸进第一基材400。参照图5，随后可于沟槽420中填充导电材料，以形成导电通孔140。
请参照图6，可对应至步骤S301。如图6所示，在一些实施方式中，第三介电层170上可形成第一重分布层110。在一些实施方式中，第一重分布层110可包含埋于第一介电层114中的第一导通路径112。更特定而言，在一些实施方式中，形成第一重分布层110的方式可为：在第一介电层114形成第一导通路径112，第一介电层114具有开口以暴露出底层的导电特征，如导电通孔140，且可形成另一第一介电层114，具有在不同位置暴露第一导通路径112的开口以进一步连结。在一些实施方式中，第一介电层114可由保护层材料或介电材料诸如氮化硅(SiN)、二氧化硅(SiO2)、其他无机介电材料、苯并环丁烯(BCB)、该聚酰亚胺(PI)、聚苯并(PBO)或其他有机介电材料。第一导通路径112的其中一端暴露于第一介电层116远离第一基材400处，且第一导通路径112的另一端连接至其中一个导电通孔140。在其他实施方式中，第三介电层170也可形成为第一重分布层110的第一介电层114，因此第一重分布层110可直接成形于第一基材400上。在其他实施方式中，导电凸块180可各别设置于暴露的第一导通路径112上。换句话说，第一重分布层110、导电通孔140与第一基材400总体上可形成工件。应了解于此处所描述工件的制造，并不限制本发明，其可在不背离本发明的精神与范畴下，由本领域的技术人员依实际需求调整。
请参照图7，可对应至步骤S302。如图7所示，在一些实施方式中，半导体元件200设置于第一重分布层110远离导电通孔140的侧面上，并连接至第一重分布层110。此外，在一些实施方式中，半导体元件200包含活性表面210，电性连接至第一重分布层110，或导电凸块180。在一些实施方式中，由于采用第一重分布层110连接至半导体元件200，第一重分布层110的最小节宽可调整以适应精细间距半导体元件200。
请参照图8，可对应至步骤S303。如图8所示，在一些实施方式中，第一铸型化合物120成形于第一重分布层110相对于第一基材400的侧面上。第一铸型化合物120环绕半导体元件200与导电凸块180。在一些实施方式中，在半导体元件200与第一重分布层110间可附接连接材料以增强半导体元件200的接合，其中剩余部分可由第一铸型化合物120填充。在一些实施方式中，第一铸型化合物120可由第一基材400的相对侧打薄。可暴露半导体元件200远离第一基材400的上表面202。半导体元件200的上表面202与第一铸型化合物120背对第一重分布层110的表面可为共平面。在一些实施方式中，半导体元件200可被包覆于第一铸型化合物120之内。
请参照图9，可对应至步骤S304。如图9所示，在一些实施方式中，移除第一基材400，并暴露导电通孔140以进一步连接。在一些实施方式中，导电通孔140可经由第一重分布层110内部连接的第一导通路径112连接二个或更多个半导体元件200。
请参照图10。如图10所示，可通过锯切或切割以分割半导体元件200，沿切割线500穿过第一铸型化合物120与第一重分布层110的第一介电层114。进一步说，半导体元件200的切割是被配置以分割互不相连的半导体元件200。
请参照图11。如图11所示，半导体元件200，尤其是与第一重分布层110连接的分割半导体元件200，设置于第二基材600上。在一些实施方式中，第二基材600可为面板。附加薄膜620可成形于第二基材600上以附接于半导体元件200。
参照图12、图13，其可对应至步骤S305。如图12所示，在一些实施方式中，在第二基材600上可形成第二铸型化合物700，且第一铸型化合物120的至少一个部分与第一重分布层110模铸于第二铸型化合物700内。如图13所示，在一些实施方式中，随后，第二铸型化合物700可由与第二基材600相对的侧面打薄，以形成第二铸型化合物130并暴露导电通孔140，尤其是远离半导体元件200的导电通孔140的末端142。在其他实施方式中，第二铸型化合物130的成形可不经打薄程序，且依然暴露出导电通孔140的末端142。
参照图14，其可对应至步骤S306。如图14所示，于第二铸型化合物130远离第一重分布层110的表面形成第二重分布层150。第二重分布层150电性连接至第一重分布层110，或经由暴露出的导电通孔140进一步连接至半导体元件200。在一些实施方式中，由于可采用第二重分布层150以连接至其他元件或I/O接头，第二重分布层150的最小节宽可大于等于连接至精细间距半导体元件200的第一重分布层110的最小节宽。在一些实施方式中，在第二重分布层150上可形成焊接球160，且电性连接至导电通孔140。
参照图15。如图15所示，可移除第二基材600。可通过锯切或切割过第二铸型化合物130与第二重分布层150的第二介电层154的方法分割半导体封装100。在一些实施方式中，半导体元件200的上表面202，第一铸型化合物120的表面以及第二铸型化合物130背对第二重分布层150的表面可为共平面。
由以上总结，本发明的一实施方式提供的半导体封装100包含至少一个半导体元件200、第一重分布层110、第一铸型化合物120、第二铸型化合物130、导电通孔140以及第二重分布层150。第一重分布层110设置于半导体元件200下，且电性连接至半导体元件200。第一铸型化合物120设置于第一重分布层110的上方且环绕半导体元件200。第二铸型化合物130环绕第一重分布层110与第一铸型化合物120的至少一部分。导电通孔140延伸过第二铸型化合物130。第二重分布层150设置于第二铸型化合物130远离第一重分布层110的表面上。第二重分布层150经由导电通孔140电性连接至第一重分布层110。由于借第一重分布层110、导电通孔140与第二重分布层150组装出了半导体封装100的扇出结构，可链接两个不同级的封装技术，诸如晶圆芯片级封装与芯片级封装，半导体封装100可享有较大的兼容性与可行性，可轻易适应多种连接配置，诸如多种半导体元件200以及与其他元件连接的扇出接头。
本发明的另一实施方式提供一半导体封装制造方法300。半导体封装制造方法300包含提供工件，工件包含第一重分布层110、导电通孔140以及第一基材400，其中导电通孔140延伸入第一基材400，第一重分布层110设置于第一基材400上并连接至导电通孔140；随后，在第一重分布层110远离导电通孔140的表面上设置至少一个半导体元件200，并且半导体元件200连接至第一重分布层110；随后，形成第一铸型化合物120以环绕半导体元件200；随后，移除第一基材400；随后，形成第二铸型化合物130以环绕第一重分布层110与第一铸型化合物120的至少一部分，其中导电通孔140暴露于第二铸型化合物130远离介电层的表面上；并接着在第二铸型化合物130远离第一重分布层110的表面上形成第二重分布层150并且经由导电通孔140电性连接至第一重分布层110。
虽然本发明的一些实施方式与其优点已被详加阐述，应了解可在不背离本发明附加权利要求的精神与范畴下在此处做出多种改变、更动与修正。举例而言，本领域的技术人员可轻易理解，在此处描述的许多特征、功能、工艺与材料依然可在本发明的范畴内改动。更进一步说，现有的应用范畴并非意图限制于说明书中解说的特别实施方式的工艺、机器、制造、对象组装、目的、方法以及步骤。此领域的一般技术人员将能轻易理解，由本发明的公开工艺、机器、制造、对象组装、目的、方法或步骤，现有者或待发展者，可通过依据本发明的实施方式实质操作出同样功能或达成实质上相等于此处描述的对应结果。依此，附加的权利要求意图涵盖于其范畴中诸如工艺、机器、制造、对象组装、目的、方法或步骤。

Claims (20)

1.一种半导体封装，其特征在于，包含：
至少一个半导体元件；
第一重分布层，设置于所述半导体元件下方并电性连接至所述半导体元件；
第一铸型化合物，设置于所述第一重分布层上方并环绕所述半导体元件；
第二铸型化合物，环绕所述第一重分布层与所述第一铸型化合物的至少一部分；
多个导电通孔，延伸过所述第二铸型化合物；以及
第二重分布层，设置于所述第二铸型化合物远离所述第一重分布层的表面下方且经由所述多个导电通孔电性连接至所述第一重分布层。
2.如权利要求1所述的半导体封装，其特征在于，进一步包含多个所述半导体元件。
3.如权利要求2所述的半导体封装，其特征在于，所述第一重分布层包含形成于其内的多个第一导电通路，且至少一个所述第一导电通路连接二个或更多个所述半导体元件。
4.如权利要求1所述的半导体封装，其特征在于，进一步包含介电层，设置于所述第一重分布层远离所述第一铸型化合物的表面，其中所述多个导电通孔进一步延伸过所述介电层。
5.如权利要求4所述的半导体封装，其特征在于，所述介电层的介电系数、所述第一重分布层的介电系数与所述第二重分布层的介电系数中的至少一个不同于其他介电系数。
6.如权利要求1所述的半导体封装，其特征在于，所述第一铸型化合物的玻璃转化温度高于所述第二铸型化合物的玻璃转化温度。
7.如权利要求1所述的半导体封装，其特征在于，所述第一重分布层的最小节宽不同于所述第二重分布层的最小节宽。
8.如权利要求1所述的半导体封装，其特征在于，所述半导体元件的表面、所述第一铸型化合物的表面与所述第二铸型化合物背对所述第二重分布层的表面共平面。
9.如权利要求1所述的半导体封装，其特征在于，进一步包含多个导电凸块延伸过所述第一铸型化合物，以使所述第一重分布层电性连接至所述半导体元件。
10.如权利要求1所述的半导体封装，其特征在于，进一步包含多焊接球，设置于所述第二重分布层远离所述第二铸型化合物的表面，其特征在于，所述多个焊接球分别连接至所述第二重分布层。
11.一种半导体封装制造方法，其特征在于，包含：
提供工件，其中所述工件包含第一重分布层、多个导电通孔以及第一基材，所述多个导电通孔延伸入所述第一基材，所述第一重分布层设置于所述第一基材上并连接至所述多个导电通孔；
在所述第一重分布层远离所述多个导电通孔的侧面设置至少一个半导体元件，且所述半导体元件连接至所述第一重分布层；
形成第一铸型化合物以环绕所述半导体元件；
移除所述第一基材；
形成第二铸型化合物以环绕所述第一重分布层与所述第一铸型化合物的至少一部分，其中所述多个导电通孔暴露于所述第二铸型化合物远离所述第一重分布层的表面；以及
在所述第二重铸化合物远离所述第一重分布层的表面形成第二重分布层，并经由所述多个导电通孔电性连接至所述第一重分布层。
12.如权利要求11所述的半导体封装制造方法，其特征在于，进一步包含：
在所述第一基材上沉积所述介电层；
形成多个沟槽延伸过所述介电层并延伸入所述第一基材；以及
在所述多个沟槽填充导电材料以形成所述多个导电通孔。
13.如权利要求11所述的半导体封装制造方法，其特征在于，所述设置所述至少一个半导体元件进一步包含设置多个所述半导体元件。
14.如权利要求13所述的半导体封装制造方法，其特征在于，进一步包含：
穿过所述第一铸型化合物以及所述第一重分布层分割所述多个半导体元件。
15.如权利要求13所述的半导体封装制造方法，其特征在于，至少一个所述导电通孔连接二个或更多个所述半导体元件。
16.如权利要求15所述的半导体封装制造方法，其特征在于，进一步包含：
穿过所述第一铸型化合物以及所述第一重分布层分割一个或多个彼此不相连的所述多个半导体元件。
17.如权利要求11所述的半导体封装制造方法，其特征在于，进一步包含：
在所述移除所述第一基材之后，在第二基材上设置所述半导体元件。
18.如权利要求11所述的半导体封装制造方法，其特征在于，所述第一重分布层的最小节宽不同于所述第二重分布层的最小节宽。
19.如权利要求11所述的半导体封装制造方法，其特征在于，所述第一铸型化合物的材料不同于所述第二铸型化合物的材料。
20.如权利要求11所述的半导体封装制造方法，其特征在于，进一步包含：
在所述第二重分布层上形成多个焊接球。
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