CN112133696A - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

Info

Publication number
CN112133696A
CN112133696A CN202010596772.1A CN202010596772A CN112133696A CN 112133696 A CN112133696 A CN 112133696A CN 202010596772 A CN202010596772 A CN 202010596772A CN 112133696 A CN112133696 A CN 112133696A
Authority
CN
China
Prior art keywords
package
die
encapsulant
interconnect structure
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010596772.1A
Other languages
English (en)
Other versions
CN112133696B (zh
Inventor
余振华
郭庭豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112133696A publication Critical patent/CN112133696A/zh
Application granted granted Critical
Publication of CN112133696B publication Critical patent/CN112133696B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
    • H01L2023/405—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink heatsink to package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4075—Mechanical elements
    • H01L2023/4081—Compliant clamping elements not primarily serving heat-conduction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4075—Mechanical elements
    • H01L2023/4087—Mounting accessories, interposers, clamping or screwing parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1082—Shape of the containers for improving alignment between containers, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19011—Structure including integrated passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种封装件包括构件。该构件包括器件管芯；中介层，与器件管芯接合；以及第一密封剂，将器件管芯密封在其中。封装件还包括第二密封剂，第二密封剂将构件密封在其中；以及互连结构，位于第二密封剂上方。该互连结构具有电耦合至器件管芯的再分布线。功率模块位于互连结构上方。功率模块通过互连结构电耦合至构件。本发明的实施例还涉及形成封装件的方法。

Description

封装件及其形成方法
技术领域
本发明的实施例涉及封装件及其形成方法。
背景技术
在一些三维集成电路(3DIC)中，首先将器件管芯接合至中介层，该中介层通过焊料区域进一步接合至封装衬底，以形成封装件。所得到的封装件接合至印刷电路板。然而，该结构具有高延迟，并且不适合于高速数据通信。
发明内容
本发明的实施例提供了一种封装件，包括：构件，包括：器件管芯；中介层，与所述器件管芯接合；和第一密封剂，将所述器件管芯密封在其中；第二密封剂，将所述构件密封在其中；互连结构，位于所述第二密封剂上方，其中，所述互连结构包括电耦合至所述器件管芯的再分布线；以及功率模块，位于所述互连结构上方，其中，所述功率模块通过所述互连结构电耦合至所述构件。
本发明的另一实施例提供了一种封装件，包括：构件的阵列，形成阵列，其中，所述构件的阵列中的每个构件包括：第一模塑料；逻辑管芯，位于所述第一模塑料中；和存储器管芯，位于所述第一模塑料中；第二模塑料，所述构件的阵列位于所述第二模塑料中；互连结构，横向扩展超出所述阵列，其中，所述互连结构包括：多个介电层；和多条再分布线，位于所述多个介电层中并且电耦合至所述阵列；以及功率模块，位于所述第二模塑料的外部，其中，所述功率模块电耦合至所述阵列。
本发明的又一实施例提供了一种形成封装件的方法，包括：将多个器件管芯接合至中介层晶圆；将所述多个器件管芯密封在第一密封剂中；抛光所述中介层晶圆以露出所述中介层晶圆的衬底中的贯通孔；形成连接至所述贯通孔的电连接件；分割所述中介层晶圆和所述第一密封剂以形成构件；将所述构件密封在第二密封剂中；在所述第二密封剂上方形成与所述第二密封剂接触的扇出互连结构；以及在所述扇出互连结构上方附接功率模块。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图7示出了根据一些实施例的构件的形成中的中间阶段的截面图。
图8至15示出了根据一些实施例的构件中的组件的布局。
图16至图24示出了根据一些实施例的的包括构件和裸器件管芯的系统封装件的形成中的中间阶段的截面图。
图25至29示出了根据一些实施例的系统封装件中的组件的布局。
图30示出了根据一些实施例的用于形成系统封装件的工艺流程。
具体实施方式
应该理解，以下公开内容提供了许多用于实现本发明的不同特征的不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然，这些仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可以在各个示例中重复参考数字和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的间距关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，间距关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的间距关系描述符可以同样地作相应地解释。
根据一些实施例，提供了一种封装件及其形成方法。封装件的结构适合于形成超大型封装件，诸如对数据通信的速度有严格要求的用于人工智能(AI)应用、5G应用等的那些。根据一些实施例示出了封装件的形成中的中间阶段。讨论了一些实施例的一些变型。本文讨论的实施例将提供示例，以使得能够进行或使用本发明的主题，并且本领域普通技术人员将容易理解可以进行的修改，同时保持在不同实施例的预期范围内。在各个视图和说明性实施例中，相似的参考标号用于指示相似的元件。虽然方法实施例可以讨论为以特定顺序执行，但是其他方法实施例可以以任何逻辑顺序执行。
根据本发明的一些实施例，系统封装件包括通过再分布线互连的多个构件和裸(器件)管芯。再分布线、构件和管芯形成扇出封装件。功率模块接合至扇出封装件，并且位于再分布线的相对侧上，而不是构件和裸管芯上。根据一些实施例，在系统封装件中不使用封装衬底和/或印刷电路板。
图1至图7示出了根据本发明的一些实施例的构件的形成中的中间阶段的截面图。图1至图7所示的工艺也示意性地反映在图30所示的工艺流程200中。
图1示出了封装组件20的截面图，该封装组件20可以是中介层晶圆，封装衬底条、器件管芯晶圆或封装件。封装组件20包括可以彼此相同的多个封装组件22。根据本发明的一些实施例，封装组件22是中介层，中介层中没有有源器件(诸如晶体管和二极管)和无源器件。在整个说明书中，封装组件22在下文中可选地称为中介层22，同时封装组件22也可以是其他类型的封装组件，包括但不限于器件管芯(其中包括有源器件和/或无源器件)、封装衬底、封装件等。
根据本发明的一些实施例，封装组件20包括衬底23，衬底23可以是诸如硅衬底的半导体衬底。衬底23也可以由其他半导体材料形成，诸如硅锗、硅碳等。根据本发明的可选实施例，衬底23是介电衬底。根据这些实施例，中介层20可以包括或可以不包括形成在其中的无源器件。
贯通孔(TV)24形成为从衬底23的顶面延伸到衬底23中。贯通孔24有时也称为衬底通孔，或者当衬底23是硅时称为硅通孔。绝缘层25形成为将贯通孔24与衬底23电绝缘。互连结构28形成在衬底23上方，并且用于电互连集成电路器件(如果有的话)，并且连接至贯通孔24。互连结构28可以包括多个介电层30。根据本发明的一些实施例，介电层30由氧化硅、氮化硅、碳化硅、氮氧化硅、它们的组合和/或它们的多层形成。可选地，介电层30可以包括一个或多个具有低介电常数(k值)的低k介电层。例如，介电层30中的低k介电材料的k值可以小于约3.0，或者小于约2.5。在介电层30中形成金属线32。在上面的金属线32和下面的金属线32之间形成通孔34，并且通孔34互连上面的金属线32和下面的金属线32。
根据一些实施例，金属线32和通孔34使用镶嵌工艺形成，镶嵌工艺包括在介电层30中形成沟槽和通孔开口，沉积导电阻挡层(诸如TiN、Ti、TaN、Ta等)，以及填充金属材料(诸如铜)以填充剩余的沟槽和通孔开口。然后执行诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以去除导电阻挡层和金属材料的多余部分，留下金属线32和通孔34。通过使用镶嵌工艺，金属线可以形成得非常窄，例如，节距(从结构的顶部观察)小于约1μm。这可以在构件内部实现足够数量的局部电连接。
电连接件38形成在封装组件20的顶面处。根据本发明的一些实施例，电连接件38包括金属柱(凸块)，其中可以在或可以不在金属柱的顶面上形成焊料盖。根据本发明的可选实施例，电连接件38包括焊料区域。根据其他实施例，电连接件38包括覆盖有镍层的铜柱、化学镍浸金(ENIG)、化学镍化学钯浸金(ENEPIG)等和/或它们的组合。
参考图2，拾取和放置封装组件40，并且例如通过倒装芯片接合将封装组件40接合至封装组件20。相应的工艺示出为图30所示的工艺流程200中的工艺202。电连接件38将封装组件40中的电路电耦合至封装组件20中的金属线32和贯通孔24。根据一些实施例，封装组件40包括器件管芯，器件管芯可以包括逻辑管芯、存储器管芯、输入输出(IO)管芯等。器件管芯可以包括中央处理单元(CPU)管芯、图形处理单元(GPU)、，移动应用管芯、串行器/解串器(SerDes)管芯、外周组件互连快速(PCiE)管芯、串行高级技术附接(SATA)管芯、微控制单元(MCU)管芯、应用处理器(AP)管芯等。存储器管芯可以包括动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等。封装组件40还可以包括片上系统(SoC)管芯、存储器堆叠件(诸如高带宽存储器(HBM)立方体)等。封装组件40还可以包括独立无源器件(IPD)管芯，IPD管芯是其中包括无源器件并且没有有源器件的分立器件管芯。例如，IPD管芯可以是电容器管芯、电阻器管芯、电感器管芯等。作为示例，电容器管芯可以是多层陶瓷芯片电容器(MLCC)。执行回流以使焊料区域42回流，使得封装组件40接合至中介层22。在中介层22的每个上，可以存在接合在其上的多个封装组件40。例如，如图8至图15所示，接合至相同封装组件20的封装组件40可以包括多种不同类型的管芯40A、40B和40C，作为示例，如参考图8至图15所描述的。
接下来，参考图3，用底部填充物44填充封装组件40和封装组件20之间的间隙。底部填充物44可以包括聚合物或环氧树脂，并且可以在其中包括填充物颗粒。相应的工艺示出为图30所示的工艺流程200中的工艺204。密封剂46密封在封装组件40上，例如，使用暴露成型。根据本发明的一些实施例，密封剂46包括模塑料，该模塑料包括基底材料和混合在基底材料中的填充物。基底材料可以包括聚合物、树脂、环氧树脂等。填充物可以由二氧化硅、氧化铝、氧化硅等的球形颗粒形成。执行固化工艺以固化和凝固密封剂46。根据一些实施例，封装组件40掩埋在密封剂46中。
在密封剂46固化之后，可以执行诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以去除密封剂46的多余部分，该多余部分位于封装组件40的顶面上方。在图4中示出了抛光的结构。根据本发明的一些实施例，由于平坦化工艺，封装组件40中的一些或全部的衬底(诸如硅衬底)暴露。
图4至图6示出了在封装组件20的后侧上形成后侧结构。参考图4，提供了载体48，并且离型膜50涂布在载体48上。载体48由透明材料形成，并且可以是玻璃载体、陶瓷载体、有机载体等。离型膜50与载体48的顶面物理接触。离型膜50可以由光热转换(LTHC)涂层材料形成。离型膜50可以通过涂布施加到载体48上。根据本发明的一些实施例，LTHC涂层材料能够在光/辐射(诸如激光束)的热量下分解，并且可以从放置和形成在其上的结构释放载体48。
根据一些实施例，例如，通过作为粘合剂膜的管芯附接膜(DAF)52将如图3所示的结构附接/接合至离型膜50。相应的工艺示出为图30所示的工艺流程200中的工艺206。封装组件40中的一些或全部可以与DAF 52接触，并且衬底23的后表面暴露。
接下来，如图5所示，执行后侧研磨工艺以减薄衬底23，直到暴露贯通孔24。相应的工艺示出为图30所示的工艺流程200中的工艺208。然后可以稍微地蚀刻衬底23，使得贯通孔24的顶部从剩余的衬底23突出。如图6所示，在随后的工艺中，介电层54形成在半导体衬底23的后侧上。介电层54的形成可以包括沉积诸如氧化硅的介电材料，以及执行平坦化工艺以去除介电材料的比贯通孔24的顶面高的部分。介电材料的剩余部分是介电层54。
在随后的工艺中，可以形成金属焊盘56和介电层58。相应的工艺示出为如图30所示的工艺流程200中的工艺210。金属焊盘56可以由铝、铝铜等形成。根据本发明的一些实施例，形成介电层58以覆盖金属焊盘56的边缘部分，同时使金属焊盘56的中心部分暴露。介电层58可以由无机和/或有机材料形成，诸如氧化硅、氮化硅、聚酰亚胺、聚苯并恶唑(PBO)等。
电连接件60形成为电连接至贯通孔24。相应的工艺也示出为如图30所示的工艺流程200中的工艺210。根据一些实施例，电连接件60是通过镀形成的金属柱。根据其他实施例，电连接件60是焊料区域。保护层62可以形成为覆盖电连接件60。根据一些实施例，保护层62由诸如聚酰亚胺、PBO等的聚合物形成。在整个说明书中，DAF 52上方的结构称为重建晶圆64。
然后，例如通过将光投射到离型膜50上，将重建晶圆64从载体48脱粘，并且光(诸如激光束)穿过透明载体48。相应的工艺示出为如图30所示的工艺流程200中的工艺212。离型膜50因此分解，并且从载体48释放重建晶圆64。可以在清洁工艺中去除DAF 52。
接下来，对重建晶圆64执行分割(切割)工艺，以将重建晶圆64锯成多个构件66，图7中示出了构件66。相应的工艺也示出为如图30所示的工艺流程200中的工艺212。每个构件66包括一个中介层22(图1)和接合在其上的相应封装组件40。根据一些实施例，构件66是大封装件，其尺寸可以在约2500mm2至约14400mm2的范围内。
应当理解，图1至图7示出了一些示例性构件66的形成，该构件66是基于中介层形成的，器件管芯接合在中介层上。根据本发明的其他实施例，构件66可以是衬底上晶圆上芯片(CoWoS)封装件、集成扇出(InFO)封装件或其他类型的3DIC结构。
图8至图15示出了根据本发明的一些实施例的构件66的示例布局。图8示出了根据一些实施例的构件66，其中构件66包括逻辑管芯40A和位于逻辑管芯40A旁边的一个或多个存储器或IO(在下文中称为存储器/IO)管芯40B。在整个说明书中，逻辑管芯40A、存储器/IO管芯40B和IPD管芯40C统称为器件管芯40或封装组件40。存储器/IO管芯40B可以放置在逻辑管芯40A的一侧。图9示出了根据本发明的可选实施例的构件66，其中构件66包括逻辑管芯40A和放置在逻辑管芯40A的相对侧上的存储器/IO管芯40B。
图10示出了根据一些实施例的构件66，其中构件66包括两个或多个逻辑管芯40A以及与围绕逻辑管芯40A的环对准的存储器/IO管芯40B。存储器/IO管芯40B可以沿着构件66的外周布置。图11示出了根据一些实施例的构件66，其中构件66包括四个逻辑管芯40A，每个逻辑管芯40A伴随并电连接和信号连接至服务存储器/IO管芯40B。存储器/IO管芯40B也与围绕逻辑管芯40A的环对准，逻辑管芯40A可以形成阵列。
图12示出了根据一些实施例的构件66，其中构件66包括逻辑管芯40A和位于逻辑管芯40A的一侧上的一个或多个存储器/IO管芯40B。多个IPD管芯40C与围绕逻辑管芯40A和存储器/IO管芯40B的环对准。IPD管芯40C可以沿着构件66的外周布置。图13示出了与图12中的结构相似的结构，除了存储器/IO管芯40B位于逻辑端40A的相对侧上。
图14示出了根据一些实施例的构件66，其中构件66包括两个或多个逻辑管芯40A以及与围绕逻辑管芯40A的环对准的存储器/IO管芯40B。IPD管芯40C进一步沿着构件66的外周与环对准，并且围绕存储器/IO管芯40B。图15示出了根据一些实施例的构件66，其中构件66包括形成阵列的多个逻辑管芯40A，其中逻辑管芯40A中的每个都伴随并且电连接和信号连接至服务存储器/IO管芯40B。IPD管芯40C进一步沿着构件66的外周与环对准，并且围绕存储器/IO管芯40B。
图16至图24示出了根据本发明的一些实施例的系统封装件的形成中的中间阶段。参考图16，提供了载体68，并且离型膜70涂布在载体68上。根据一些实施例，在离型膜70上形成介电缓冲层72。根据可选实施例，省略了介电缓冲层72。载体68、离型膜70和介电缓冲层72的材料可以分别选自如图4所示的用于形成载体48、离型膜50和DAF 52的同一组候选材料，并且在此不再重复。
图16进一步示出了构件66、裸管芯76和IPD管芯78的放置/附接。相应的工艺示出为图30所示的工艺流程200中的工艺214。裸管芯可以是从相应的晶圆上锯且并且未进一步封装的器件管芯。根据一些实施例，裸管芯包括逻辑管芯、存储器管芯、SoC管芯等。构件66、裸管芯76和IPD管芯78通过DAF 74附接至介电缓冲层72。根据本发明的一些实施例，DAF74与构件66、裸管芯76和IPD管芯78的一些或全部的半导体衬底物理接触。在介电缓冲层72上可以放置有多组构件66、裸管芯76和IPD管芯78。构件66可以彼此相同，或者可以彼此不同。例如，不同的构件66中的管芯40的数量可以彼此相同或彼此不同。不同的构件66中的管芯40的类型也可以彼此相同或彼此不同。
接下来，如图17所示，分配密封剂80以密封构件66、裸管芯76和IPD管芯78。然后固化密封剂80。相应的工艺示出为图30中所示的工艺流程200中的工艺216。密封剂80填充构件66、裸管芯76和IPD管芯78之间的间隙。密封剂80可以包括模塑料、模制底部填充物、环氧树脂和/或树脂。由于已经在分割工艺中锯切了构件中的密封剂46(图7)，因此密封剂46和密封剂80之间存在可区分的界面。例如，密封剂46中的球形填充物颗粒在锯切时将变成部分颗粒，使密封剂46和密封剂80之间的界面是可区分的。
将密封剂80分配到一定层级，使得密封剂80的顶面高于构件66中的电连接件60和保护层62的顶端。当由模塑料或模制底部填充物形成时，密封剂80可以包括基底材料以及基底材料中的填充物颗粒(未示出)，基底材料可以是聚合物、树脂、环氧树脂等。填充物颗粒可以是SiO2、Al2O3、二氧化硅等的介电颗粒，介电颗粒可以具有球形形状。而且，球形填充物颗粒可以具有相同或不同的直径。
如图18所示，在分配密封剂80之后，执行诸如CMP工艺或机械研磨工艺的平坦化工艺，以平坦化构件66的密封剂80、保护层62和电连接件60。结果，裸管芯76和IPD管芯78的电连接件全部暴露。相应的工艺示出为如图30所示的工艺流程200中的工艺218。
在随后的工艺中，互连结构86形成在密封剂80上方。图19和图20分别示出了互连结构86的第一部分和第二部分的形成。相应的工艺示出为图30所示的工艺流程200中的工艺220和222。根据本发明的一些实施例，互连结构86包括介电层82A和位于介电层82A上方的介电层82B。每个介电层82B可以比任何介电层82A厚。根据本发明的一些实施例，介电层82A由诸如PBO、聚酰亚胺、BCB等的光敏材料形成，并且介电层82B由非光敏材料形成，诸如模塑料、模制底部填充材料、氧化硅、氮化硅等。根据可选实施例，介电层82A和82B均由光敏材料形成。
RDL 84A形成在介电层82A中，并且RDL 84B形成在介电层82B中。根据一些实施例，RDL 84B比RDL 84A厚和/或宽，并且可以用于远程电气布线，而RDL 84A可以用于短程电气布线。电连接件88形成在互连结构86的表面上。电连接件88和RDL 84A和84B电连接至构件66、裸管芯76和IPD管芯78。在整个说明书中，介电缓冲层72上方的结构(或“离型膜70”，如果没有形成介电缓冲层72)称为InFO封装件92，InFO封装件92也是重建晶圆。
在随后的工艺中，将载体68从InFO封装件92脱粘。根据本发明的一些实施例，例如在清洁工艺或研磨工艺中去除DAF 74。相应的工艺示出为如图30所示的工艺流程200中的工艺224。图21中示出了所得的InFO封装件92。贯通孔98可以形成为穿透InFO封装件92。相应的工艺也示出为如图30所示的工艺流程200中的工艺224。可以通过激光钻孔、使用钻头的钻孔等形成贯通孔98。根据一些实施例，构件66以包括多个行和多个列的阵列的形式分布，如图25至图29所示。多个水平间距和多个垂直间距分别将行和列彼此分隔开。贯通孔98可以位于水平间距和垂直间距的重叠区处。然后将InFO封装件92附接至胶带94，胶带94进一步附接至框架96，如图21所示。
图22示出了例如通过焊料区域102将插座104和一个或多个连接件106接合至InFO封装件92。相应的工艺示出为如图30所示的工艺流程200中的工艺226。根据一些实施例，插座104具有引脚孔108，并且引脚孔108中的(阴)电连接件电连接至焊料区域102以及下面的RDL、管芯和构件。用于所得系统封装件110(图24)与其他系统之间的信号连接的连接件106也接合至InFO封装件92。连接件106可以包括适配器、插座等。连接件106可以包括多个信号路径，诸如多个引脚、引脚孔等，并且可以用作用于系统封装件110与其他系统之间的并行或串行信号传输的总线。例如，示意性示出的引线107连接至连接件106，并且用于将系统封装件110连接至其他系统。尽管未示出，但是可以在插座104与InFO封装件92之间以及在连接件106与InFO封装件92之间分配底部填充物以保护焊料区域102。
在整个说明书中，胶带94上方的组件统称为系统封装件110。在随后的工艺中，将系统封装件110从胶带94脱粘，并且图23中示出了得到的系统封装件110。相应的工艺示出为在如图30中所示的工艺流程200中的工艺228。
接下来，如图24所示，功率模块112连接至插座104以扩展系统封装件110。相应的工艺示出为如图30所示的工艺流程200中的工艺230。例如，功率模块112包括引脚114，引脚114插入插座104中的引脚孔108(图23)中。功率模块112可以包括用于调节功率和/或其他类型的功率管理电路的脉冲宽度调制(PWM)电路。功率模块112将调节的功率提供给下面的构件66、裸管芯76和IPD管芯78。功率模块112也连接至IPD管芯78以进行功率管理和功率存储。功率模块112例如通过连接线(该连接线可以位于功率模块112上方并且连接至功率模块112)接收电源(例如AC电源)。未示出电源和连接线。
根据本发明的一些实施例，功率模块112和构件116可以一一对应，其中每个功率模块112与一个(并且仅一个)构建116对应(并且可以重叠)，并且每个构件116对应于一个(并且仅一个)功率模块112。根据本发明的可选实施例，功率模块112和构件116可以具有N对一的对应关系，其中多个功率模块112对应于同一构件66，并且向同一构件66提供功率。根据本发明的又一可选实施例，功率模块112和构件116可以具有一对N的对应关系，其中一个功率模块112对应于多个构件66并且向多个构件66提供功率。
图24还示出了冷却板(散热板)120、支架124和环130的安装，以进一步扩展系统封装件110。相应的工艺示出为如图30所示的工艺流程200中的工艺232。冷却板120通过热界面材料(TIM)122附接至InFO封装件92，该TIM是具有良好导热性的粘合膜。冷却板120可以由诸如铜、铝、不锈钢、镍等的金属材料形成。支架124通过螺钉126和螺栓128安装。根据一些实施例，支架124的底面与插座104的顶面接触。支架124可以由诸如铜、不锈钢等的金属材料形成。在系统封装件110的顶视图中，支架124可以形成栅格(网格)，该栅格包括与构件66的行和列之间的间距重叠的多个水平条和多个垂直条(图25至图29)，水平条和垂直条连接在一起以形成栅格。支架124、螺钉126和螺栓128组合用于将插座104与InFO封装件92和冷却板120固定在一起。此外，金属环130是压在InFO封装件92的外周区域上的环，用于使用螺钉132和螺栓134将InFO封装件92和冷却板120固定在一起。所得的系统封装件110也是可以安装在更大系统中的系统模块。
图25至图29示出了根据本发明的一些实施例的InFO封装件92中的构件66、裸管芯76和IPD管芯78的布局。应当理解，每个InFO封装件92中的构件66可以具有彼此相同的结构，或者可以具有不同的结构和布局，作为示例，结构和布局可以选自图8至图15。根据一些实施例，InFO封装件92是超大型封装件，其尺寸可大于约10000mm2。此外，取决于构件66的尺寸，InFO封装件92的尺寸可以显著大于10000mm2，例如，在约50000mm2至100000mm2之间的范围内或更大。
图25示出了InFO封装件92，其中多个构件66形成阵列，没有IPD管芯和裸管芯位于构件66之间。裸管芯76可以是IO管芯或其他类型的器件管芯，布置在阵列的外周处，并且没有IO管芯和裸管芯放置为围绕阵列。图26示出了InFO封装件92，其中，多个构件66形成阵列，裸管芯76放置在构件66之间。裸管芯76也布置在阵列的外周处。图27示出了InFO封装件92，其中多个构件66形成阵列，并且在阵列中没有放置IO管芯和裸管芯。裸管芯76布置为与围绕构件66的阵列的环对准。多个IPD管芯78也沿着围绕构件66的阵列的环布置。图28示出了与图25中所示的InFO封装件92相似的InFO封装件92，除了将IPD管芯78放置在构件66的阵列内之外。图29示出了与图25中所示的InFO封装件92相似的InFO封装件92，除了IPD管芯78和裸管芯76放置在构件66的阵列内之外。
根据本发明的一些实施例，如图25、图26、图27、图28和图29所示，InFO封装件92处于晶圆水平，并且具有圆形顶视图形状。根据这些实施例，如图16至图21所示的工艺中形成的InFO封装件92未被锯切，并且以晶圆形式使用。根据其他实施例，图25、图26、图27、图28和图29中的InFO封装件92的圆形边缘被切割以减小所得系统封装件的尺寸。虚线142表示通过切割形成的笔直边缘。在又一可选实施例中，InFO封装件92可以具有矩形顶视图形状。根据这些实施例，多个相同的InFO封装件92可以作为大的重建晶圆的一部分同时形成，然后从大的重建晶圆锯切。
在以上示出的实施例中，根据本发明的一些实施例讨论了一些工艺和部件，以形成三维(3D)封装件。也可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，该测试焊盘允许测试3D封装或3DIC、使用探针和/或探针卡等。可以对中间结构以及最终结构执行验证测试。另外，本文公开的结构和方法可以与结合了已知良管芯的中间验证的测试方法结合使用，以增加产量并且降低成本。
本发明的实施例具有一些有利特征。在常规封装件中，将器件管芯接合至中介层晶圆以形成晶圆上芯片(CoW)结构，然后将CoW结构锯切以分离晶圆中的中介层。然后将得到的分离的CoW结构接合至封装衬底，以形成衬底上晶圆上芯片(CoWoS)结构，以形成系统封装件。可以理解，由于封装衬底在最终封装件中彼此分隔开，因此所得系统封装件中的器件管芯不能通过封装衬底进行通信。因此，CoWoS结构进一步接合至印刷电路板(PCB)，并且CoWoS结构之间的通信通过PCB。因此，器件管芯之间的信号通信必须通过多个组件，包括中介层、封装衬底和PCB。所得的通信路径很长，这会导致信号延迟。这使高速通信变得困难，尤其是对于超大型封装件。在本申请的实施例中，互连结构86(诸如RDL 84A)可以用于构件之间的横向通信，并且经过较少组件的信号路径非常短，使得高速通信成为可能。
另外，在常规结构中，功率模块接合至PCB，并且与CoWoS结构处于同一层级。当形成超大型系统封装件时，横向供电路径变得非常长，有时长达数十毫米。这显著增加了电源路径，并且对于在短时间内汲取大电流的应用，供电不够快。在本发明的实施例中，功率模块位于互连结构的与构件和器件管芯相对的侧上，并且供电路径不会比互连结构的厚度加上焊料区域的高度长太多，供电路径可以小到1毫米或2毫米或更短。因此显著改善供电能力。
根据本发明的一些实施例，一种封装件包括：构件，该构件包括器件管芯；中介层，与器件管芯接合；以及第一密封剂，将器件管芯密封在其中。封装件还包括第二密封剂，第二密封剂将构件密封在其中；互连结构，位于第二密封剂上方，其中该互连结构包括电耦合至器件管芯的再分布线；功率模块，位于互连结构上方，其中，功率模块通过互连结构电耦合至构件。在实施例中，构件包括多个介电层，并且多个介电层中的底部介电层与第二密封剂和器件管芯物理接触。在实施例中，器件管芯是逻辑管芯，并且构件还包括密封在第一密封剂中的存储器堆叠件。在实施例中，封装件还包括冷却板；热界面材料，包括与器件管芯的半导体衬底的表面接触的第一表面和与冷却板接触的第二表面；以及螺钉，穿透第二密封剂、冷却板和热界面材料。在实施例中，封装件还包括位于第二密封剂中的多个构件，其中多个构件形成阵列。在实施例中，封装件还包括与功率模块处于同一层级的多个功率模块，其中，多个功率模块以一一对应的方式电耦合至多个构件。在实施例中，封装件还包括形成网格的金属支架；以及多个螺钉和螺栓，将金属支架固定至互连结构和第二密封剂。在实施例中，封装件还包括接合至互连结构的插座，功率模块连接至插座，其中金属支架接触插座。在实施例中，封装件还包括密封在第二密封剂中的多个独立的无源器件管芯。在实施例中，封装件还包括密封在第二密封剂中的多个裸管芯。
根据本发明的一些实施例，封装件包括形成阵列的构件的阵列，其中，构件的阵列中的每个构件包括第一模塑料；逻辑管芯，位于第一模塑料中；以及存储器管芯，位于第一模塑料中；第二模塑料，构件的阵列位于第二模塑料中；互连结构，横向扩展超出阵列，其中互连结构包括多个介电层；以及多条再分布线，位于多个介电层中并且电耦合至阵列；以及功率模块，位于第二模塑料的外部，其中功率模块电耦合至阵列。在实施例中，功率模块位于互连结构上方。在实施例中，封装件还包括多个功率模块，其中功率模块是多个功率模块中的一个，其中多个功率模块与阵列重叠。在实施例中，封装件还包括连接件，该连接件位于互连结构上方并且通过焊料区域接合至互连结构，其中，该连接件配置为向阵列提供电信号。
根据本发明的一些实施例，一种方法包括：将多个器件管芯接合至中介层晶圆；将多个器件管芯密封在第一密封剂中；抛光中介层晶圆以露出中介层晶圆的衬底中的贯通孔；形成连接至贯通孔的电连接件；分割中介层晶圆和第一密封剂以形成构件；将构件密封在第二密封剂中；在第二密封剂上方形成与第二密封剂接触的扇出互连结构；以及将功率模块附接在扇出互连结构上方。在实施例中，该方法还包括在第二密封剂中密封构件的阵列，其中，该构件的阵列包括构件。在实施例中，该方法还包括在扇出互连结构上方附接多个功率模块，其中，多个功率模块中的每个电连接至构件的阵列中的一个。在实施例中，该方法还包括将多个裸管芯密封在第二密封剂中。在实施例中，该方法还包括将多个独立的无源器件管芯密封在第二密封剂中。在实施例中，该方法还包括在扇出互连结构上方连接包括多个信号路径的连接件。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同配置并且不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种封装件，包括：
构件，包括：
器件管芯；
中介层，与所述器件管芯接合；和
第一密封剂，将所述器件管芯密封在其中；
第二密封剂，将所述构件密封在其中；
互连结构，位于所述第二密封剂上方，其中，所述互连结构包括电耦合至所述器件管芯的再分布线；以及
功率模块，位于所述互连结构上方，其中，所述功率模块通过所述互连结构电耦合至所述构件。
2.根据权利要求1所述的封装件，其中，所述构件包括多个介电层，并且所述多个介电层中的底部介电层与所述第二密封剂和所述器件管芯物理接触。
3.根据权利要求1所述的封装件，其中，所述器件管芯是逻辑管芯，并且所述构件还包括密封在所述第一密封剂中的存储器堆叠件。
4.根据权利要求1所述的封装件，还包括：
冷却板；
热界面材料，包括与所述器件管芯的半导体衬底的表面接触的第一表面和与所述冷却板接触的第二表面；以及
螺钉，穿透所述第二密封剂、所述冷却板和所述热界面材料。
5.根据权利要求1所述的封装件，还包括：
多个构件，位于所述第二密封剂中，其中，所述多个构件形成阵列。
6.根据权利要求5所述的封装件，还包括：
多个功率模块，与所述功率模块处于同一层级，其中，所述多个功率模块以一一对应的方式电耦合至所述多个构件。
7.根据权利要求1所述的封装件，还包括：
金属支架，形成网格；以及
多个螺钉和螺栓，将所述金属支架固定至所述互连结构和所述第二密封剂。
8.根据权利要求7所述的封装件，还包括：
插座，接合至所述互连结构，所述功率模块连接至所述插座，其中，所述金属支架与所述插座接触。
9.一种封装件，包括：
构件的阵列，形成阵列，其中，所述构件的阵列中的每个构件包括：
第一模塑料；
逻辑管芯，位于所述第一模塑料中；和
存储器管芯，位于所述第一模塑料中；
第二模塑料，所述构件的阵列位于所述第二模塑料中；
互连结构，横向扩展超出所述阵列，其中，所述互连结构包括：
多个介电层；和
多条再分布线，位于所述多个介电层中并且电耦合至所述阵列；以及
功率模块，位于所述第二模塑料的外部，其中，所述功率模块电耦合至所述阵列。
10.一种形成封装件的方法，包括：
将多个器件管芯接合至中介层晶圆；
将所述多个器件管芯密封在第一密封剂中；
抛光所述中介层晶圆以露出所述中介层晶圆的衬底中的贯通孔；
形成连接至所述贯通孔的电连接件；
分割所述中介层晶圆和所述第一密封剂以形成构件；
将所述构件密封在第二密封剂中；
在所述第二密封剂上方形成与所述第二密封剂接触的扇出互连结构；以及
在所述扇出互连结构上方附接功率模块。
CN202010596772.1A 2019-06-25 2020-06-28 封装件及其形成方法 Active CN112133696B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962866227P 2019-06-25 2019-06-25
US62/866,227 2019-06-25
US16/671,927 US11296062B2 (en) 2019-06-25 2019-11-01 Three-dimension large system integration
US16/671,927 2019-11-01

Publications (2)

Publication Number Publication Date
CN112133696A true CN112133696A (zh) 2020-12-25
CN112133696B CN112133696B (zh) 2023-04-18

Family

ID=73747722

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010596772.1A Active CN112133696B (zh) 2019-06-25 2020-06-28 封装件及其形成方法

Country Status (5)

Country Link
US (2) US11296062B2 (zh)
KR (1) KR102319275B1 (zh)
CN (1) CN112133696B (zh)
DE (1) DE102019130466B4 (zh)
TW (1) TWI731645B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11296062B2 (en) * 2019-06-25 2022-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimension large system integration
US11837575B2 (en) * 2019-08-26 2023-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding passive devices on active device dies to form 3D packages
US11462418B2 (en) * 2020-01-17 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11600526B2 (en) * 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11444002B2 (en) * 2020-07-29 2022-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
US11764171B2 (en) * 2021-04-27 2023-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure and method
US20230178536A1 (en) 2021-12-07 2023-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Trimming and Sawing Processes in the Formation of Wafer-Form Packages

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1630076A (zh) * 2003-12-19 2005-06-22 株式会社日立产机系统 电路组件
CN101523597A (zh) * 2006-12-27 2009-09-02 爱信艾达株式会社 电子电路装置及其制造方法
CN101681907A (zh) * 2007-11-30 2010-03-24 松下电器产业株式会社 散热结构体基板和使用其的模块及散热结构体基板的制造方法
CN104377171A (zh) * 2013-08-16 2015-02-25 台湾积体电路制造股份有限公司 具有中介层的封装件及其形成方法
CN105023837A (zh) * 2014-04-28 2015-11-04 台湾积体电路制造股份有限公司 划线结构及其形成方法
CN106997855A (zh) * 2015-12-31 2017-08-01 台湾积体电路制造股份有限公司 集成电路封装件及其形成方法
CN107731761A (zh) * 2017-09-30 2018-02-23 睿力集成电路有限公司 底部半导体封装件及其制造方法
TW201810575A (zh) * 2016-06-23 2018-03-16 三星電機股份有限公司 扇出型半導體封裝模組
US20180156865A1 (en) * 2016-12-06 2018-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package structure and testing method using the same
CN108231716A (zh) * 2016-12-09 2018-06-29 胡迪群 封装结构及其制造方法
CN108400119A (zh) * 2017-02-08 2018-08-14 美光科技公司 半导体封装及其制造方法
US20180350747A1 (en) * 2017-06-05 2018-12-06 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor device
CN109390314A (zh) * 2017-08-04 2019-02-26 三星电机株式会社 半导体封装件的连接系统
CN109904134A (zh) * 2017-12-07 2019-06-18 胡迪群 基板结构及电子装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7560309B1 (en) 2005-07-26 2009-07-14 Marvell International Ltd. Drop-in heat sink and exposed die-back for molded flip die package
US7553752B2 (en) * 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
US8618654B2 (en) * 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
US8105875B1 (en) * 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US8268677B1 (en) * 2011-03-08 2012-09-18 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer over semiconductor die mounted to TSV interposer
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US8970023B2 (en) * 2013-02-04 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming same
US10418298B2 (en) * 2013-09-24 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual fan-out semiconductor package
US10068862B2 (en) * 2015-04-09 2018-09-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a package in-fan out package
US9520333B1 (en) * 2015-06-22 2016-12-13 Inotera Memories, Inc. Wafer level package and fabrication method thereof
US10217719B2 (en) * 2017-04-06 2019-02-26 Micron Technology, Inc. Semiconductor device assemblies with molded support substrates
US10393799B2 (en) * 2017-09-30 2019-08-27 Intel Corporation Electronic device package
KR102449368B1 (ko) * 2017-10-20 2022-09-30 삼성전기주식회사 다층 인쇄회로기판
US10515827B2 (en) * 2017-10-31 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package with recessed interposer substrate
DE102018125372B4 (de) 2017-12-08 2021-11-11 Taiwan Semiconductor Manufacturing Co., Ltd. Elektromagnetischer abschirmungsaufbau in einem info-package und verfahren zu dessen herstellung
US11387177B2 (en) * 2019-06-17 2022-07-12 Taiwan Semiconductor Manufacturing Company Ltd. Package structure and method for forming the same
US11296062B2 (en) * 2019-06-25 2022-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimension large system integration

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1630076A (zh) * 2003-12-19 2005-06-22 株式会社日立产机系统 电路组件
CN101523597A (zh) * 2006-12-27 2009-09-02 爱信艾达株式会社 电子电路装置及其制造方法
CN101681907A (zh) * 2007-11-30 2010-03-24 松下电器产业株式会社 散热结构体基板和使用其的模块及散热结构体基板的制造方法
CN104377171A (zh) * 2013-08-16 2015-02-25 台湾积体电路制造股份有限公司 具有中介层的封装件及其形成方法
CN105023837A (zh) * 2014-04-28 2015-11-04 台湾积体电路制造股份有限公司 划线结构及其形成方法
CN106997855A (zh) * 2015-12-31 2017-08-01 台湾积体电路制造股份有限公司 集成电路封装件及其形成方法
TW201810575A (zh) * 2016-06-23 2018-03-16 三星電機股份有限公司 扇出型半導體封裝模組
US20180156865A1 (en) * 2016-12-06 2018-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package structure and testing method using the same
CN108231716A (zh) * 2016-12-09 2018-06-29 胡迪群 封装结构及其制造方法
CN108400119A (zh) * 2017-02-08 2018-08-14 美光科技公司 半导体封装及其制造方法
US20180350747A1 (en) * 2017-06-05 2018-12-06 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor device
CN109390314A (zh) * 2017-08-04 2019-02-26 三星电机株式会社 半导体封装件的连接系统
CN107731761A (zh) * 2017-09-30 2018-02-23 睿力集成电路有限公司 底部半导体封装件及其制造方法
CN109904134A (zh) * 2017-12-07 2019-06-18 胡迪群 基板结构及电子装置

Also Published As

Publication number Publication date
US11296062B2 (en) 2022-04-05
US20200411488A1 (en) 2020-12-31
DE102019130466A1 (de) 2020-12-31
DE102019130466B4 (de) 2023-01-19
TWI731645B (zh) 2021-06-21
KR20210001879A (ko) 2021-01-06
TW202101691A (zh) 2021-01-01
CN112133696B (zh) 2023-04-18
US20220223572A1 (en) 2022-07-14
KR102319275B1 (ko) 2021-11-02

Similar Documents

Publication Publication Date Title
CN112133696B (zh) 封装件及其形成方法
CN110676223B (zh) 封装件和形成封装件的方法
KR102318305B1 (ko) 반도체 패키지
US11621205B2 (en) Underfill structure for semiconductor packages and methods of forming the same
US10431738B2 (en) Integrated fan-out package and method for fabricating the same
CN110323143B (zh) 包括多芯片模块的电子卡
US9831214B2 (en) Semiconductor device packages, packaging methods, and packaged semiconductor devices
US20180040587A1 (en) Vertical Memory Module Enabled by Fan-Out Redistribution Layer
KR101684787B1 (ko) 반도체 패키지 디바이스 및 그 형성 방법
US11798925B2 (en) IPD modules with flexible connection scheme in packaging
CN112436001A (zh) 封装件及其形成方法
US20230290747A1 (en) Heat dissipating features for laser drilling process
CN221041116U (zh) 集成电路封装
CN116779556A (zh) 半导体封装件及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant