CN106997855A - 集成电路封装件及其形成方法 - Google Patents

集成电路封装件及其形成方法 Download PDF

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Publication number
CN106997855A
CN106997855A CN201611222981.XA CN201611222981A CN106997855A CN 106997855 A CN106997855 A CN 106997855A CN 201611222981 A CN201611222981 A CN 201611222981A CN 106997855 A CN106997855 A CN 106997855A
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China
Prior art keywords
contact pad
tube cores
die
tube core
tube
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CN201611222981.XA
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English (en)
Inventor
潘国龙
刘重希
蔡豪益
陈玉芬
郑余任
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN106997855A publication Critical patent/CN106997855A/zh
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    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/0023—Packaging together an electronic processing unit die and a micromechanical structure die
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/181—Encapsulation
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    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

本发明的实施例提供了一种集成电路封装件以及其形成方法。一种方法包括将第一管芯和第二管芯附接至载体，第一管芯具有第一接触焊盘，第二管芯具有第二接触焊盘，第一接触焊盘和第二接触焊盘具有不同的结构。释放层形成在第一管芯和第二管芯上方。在载体和释放层之间注射包封剂。在第一管芯、第二管芯和包封剂上方形成一个或多个再分布层(RDL)，第一接触焊盘和第二接触焊盘与一个或多个RDL电接触。

Description

集成电路封装件及其形成方法
技术领域
本发明的实施例涉及半导体领域，更具体地涉及集成电路封装件及其形成方法。
背景技术
半导体器件用于各种电子应用中，诸如个人电脑、手机、数码相机和其他电子设备。通常通过以下步骤来制造半导体器件：在半导体衬底上方相继沉积绝缘或介电层、导电层和半导体材料层；以及使用光刻来图案化该多个材料层，以在该多个材料层上形成电路组件和元件。通常，在单个半导体晶圆上制造数十或数百的集成电路。通过沿着划割线锯切集成电路来分割单独的管芯。然后，将单个的管芯单独封装在多芯片模块中，或封装在其他类型的封装件中。
由于许多电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成度的不断提高，所以半导体工业经历了快速发展。在很大程度上，集成度的这种提高源自于最小部件尺寸的不断减小(例如，将半导体工艺节点朝向亚20nm节点缩小)，这允许更多的组件集成在给定区域内。随着对小型化的需求，近来已经发展了更高速度和更大带宽以及更低功耗和延迟，已经产生了对用于半导体管芯的一种更小且更富创造性的封装技术的需要。
随着半导体技术的进一步发展，已经出现了堆叠的半导体器件(例如，三维集成电路(3DIC))作为有效替代以进一步减小半导体器件的物理尺寸。在堆叠式半导体器件中，在不同半导体晶圆上制造诸如逻辑、存储器、处理器电路等的有源电路。两个或更多的半导体晶圆可以安装或堆叠在彼此的顶部上以进一步降低半导体器件的形状因数。叠层封装(POP)器件是一种类型的3DIC，其中，封装管芯并且然后将管芯与另一封装的一个管芯或多个管芯封装在一起。封装件上芯片(COP)器件是另一种类型的3DIC，其中，封装管芯并且然后将管芯与另一管芯或多个管芯封装在一起。
发明内容
本发明的实施例提供了一种形成集成电路封装件的方法，包括：将第一管芯和第二管芯附接至载体，所述第一管芯具有第一接触焊盘，所述第二管芯具有第二接触焊盘，所述第一接触焊盘和所述第二接触焊盘具有不同的结构；在所述第一管芯和所述第二管芯上方形成释放层；在所述载体和所述释放层之间注射包封剂；以及在所述第一管芯、所述第二管芯和所述包封剂上方形成一个或多个再分布层(RDL)，所述第一接触焊盘和所述第二接触焊盘与所述一个或多个再分布层电接触。
本发明的实施例还提供了一种形成集成电路封装件的方法，包括：将第一管芯的第一侧附接至载体，所述第一管芯具有：位于所述第一管芯的第二侧上的第一接触焊盘，所述第一管芯的所述第二侧与所述第一管芯的所述第一侧相对；和位于所述第一管芯的所述第二侧上的第一绝缘层，通过所述第一绝缘层中的开口暴露所述第一接触焊盘的至少一部分；将第二管芯的第一侧附接至所述载体，所述第二管芯具有：贯通孔，所述贯通孔从所述第二管芯的所述第一侧延伸至所述第二管芯的第二侧，所述第二管芯的所述第二侧与所述第二管芯的所述第一侧相对；位于所述第二管芯的所述第二侧上的第二绝缘层，所述贯通孔的至少一部分延伸穿过所述第二绝缘层；和位于所述第二绝缘层上方的第二接触焊盘，所述第二接触焊盘接触所述贯通孔；将释放层层压在所述第一接触焊盘、所述第二接触焊盘、所述第一绝缘层和所述第二绝缘层的顶面上方；在所述载体和所述释放层之间、以及在所述第一管芯和所述第二管芯之间的间隙中注射第一包封剂；以及在所述第一管芯、所述第二管芯和所述第一包封剂上方形成一个或多个再分布层(RDL)，所述第一接触焊盘和所述第二接触焊盘与所述一个或多个再分布层电接触。
本发明的实施例还提供了一种集成电路封装器件，包括：一个或多个再分布层(RDL)；第一管芯，位于所述一个或多个再分布层的第一侧上，所述第一管芯包括嵌在第一绝缘层中的第一接触焊盘，所述一个或多个再分布层的导电部件延伸穿过所述第一绝缘层并且接触所述第一接触焊盘；第二管芯，位于所述一个或多个再分布层的所述第一侧上，所述第二管芯包括：贯通孔，延伸穿过第二绝缘层；和第二接触焊盘，位于所述第二绝缘层上方，所述第二接触焊盘接触所述贯通孔，所述一个或多个再分布层的第三绝缘层的至少一部分沿着所述第二接触焊盘的侧壁延伸；以及第一包封剂，位于所述一个或多个再分布层的所述第一侧上，所述第一包封剂的至少一部分插在所述第一管芯和所述第二管芯之间。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1A、图1B、图2A、图2B、图3A、图3B、图4A、图4B、以及图5至图7是根据一些实施例的集成电路封装件的制造期间的各个处理步骤的顶视图和截面图。
图8A和图8B是根据一些实施例的附接至印刷电路板的堆叠的集成电路封装件的顶视图和截面图。
图9A和图9B是根据一些实施例的附接至印刷电路板的堆叠的集成电路封装件的顶视图和截面图。
图10A和图10B是根据一些实施例的附接至印刷电路板的堆叠的集成电路封装件的顶视图和截面图。
图11A和图11B是根据一些实施例的附接至印刷电路板的堆叠的集成电路封装件附的顶视图和截面图。
图12至图15是根据一些实施例的贯通孔和接触焊盘的制造期间的各个处理步骤的截面图。
图16是根据一些实施例示出的形成集成电路封装件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
在具体地描述所示出的实施例之前，通常描述所公开的实施例的特定优势特征和实施例。以下描述的是各种集成电路封装件及其形成方法。诸如以下描述的方法允许将具有不同接触焊盘结构的集成电路管芯封装至同一集成电路封装件中。因此，这样的方法允许更加灵活地将具有不同功能的集成电路管芯封装至同一集成电路封装件中。此外，诸如以下描述的方法允许消除特定的工艺步骤且允许降低制造成本。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。
图1A、图1B、图2A、图2B、图3A、图3B、图4A、图4B、以及图5至图7是根据一些实施例的在集成电路封装件的制造期间的各个处理步骤的顶视图和截面图，其中，“A”图表示顶视图以及“B”图表示沿相应的“A”图的B-B'线的截面图。
首先参考图1A和图1B，根据一些实施例示出了具有附接在其上的多个第一集成电路(IC)管芯107和多个第二IC管芯109的载体101。在一些实施例中，在载体101上方形成释放层103，在释放层103上方形成粘合层105，并且第一IC管芯107和第二IC管芯109附接至粘合层105。在一些实施例中，载体101可由硅、石英、玻璃等形成，并且提供对于随后的操作的机械支撑。在一些实施例中，释放层103可包括光热转换(LTHC)材料、紫外线(UV)胶(当暴露于UV辐射时，其失去了粘合性能)等，并且可使用旋涂工艺、印刷工艺、层压工艺等形成。在释放层103是由LTHC材料形成的一些实施例中，当暴露于光下时，释放层103部分地或全部地失去了其粘合强度且载体101可以容易地从第一IC管芯107和第二IC管芯109分离。粘合层105可以是管芯附接膜(DAF)或任何合适的粘合剂、环氧树脂、UV胶等，并且可使用旋涂工艺、印刷工艺、层压工艺等形成。在一些实施例中，例如，第一IC管芯107和第二IC管芯109使用拾取和放置装置附接至载体101。在其它实施例中，第一IC管芯107和第二IC管芯109可手动地或使用任何其它合适的方法附接至载体101。
在一些实施例中，第一IC管芯107和第二IC管芯109可以是互补金属氧化物半导体(CMOS)管芯、微机电系统(MEMS)管芯等。第一IC管芯107和第二IC管芯109可具有各种功能且可包括存储器管芯、微控制器单元(MCU)芯片、电源管理集成电路(PMIC)芯片、射频(RF)芯片、专用集成电路(ASIC)芯片、液晶显示器(LCD)、发光二极管(LED)显示器、触摸传感器、运动传感器、心率传感器、环境传感器，诸如温度传感器、压力传感器、湿度传感器、颗粒传感器等。在一些实施例中，第一IC管芯107和第二IC管芯109可以形成为晶圆的一部分，其随后地被分割为单独的第一IC管芯107和单独的第二IC管芯109。在一些实施例中，通过锯切、激光烧蚀等分割晶圆。随后地，可以在第一IC管芯107和第二IC管芯109上执行功能测试。因此，图1A和图1B中示出的第一IC管芯107和第二IC管芯109可仅包括已知良好管芯(KGD)，其已经通过了一个或多个功能质量测试。在示出的实施例中，第一IC管芯107是CMOS管芯并且第二IC管芯109是MEMS管芯。在其他实施例中，第一IC管芯107和第二IC管芯109可以是MEMS管芯。在又一实施例中，第一IC管芯107和第二IC管芯109可以是CMOS管芯。此外，如图1B中所示，第一IC管芯107和第二IC管芯109的顶侧具有不同的接触焊盘结构。然而，在其它实施例中，第一IC管芯107和第二IC管芯109具有类似的接触焊盘结构。
进一步参考图1A和图1B，在其中第一IC管芯107是CMOS管芯的一些实施例中，第一IC管芯107中的每个都包括衬底111、衬底111上的一个或多个有源和/或无源器件113以及衬底111和一个或多个有源和/或无源器件113上方的一个或多个金属化层115。在一些实施例中，衬底111可由硅形成，但是它还可由诸如硅、锗、镓、砷和它们的组合的其他III族、IV族和/或V族元素形成。衬底111还可为绝缘体上硅(SOI)的形式。SOI衬底可包括在绝缘体层(例如，掩埋氧化物等)上方形成的半导体材料层(例如，硅、锗等)，该绝缘体层形成在硅衬底上。此外，可使用的其他衬底包括多层衬底、梯度衬底、混合取向衬底、其任意组合等。
在一些实施例中，一个或多个有源和/或无源器件113可以包括诸如晶体管的各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件、电容器、电阻器、二极管、光电二极管、熔丝等。一个或多个金属化层115可包括在衬底111上方形成的且由相邻的ILD/IMD分离的层间介电层(ILD)/金属间介电层(IMD)和导电层(未示出)。例如，可通过诸如旋涂方法、化学汽相沉积(CVD)、等离子体增强的CVD(PECVD)等或其组合的本领域已知的任何合适的方法，由诸如磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、其化合物、其复合物、其组合等的低-k介电材料形成ILD/IMD。在一些实施例中，例如，可使用镶嵌工艺、双镶嵌工艺等在ILD/IMD中形成互连结构。在一些实施例中，互连结构可以包括铜、铜合金、银、金、钨、钽、铝等。在一些实施例中，互连结构可在衬底111上形成的一个或多个有源和/或无源器件113之间提供电连接。
在一些实施例中，第一IC管芯107的每个都还包括在一个或多个金属化层115上方形成的接触焊盘117、并且可以通过一个或多个金属化层115的各个互连结构电连接至一个或多个有源和/或无源器件113。在一些实施例中，接触焊盘117可以包括诸如铝、铜、钨、银、金、镍等或它们的组合的导电材料。在一些实施例中，例如，可以使用物理汽相沉积(PVD)、原子层沉积(ALD)、电化学镀、无电镀等或它们的组合来在一个或多个金属化层115上方形成导电材料。在导电材料是铝的一些实施例中，导电材料被图案化以形成接触焊盘117。在一些实施例中，可使用光刻技术图案化导电材料。通常，光刻技术涉及沉积光刻胶材料(未示出)，随后，对该光刻胶材料进行辐射(暴露)以及显影，以去除部分光刻胶材料。剩余的光刻胶材料保护下面的材料(诸如接触焊盘117的导电材料)免于随后的诸如蚀刻的处理步骤。可以将诸如反应离子蚀刻(RIE)或其他干蚀刻、各向同性或各向异性的湿蚀刻或任何其他合适的蚀刻的合适的蚀刻工艺或图案化工艺应用于导电材料，以去除导电材料的暴露部分，并且形成接触焊盘117。在导电材料为铝的一些实施例中，可使用80％磷酸、5％硝酸、5％乙酸和10％去离子(DI)水的混合物蚀刻导电材料。随后，例如，可使用灰化工艺和随后的湿清洗工艺去除光刻胶材料。
还参考图1A和图1B，钝化层119形成在衬底111和接触焊盘117上方。在一些实施例中，钝化层119可包括诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)等的可光图案化的介电材料的一层或多层，并且可使用旋涂工艺等形成。可以使用与光刻胶材料类似的光刻方法容易地图案化这种可光图案化的介电材料。在其他的实施例中，钝化层119可以包括一层或多层不可光图案化的介电材料，诸如氮化硅、氧化硅、氮氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)等，并且可以使用CVD、PVD、ALD、旋涂工艺等或它们的组合来形成。
在一些实施例中，在钝化层119中形成开口121以暴露接触焊盘117。在钝化层119是由可光图案化介电材料形成的一些实施例中，可使用与光刻胶材料类似的光刻方法图案化钝化层119。在钝化层119是由非可光图案化的介电材料形成的其他实施例中，在钝化层119上方形成光刻胶材料(未示出)。随后，辐照(暴露)和显影光刻胶材料以去除光刻胶材料的一部分。随后，例如，使用合适的蚀刻工艺去除钝化层119的暴露部分以形成开口121。在钝化层119是由氧化硅形成的一些实施例中，例如，使用缓冲的氢氟酸(HF)蚀刻钝化层119。在钝化层119是由氮化硅形成的一些实施例中，例如，使用热磷酸(H3PO4)蚀刻钝化层119。随后，例如，可使用灰化工艺和随后的湿清洗工艺去除光刻胶材料。
还参考图1A和图1B，在第二IC管芯109是MEMS管芯的一些实施例中，第二IC管芯109的每个都包括接合至盖(cap)125并且环绕一个或多个腔体127的MEMS衬底123。在一些实施例中，MEMS衬底123和盖125接合，以使盖125的前侧125A面向MEMS衬底123的前侧123A。可以使用诸如熔融接合(如，氧化物与氧化物接合、金属与金属接合、混合接合等)、阳极接合、共晶接合等或它们的组合的任何合适的技术将MEMS衬底123接合至盖125。在一些实施例中，作为可以在低压环境中执行的接合工艺，一个或多个腔体127可以具有低压(高真空)。在其他的实施例中，一个或多个腔体127可以具有取决于第二IC管芯109的设计需求的任何合适的压力。
在一些实施例中，可使用与衬底111类似的材料和方法形成MEMS衬底123，并且本文不再赘述。在一些实施例中，第二IC管芯109中的每个都还包括在MEMS衬底123的前侧123A上位于一个或多个腔体127中的各个MEMS器件129。各个MEMS器件129可以包括膜、谐振器、悬臂式元件、压力传感器、加速计、运动传感器、陀螺仪等，并且可以使用合适的MEMS技术来形成。在一些实施例中，盖125可以是CMOS管芯且可以使用与第一IC管芯107类似的材料和方法形成。在其它实施例中，盖125可以是无源盖且在其中可以不具有电路。在这样的实施例中，盖125可以由陶瓷材料、石英、玻璃等形成。盖125还可包括从盖125的前侧125A延伸至盖125的背侧125B的贯通孔(TV)131。TV 131配置为提供各个MEMS器件129和第二IC管芯109外部的电路之间的电连接。在示出的实施例中，盖125还包括沿着TV 131的侧壁的衬垫层133、盖125的背侧125B上的钝化层135以及在钝化层135上方且接触TV 131的接触焊盘137。在一些实施例中，衬垫层133可包括合适的介电材料且配置为使TV 131与盖125的材料电隔离。在一些实施例中，TV 131和接触焊盘137可以包括诸如铝、铜、钨、银、金、镍等或它们的组合的导电材料。在示出的实施例中，TV 131和接触焊盘137由铜形成。在一些实施例中，钝化层135可包括氮化硅、氧化硅、氮氧化硅、PSG、BSG、BPSG等的一层或多层。以下参考图12至图15描述TV 131和接触焊盘137的制造期间的各个处理步骤。
还参考图1A和图1B，第一IC管芯107和第二IC管芯109具有不同的接触焊盘结构。在示出的实施例中，第一IC焊盘107的接触焊盘结构包括嵌入在钝化层119中的接触焊盘117，并且第二IC焊盘109的接触焊盘结构包括位于钝化层135上方且与TV 131电接触的接触焊盘137。如下面更详细地描述，将在载体101上方且在第一IC管芯107和第二IC管芯109之间形成包封剂(encapsulant)。随后，将在第一IC管芯107和第二IC管芯109以及包封剂上方形成一个或多个再分布层(RDL)。
图2A、图2B、图3A、图3B、图4A、图4B示出了根据一些实施例的使用模塑工具201在载体101上方且在第一IC管芯107和第二IC管芯109之间形成包封剂207期间的各个处理步骤的顶视图和截面图。为了清楚的展示，从图2A、图3A、图4A中示出的顶视图省略模塑工具201。在示出的实施例中，传递模塑法用于包封第一IC管芯107和第二IC管芯109。在其他实施例中，还可以利用其他合适的模塑工艺。在一些实施例中，包封剂207可包括诸如环氧树脂、树脂、可模制聚合物等的模塑料。可以施加基本上是液体的模塑料，并且然后可以通过诸如在环氧树脂或树脂中的化学反应固化。在其他实施例中，模塑料可为紫外线(UV)或热固化聚合物，该紫外线或热固化聚合物用作能够设置在第一IC管芯107和第二IC管芯109周围以及之间的凝胶或可塑固体。
首先参考图2A和图2B，模塑工具201将释放层205附接至第一IC管芯107和第二IC管芯109。在一些实施例中，释放层205可以由类似于释放层103的材料形成且可以层压在第一IC管芯107和第二IC管芯109的顶面上。在一些实施例中，模塑工具201包括插塞203，该插塞配置为在横向方向上移动以及在释放层205和载体101之间、和第一IC管芯107与第二IC管芯109之间的间隙中转移或注射包封剂207。
图3A和图3B示出了部分地注射在释放层205和载体101之间、以及在第一IC管芯107和第二IC管芯109之间的间隙中的包封剂207。在一些实施例中，插塞203在平行于载体101的主面的方向上注射包封剂207，且包封剂207从载体101的边缘流动至载体101的内部中。
图4A和图4B示出了包封工艺的最后阶段。在一些实施例中，插塞203在释放层205和载体101之间注射更多的包封剂207，直至包封剂207完全地填充第一IC管芯107和第二IC管芯109之间的间隙。随后地，使用UV固化、热固化等固化包封剂207。
参考图5，在完成包封工艺之后，去除释放层205且暴露第一IC管芯107和第二IC管芯109的顶面。通过使用以上参考图2A、图2B、图3A、图3B、图4A、图4B描述的方法形成包封剂207，第一IC管芯107的接触焊盘117和第二IC管芯109的接触焊盘137未被包封剂207覆盖且在去除释放层205之后暴露。由于包封剂207未覆盖第一IC管芯107的接触焊盘117和第二IC管芯109的接触焊盘137，所以可以消除诸如研磨工艺、化学机械抛光(CMP)工艺等的包封剂去除工艺。相应地，接触焊盘117和137的顶面可以不与包封剂207的顶面207A共面。此外，通过使用以上参考图2A、图2B、图3A、图3B、图4A、图4B描述的方法形成包封剂207，具有不同接触焊盘结构的集成电路管芯(诸如第一IC管芯107和第二IC管芯109)可以被包封而在包封工艺期间不损坏接触焊盘结构。
参考图6，一个或多个再分布层(RDL)601形成在第一IC管芯107、第二IC管芯109和包封剂207上方并且电耦合至第一IC管芯107的接触焊盘117和第二IC管芯109的接触焊盘137。在一些实施例中，RDL 601包括一个或多个介电层603和设置在一个或多个介电层603内的一个或多个导电部件605(诸如导线、迹线和通孔)。在一些实施例中，一个或多个介电层603可以包括介电材料，诸如PBO、PI、BCB等，并且可以使用旋涂工艺等来形成。在一些实施例中，一个或多个导电部件605可以包括铜、钨、铝、银、金等或它们的组合，并且可以使用电化学镀工艺、无电镀工艺、ALD、PVD等或它们的组合来形成。
还参考图6，凸块下金属(UBM)607形成在一个或多个RDL 601上方并与之电耦合。在一些实施例中，UBM 607可以包括三层导电材料，诸如钛层、铜层和镍层。然而，本领域技术人员将认识到，存在适于形成UBM607的材料和层的许多适当的布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可用于UBM 607的任何合适的材料或材料层全部意欲包括在当前应用的范围内。
参考图7，连接件701形成在UBM 607上方并且与之电耦合。在一些实施例中，连接件701可以是焊球、金属柱、可控坍塌芯片连接(C4)凸块、球栅阵列(BGA)球、微凸块、无电镀镍-无电镀钯浸金技术(ENEPIG)形成的凸块等。连接件701可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在连接件701是焊料凸块的一些实施例中，通过最初由诸如蒸发、电镀、印刷、焊料转移、植球等常用的方法形成焊料层来形成连接件701。一旦在结构上形成焊料层，就可以执行回流，以将材料成形为期望的凸块形状。在其他的实施例中，连接件701可以是通过溅射、印刷、电化学镀、无电镀、PVD等形成的金属柱(例如，诸如铜柱)。金属柱可以不含焊料并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括焊料、镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或它们组合并且可以通过镀敷工艺等来形成。
还参考图7，从包封的第一IC管芯107和第二IC管芯109去除载体101，并且切割包封的第一IC管芯107和第二IC管芯109以形成单独的集成电路封装件703。在释放层103由LTHC材料形成的一些实施例中，释放层103暴露于光。暴露于光造成释放层103失去粘合强度且载体101很容易与第一IC管芯107、第二IC管芯109和包封剂207分离。随后，粘合层105可被去除以暴露第一IC管芯107、第二IC管芯109和包封剂207。在一些实施例中，例如，可使用蚀刻、锯切、激光烧蚀等或它们组合切割包封的第一IC管芯107和第二IC管芯109。随后，为了进一步处理，可以测试每个IC封装件703以识别已知良好封装件(KGP)。
图8A和图8B是根据一些实施例的附接至印刷电路板(PCB)801的堆叠的IC封装件800的顶视图和截面图，其中，图8A表示顶视图且图8B表示沿图8A的B-B'线的截面图。为了清楚地展示，从图8A中示出的顶视图省略PCB 801和连接件701。在一些实施例中，PCB 801具有开口以使堆叠的IC封装件800至少部分地延伸穿过开口。在一些实施例中，堆叠的IC封装件800包括使用连接件701接合至IC封装件703的IC管芯807、809和811，以使在IC封装件703的周边部分上形成的连接件701用于将堆叠的IC封装件800接合至PCB 801。IC管芯807、809和811延伸穿过PCB 801中的开口且允许使用在IC封装件703的周边部分上形成的连接件701以用于将堆叠的IC封装件800接合至PCB 801。在一些实施例中，除了第一IC管芯107和第二IC管芯109，IC封装件703还包括IC管芯803和805。在一些实施例中，IC管芯803、805、807、809和811可以是CMOS管芯、MEMS管芯等。IC管芯803、805、807、809和811可具有各种功能且可以是存储器管芯、MCU芯片、PMIC芯片、RF芯片、ASIC芯片、LCD、LED显示器、触摸传感器、运动传感器、心率传感器、诸如温度传感器、压力传感器、湿度传感器、颗粒传感器的环境传感器等。在示出的实施例中，第一IC管芯107是MCU芯片、第二IC管芯109是运动传感器芯片、IC管芯803是RF芯片、IC管芯805是PMIC芯片、IC管芯807是温度传感器、IC管芯809是心率传感器、以及IC管芯809是MEMS芯片。在一些实施例中，堆叠的IC封装件800可以是诸如腕表、健康监测器件等的可穿戴器件的一部分。
图9A和图9B是根据一些实施例的附接至PCB 801的堆叠的IC封装件900的顶视图和截面图，其中，图9A表示顶视图且图9B表示沿图9A的B-B'线的截面图。为了清楚地展示，从图9A中示出的顶视图省略PCB 801和连接件701。在一些实施例中，堆叠的IC封装件900包括使用连接件701接合至IC封装件901的IC管芯807、809和811，并且可使用类似于堆叠IC封装件800的方法形成。在一些实施例中，可使用与上述参考图1A、图1B、图2A、图2B、图3A、图3B、图4A、图4B、以及图5至图7描述的类似于IC封装件703的方法形成IC封装件901，并且此处不重复描述。替代第二IC管芯109，IC封装件901包括IC管芯903。在一些实施例中，IC管芯903与第二IC管芯109的不同之处在于接触焊盘结构。与第二IC管芯109相反，IC管芯903不包括接触焊盘137，且TV 131直接耦合至一个或多个RDL 601。在一些实施例中，堆叠的IC封装件900可以是诸如腕表、健康监测器件等的可穿戴器件的一部分。
图10A和图10B是根据一些实施例的附接至PCB 801的堆叠的IC封装件1000的顶视图和截面图，其中，图10A表示顶视图且图10B表示沿图10A的B-B'线的截面图。为了清楚地展示，从图10A中示出的顶视图省略PCB 801和连接件701。在一些实施例中，堆叠的IC封装件1000包括使用连接件701接合至IC封装件1001的IC管芯807、809和811，并且可使用类似于堆叠IC封装件800的方法形成。在一些实施例中，可使用与上述参考图1A、图1B、图2A、图2B、图3A、图3B、图4A、图4B、以及图5至图7描述的类似于IC封装件703的方法形成IC封装件1001，并且此处不重复描述。替代第二IC管芯109，IC封装件1001包括IC管芯1003。在示出的实施例中，IC管芯1003是环境传感器。在这样的实施例中，开口1005形成在包封剂207中以将IC管芯1003暴露于外部环境。在一些实施例中，使用合适的光刻和蚀刻方法形成开口1005。在一些实施例中，堆叠的IC封装件1000可以是诸如腕表、健康监测器件等的可穿戴器件的一部分。
图11A和图11B是根据一些实施例的附接至PCB 801的堆叠的IC封装件1100的顶视图和截面图，其中，图11A表示顶视图且图11B表示沿图11A的B-B'线的截面图。为了清楚地展示，从图11A中示出的顶视图省略PCB 801和连接件701。在一些实施例中，堆叠的IC封装件1100包括使用连接件701接合至IC封装件1101的IC管芯1111、1113和1115，并且可使用类似于堆叠的IC封装件800的方法形成。在一些实施例中，IC封装件1101包括IC管芯1103、1105、1107和1109，并且可使用与上述参考图1A、图1B、图2A、图2B、图3A、图3B、图4A、图4B、以及图5至图7描述的类似于IC封装件703的方法形成，以及此处不重复描述。在一些实施例中，IC管芯1103、1105、1107、1109、1111、1113和1115可以是CMOS管芯、MEMS管芯等。IC管芯1103、1105、1107、1109、1111、1113和1115可具有各种功能且可以是存储器管芯、MCU芯片、PMIC芯片、RF芯片、ASIC芯片、LCD、LED显示器、触摸传感器、运动传感器、心率传感器、诸如温度传感器、压力传感器、湿度传感器、和颗粒传感器的环境传感器等。在示出的实施例中，IC管芯1103是PMIC芯片、IC管芯1105是MCU芯片、IC管芯1107是PMIC芯片、IC管芯1109是RF芯片、IC管芯1111是心率传感器、IC管芯1113是诸如运动传感器的MEMS芯片、以及IC管芯1115是温度传感器。在一些实施例中，在IC封装件1101上方、以及在IC管芯1111、1113和1115上方和周围形成包封剂1117。在一些实施例中，可使用与包封剂207类似的材料和方法形成包封剂1117，并且本文不再赘述。在一些实施例中，使用CMP工艺、研磨工艺等或其组合平坦化包封剂1117。在一些实施例中，执行平坦化工艺直至暴露IC管芯1111的顶面。在一些实施例中，可以使用模具(mold chase tool)(未示出)，同时形成包封剂1117以暴露沿着IC封装件1101的周边部分形成的UBM 607和连接件701。在一些实施例中，堆叠的IC封装件1100可以是诸如腕表、健康监测器件等的可穿戴器件的一部分。
图12至图15是根据一些实施例的第二IC管芯109的TV 131和接触焊盘137的制造期间的各个处理步骤的截面图。首先参考图12，示出了包括第二IC管芯109的晶圆1200的一部分，其中，相邻的第二IC管芯109通过划线1201分离。如下面更详细地描述，晶圆1200随后沿着划线1201被分割成单独的第二IC管芯109。在一些实施例中，在盖125接合至MEMS衬底123之前，盖125被图案化以在盖125的前侧125A上形成开口。图12示出了每个第二IC管芯109具有两个开口以作为实例。然而，本领域的技术人员应该理解，根据第二IC管芯109的设计规格，开口的数量可以两个以上且可以变化。在一些实施例中，可使用光刻技术图案化盖125。通常，光刻技术涉及沉积光刻胶材料，随后，对该光刻胶材料进行辐射(暴露)以及显影，以去除部分光刻胶材料。剩余的光刻胶材料保护诸如盖125的下面的材料免受诸如蚀刻的后续处理步骤的影响。可将诸如反应离子蚀刻(RIE)的各向异性干蚀刻、各向同性或各向异性湿蚀刻的合适的蚀刻工艺、或任何其他合适的蚀刻或图案化工艺应用于去除盖125的暴露部分。
还参考图12，衬垫层133共形地形成在盖125的前侧125A上方和开口中。在一些实施例中，衬垫层133可包括合适的介电材料并且可以使用CVD、PECVD、次大气压CVD(SACVD)、ALD等或它们的组合形成。衬垫层133配置为使随后形成的TV 131与盖125的材料电隔离。在一些实施例中，衬垫层133上方共形地形成阻挡/粘合层(未示出)。阻挡/粘合层可以使用溅射、PVD、CVD、ALD等或它们的组合来形成。阻挡/粘合层配置为用作扩散阻挡且保护盖125免受金属扩散的影响。通过用诸如铝、铜、钨、银、金等或它们的组合的导电材料填充开口来形成TV 131。在一些实施例中，使用电化学镀工艺、无电镀工艺、ALD、PVD等、或它们的组合沉积导电材料。在一些实施例中，在用导电材料填充开口之前，在阻挡/粘合层上方共形地形成晶种层(未示出)，以及在晶种层上方沉积导电材料。晶种层可以包括铜、钛、镍、金、锰等或它们的组合，并且可以通过ALD、PVD、溅射等或它们的组合来形成。在一些实施例中，盖125的前侧125A上的开口过填充有导电材料，可以使用蚀刻工艺、CMP工艺等去除导电材料。在盖125中形成TV 131之后，盖125和MEMS衬底123接合以形成具有第二IC管芯109的晶圆1200。可以使用诸如熔融接合(如，氧化物与氧化物接合、金属与金属接合、混合接合等)、阳极接合、共晶接合等或它们的组合的任何合适的技术将MEMS衬底123接合至盖125。
参考图13，减薄盖125的背侧125B直至暴露TV 131。在一些实施例中，可以使用研磨工艺、蚀刻工艺、CMP工艺等减薄盖125的背侧125B。如下面参考图14和图15更详细地描述，在一些实施例中，工艺持续形成位于盖125的背侧125B上方且与TV 121电接触的接触焊盘137。在其它实施例中，工艺在此停止且在形成接触焊盘137之前可沿着划线1201分割晶圆1200。在这样的实施例中，可以形成诸如图9A和图9B中示出的IC管芯903的单独管芯。
参考图14，在盖125的背侧125B上和TV 131上方形成钝化层135。在一些实施例中，钝化层135可以包括氮化硅、氧化硅、氮氧化硅、PSG、BSG、BPSG等的一层或多层，并且可以使用CVD、PVD、ALD、旋涂工艺等或它们的组合来形成。在一些实施例中，平坦化钝化层135直至暴露TV 131。在一些实施例中，可以使用研磨工艺、蚀刻工艺、CMP工艺等平坦化钝化层135。随后，开槽钝化层135以暴露TV 131的侧壁的至少一部分且形成在钝化层135的顶面之上延伸的通孔突起。在一些实施例中，可使用选择性蚀刻工艺等开槽钝化层135。
参考图15，形成位于钝化层135上方且与TV 131电接触的接触焊盘137。在一些实施例中，牺牲层(未示出)可以形成在钝化层135上方且可被图案化以在牺牲层中形成开口。在一些实施例中，牺牲层可包括光刻胶材料等。牺牲层中的开口暴露TV 131的通孔突起。在一些实施例中，诸如铝、铜、钨、银、金、镍等或它们的组合的导电材料沉积在牺牲层中的开口中以形成接触焊盘137。在其它实施例中，可在钝化层上方形成导电材料并且随后被图案化以形成接触焊盘。在完成接触焊盘137的形成之后，晶圆1200被切割以形成单独的第二IC管芯109。在一些实施例中，例如，可使用蚀刻、锯切、激光烧蚀等或其组合切割晶圆。随后，为了进一步处理，可以测试每个第二IC封装件109以识别已知良好封装件(KGP)。
图16是示出根据一些实施例的形成集成电路封装件的方法1600的流程图。方法开始于步骤1601，其中，如上述参考图1A和图1B描述的，第一管芯(诸如第一IC管芯107)和第二管芯(诸如第二IC管芯109)附接至载体(诸如载体101)。在步骤1603中，如以上参考图2A和图2B所述，在第一管芯和第二管芯的顶面上方形成释放层(诸如释放层205)。在步骤1605中，如以上参考图3A、图3B、图4A和图4B所述，在释放层和载体之间、以及在相邻的管芯之间注射包封剂(诸如包封剂207)。在步骤1607中，如以上参考图6所述，在第一管芯、第二管芯和包封剂上方形成一个或多个再分布层(诸如一个或多个RDL 601)。在步骤1609中，如上述参考图7描述，在一个或多个RDL上方形成连接件(诸如连接件701)。在步骤1611中，如以上关于图7所述，所得到的结构从载体分离并且被切割以形成单独的封装件(诸如IC封装件703)。在步骤1613中，如以上关于图8所述，一个或多个管芯(诸如IC管芯807、809和811)使用连接件附接至单独的封装件。在一些可选实施例中，可以在步骤1611之前执行步骤1613。
本文中呈现的各个实施例可提供若干益处。诸如本文描述的实施例允许将具有不同接触焊盘结构的集成电路管芯封装至同一集成电路封装件中。此外，诸如本文描述的实施例在集成电路封装件的形成期间允许消除特定的工艺步骤且允许降低制造成本。此外，本文描述的实施例允许具有不同接触焊盘结构的集成电路管芯的包封而在包封工艺期间不损坏接触件焊盘结构。
根据实施例，一种方法包括将第一管芯和第二管芯附接至载体，第一管芯具有第一接触焊盘，第二管芯具有第二接触焊盘，第一接触焊盘和第二接触焊盘具有不同的结构。释放层形成在第一管芯和第二管芯上方。在载体和释放层之间注射包封剂。在第一管芯、第二管芯和包封剂上方形成一个或多个再分布层(RDL)，第一接触焊盘和第二接触焊盘与一个或多个RDL电接触。
根据另一实施例，一种方法包括将第一管芯的第一侧附接至载体。第一管芯包括位于第一管芯的第二侧上的第一接触焊盘，第一管芯的第二侧与第一管芯的第一侧相对。第一管芯还包括位于第一管芯的第二侧上的第一绝缘层，通过第一绝缘层中的开口暴露第一接触焊盘的至少一部分。第二管芯的第一侧附接至载体。第二管芯包括贯通孔，贯通孔从第二管芯的第一侧延伸至第二管芯的第二侧，第二管芯的第二侧与第二管芯的第一侧相对。第二管芯还包括位于第二管芯的第二侧上的第二绝缘层、贯通孔的延伸穿过第二绝缘层的至少一部分、以及位于第二绝缘层上方的第二接触焊盘，第二接触焊盘接触贯通孔。释放层层压在第一接触焊盘、第二接触焊盘、第一绝缘层和第二绝缘层的顶面上方。在载体和释放层之间、以及在第一管芯和第二管芯之间的间隙中注射第一包封剂。在第一管芯、第二管芯和第一包封剂上方形成一个或多个再分布层(RDL)，第一接触焊盘和第二接触焊盘与一个或多个RDL电接触。
根据又一实施例，一种器件包括一个或多个再分布层(RDL)、以及位于一个或多个RDL的第一侧上的第一管芯，第一管芯包括嵌入在第一绝缘层中的第一接触焊盘，一个或多个RDL的导电部件延伸穿过第一绝缘层并且接触第一接触焊盘。器件还包括位于一个或多个RDL的第一侧上的第二管芯。第二管芯包括延伸穿过第二绝缘层的贯通孔和位于第二绝缘层上方的第二接触焊盘，第二接触焊盘接触贯通孔，一个或多个RDL的第三绝缘层的至少一部分沿着第二接触焊盘的侧壁延伸。器件还包括位于一个或多个RDL的第一侧上的第一包封剂，第一包封剂的至少一部分插在第一管芯和第二管芯之间。
本发明的实施例提供了一种形成集成电路封装件的方法，包括：将第一管芯和第二管芯附接至载体，所述第一管芯具有第一接触焊盘，所述第二管芯具有第二接触焊盘，所述第一接触焊盘和所述第二接触焊盘具有不同的结构；在所述第一管芯和所述第二管芯上方形成释放层；在所述载体和所述释放层之间注射包封剂；以及在所述第一管芯、所述第二管芯和所述包封剂上方形成一个或多个再分布层(RDL)，所述第一接触焊盘和所述第二接触焊盘与所述一个或多个再分布层电接触。
根据本发明的一个实施例，方法还包括将第三管芯附接至所述一个或多个再分布层，所述第一或多个再分布层插在所述包封剂和所述第三管芯之间。
根据本发明的一个实施例，其中，所述包封剂的最顶部表面位于所述第一管芯的最顶部表面下方。
根据本发明的一个实施例，其中，所述包封剂的最顶部表面位于所述第二接触焊盘的最顶部表面下方。
根据本发明的一个实施例，其中，所述第一接触焊盘嵌在第一介电层中。
根据本发明的一个实施例，其中，所述第二接触焊盘在第二介电层上方延伸，所述第二接触焊盘与所述第二管芯中的贯通孔电接触。
根据本发明的一个实施例，其中，所述第一管芯为CMOS管芯，并且其中，所述第二管芯为MEMS管芯。
本发明的实施例还提供了一种形成集成电路封装件的方法，包括：将第一管芯的第一侧附接至载体，所述第一管芯具有：位于所述第一管芯的第二侧上的第一接触焊盘，所述第一管芯的所述第二侧与所述第一管芯的所述第一侧相对；和位于所述第一管芯的所述第二侧上的第一绝缘层，通过所述第一绝缘层中的开口暴露所述第一接触焊盘的至少一部分；将第二管芯的第一侧附接至所述载体，所述第二管芯具有：贯通孔，所述贯通孔从所述第二管芯的所述第一侧延伸至所述第二管芯的第二侧，所述第二管芯的所述第二侧与所述第二管芯的所述第一侧相对；位于所述第二管芯的所述第二侧上的第二绝缘层，所述贯通孔的至少一部分延伸穿过所述第二绝缘层；和位于所述第二绝缘层上方的第二接触焊盘，所述第二接触焊盘接触所述贯通孔；将释放层层压在所述第一接触焊盘、所述第二接触焊盘、所述第一绝缘层和所述第二绝缘层的顶面上方；在所述载体和所述释放层之间、以及在所述第一管芯和所述第二管芯之间的间隙中注射第一包封剂；以及在所述第一管芯、所述第二管芯和所述第一包封剂上方形成一个或多个再分布层(RDL)，所述第一接触焊盘和所述第二接触焊盘与所述一个或多个再分布层电接触。
根据本发明的一个实施例，方法还包括：将一个或多个管芯附接至所述一个或多个再分布层，所述一个或多个再分布层插在所述一个或多个管芯与所述第一包封剂之间；以及将所述一个或多个再分布层附接至电路板，所述电路板具有开口，所述一个或多个管芯延伸穿过所述开口。
根据本发明的一个实施例，方法还包括将第三管芯附接至所述一个或多个再分布层，所述第一或多个再分布层插在所述第一管芯和所述第三管芯之间。
根据本发明的一个实施例，方法还包括在所述一个或多个再分布层上方形成第二包封剂，所述第二包封剂的至少一部分沿着所述第三管芯的侧壁延伸。
根据本发明的一个实施例，其中，注射所述第一包封剂包括使用插塞迫使所述第一包封剂进入所述第一管芯和所述第二管芯之间的间隙中。
根据本发明的一个实施例，其中，所述第一接触焊盘的最顶部表面与所述第一包封剂的最顶部表面不共面。
根据本发明的一个实施例，其中，所述第二接触焊盘的最顶部表面与所述第一包封剂的最顶部表面不共面。
本发明的实施例还提供了一种集成电路封装器件，包括：一个或多个再分布层(RDL)；第一管芯，位于所述一个或多个再分布层的第一侧上，所述第一管芯包括嵌在第一绝缘层中的第一接触焊盘，所述一个或多个再分布层的导电部件延伸穿过所述第一绝缘层并且接触所述第一接触焊盘；第二管芯，位于所述一个或多个再分布层的所述第一侧上，所述第二管芯包括：贯通孔，延伸穿过第二绝缘层；和第二接触焊盘，位于所述第二绝缘层上方，所述第二接触焊盘接触所述贯通孔，所述一个或多个再分布层的第三绝缘层的至少一部分沿着所述第二接触焊盘的侧壁延伸；以及第一包封剂，位于所述一个或多个再分布层的所述第一侧上，所述第一包封剂的至少一部分插在所述第一管芯和所述第二管芯之间。
根据本发明的一个实施例，器件还包括：第三管芯，位于所述一个或多个再分布层的第二侧上，所述一个或多个再分布层的所述第二侧与所述一个或多个再分布层的所述第一侧相对；第二包封剂，位于所述一个或多个再分布层的所述第二侧上，所述第三管芯延伸穿过所述第二包封剂；以及电路板，位于所述一个或多个再分布层的第二侧上，所述第二包封剂延伸穿过所述电路板中的开口。
根据本发明的一个实施例，其中，所述第二包封剂的至少一部分插在所述第三管芯和所述一个或多个再分布层之间。
根据本发明的一个实施例，其中，所述第一包封剂的最顶部表面位于所述第一绝缘层的最顶部表面下方。
根据本发明的一个实施例，其中，所述第一包封剂的所述最顶部表面位于所述第二接触焊盘的最顶部表面下方。
根据本发明的一个实施例，其中，所述第一管芯为CMOS管芯，并且其中，所述第二管芯为MEMS管芯。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的实施例。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (1)

1.一种形成集成电路封装件的方法，包括：
将第一管芯和第二管芯附接至载体，所述第一管芯具有第一接触焊盘，所述第二管芯具有第二接触焊盘，所述第一接触焊盘和所述第二接触焊盘具有不同的结构；
在所述第一管芯和所述第二管芯上方形成释放层；
在所述载体和所述释放层之间注射包封剂；以及
在所述第一管芯、所述第二管芯和所述包封剂上方形成一个或多个再分布层(RDL)，所述第一接触焊盘和所述第二接触焊盘与所述一个或多个再分布层电接触。
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