CN105374693A - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN105374693A
CN105374693A CN201410808031.XA CN201410808031A CN105374693A CN 105374693 A CN105374693 A CN 105374693A CN 201410808031 A CN201410808031 A CN 201410808031A CN 105374693 A CN105374693 A CN 105374693A
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China
Prior art keywords
packaging part
bottom filler
electrical connector
tube core
layer
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CN201410808031.XA
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CN105374693B (zh
Inventor
余振华
林俊成
蔡柏豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例包括半导体封装件及其形成方法。一个实施例为一种方法，包括：形成第一管芯封装件，第一管芯封装件包括第一管芯、第一电连接件和第一再分布层，第一再分布层连接至第一管芯和第一电连接件；在第一管芯封装件上方形成底部填充物；图案化底部填充物以具有露出第一电连接件的一部分的开口；以及利用接合结构将第二管芯封装件接合至第一管芯封装件，接合结构连接至底部填充物的开口中的第一电连接件。

Description

半导体封装件及其形成方法
技术领域
本发明总体涉及半导体领域，更具体地，涉及半导体封装件及其形成方法。
背景技术
半导体器件用于各种电子应用，诸如个人计算机、手机、数码相机和其他电子设备。半导体器件通常通过在半导体衬底上方顺序沉积绝缘或介电层、导电层和半导体材料层并且使用光刻图案化各个材料层以在其上形成电路部件和元件来制造。
半导体工业由于各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的改进而经历了快速发展。很大程度上，这种集成密度的改进源于半导体工艺节点的缩小(例如，朝向亚20nm节点的工艺节点的缩小)。随着近年来对小型化、更高速度和更大宽度、以及更低功耗和更小延迟的需求的增长，对于更小且更具创造性的半导体管芯的封装技术的需求也正在增长。
发明内容
根据本发明的一个方面，提供了一种方法，包括：形成第一封装件；利用接合结构将第二封装件接合至第一封装件，接合结构连接至第一电连接件；以及在第一封装件和第二封装件之间形成底部填充物。其中，形成第一封装件包括：在载体衬底上方形成第一介电层；在第一介电层上方形成第一电连接件；将第一管芯附接为与第一电连接件相邻且位于第一介电层上方；在第一管芯和第一电连接件上方形成再分布层；在再分布层上方形成第二电连接件，第二电连接件连接至第一管芯和第一电连接件中的至少一个；去除载体衬底以露出第一介电层；和去除第一介电层以露出第一管芯和第一电连接件的一部分。
优选地，在第一封装件和第二封装件之间形成底部填充物包括：在利用接合结构将第一封装件接合至第一封装件之后，在第一封装件和第二封装件之间注入底部填充物，底部填充物环绕接合结构。
优选地，在第一封装件和第二封装件之间注入底部填充物之后，第一管芯的一部分透过底部填充物露出。
优选地，在第一封装件和第二封装件之间形成底部填充物包括：在利用接合结构将第一封装件接合至第二封装件之前，在第一封装件上方形成底部填充物；和图案化底部填充物，以至少露出第一电连接件的一部分。
优选地，图案化底部填充物还包括：图案化底部填充物以露出第一管芯的一部分。
优选地，在第一封装件和第二封装件之间形成底部填充物包括：形成液体环氧树脂、可变形凝胶、硅橡胶、非导电膜、聚合物、聚苯并唑、聚酰亚胺、阻焊剂或它们的组合。
优选地，去除第一介电层还包括：蚀刻第一介电层以露出第一管芯和第一电连接件的一部分。
优选地，去除第一介电层还包括：研磨第一介电层以露出第一管芯和第一电连接件的一部分。
优选地，形成第一封装件还包括：利用模制材料来封装第一管芯和第一电连接件，第一电连接件延伸穿过模制材料，第二电连接件为金属凸块。
根据本发明的另一方面，提供了一种方法，包括：形成第一管芯封装件，第一管芯封装件包括第一管芯、第一电连接件和第一再分布层，第一再分布层连接至第一管芯和第一电连接件；在第一管芯封装件上方形成底部填充物；图案化底部填充物以具有露出第一电连接件的一部分的开口；以及利用接合结构将第二管芯封装件接合至第一管芯封装件，接合结构连接至底部填充物的开口中的第一电连接件。
优选地，该方法还包括：将第一管芯封装件和第二管芯封装件与相邻的管芯封装件分割开以形成半导体封装件，半导体封装件包括第一管芯封装件和第二管芯封装件。
优选地，形成第一管芯封装件还包括：在第一载体衬底上方形成第一介电层；在第一介电层上方形成第一电连接件，第一电连接件从第一介电层的第一侧处延伸；将第一管芯附接至第一介电层的第一侧；利用模制材料来封装第一管芯和第一电连接件，第一电连接件延伸穿过模制材料；在第一管芯、第一电连接件和模制材料上方形成第一再分布层；去除第一载体衬底以露出第一介电层的第二侧，第二侧与第一侧相对；以及去除第一介电层以露出第一管芯的背面和第一电连接件的背面，底部填充物形成在第一管芯的露出的背面上方和第一电连接件的露出的背面上方。
优选地，第一管芯的背面还包括管芯附接膜。
优选地，经过图案化的底部填充物具有基本垂直于第一管芯的背面的侧壁。
优选地，在第一管芯封装件上方形成底部填充物包括：形成液体环氧树脂、可变形凝胶、硅橡胶、非导电膜、聚合物、聚苯并唑、聚酰亚胺、阻焊剂或它们的组合。
优选地，该方法还包括：图案化底部填充物以形成位于第一管芯上方且与第一管芯对准的开口，开口的宽度小于第一管芯的宽度。
根据本发明的又一方面，提供了一种半导体封装件，包括第一封装件、第二封装件以及底部填充物。第一封装件包括：第一管芯；封装物，环绕第一管芯；和封装通孔，延伸穿过封装物。第二封装件，包括第二管芯，第二封装件通过一组连接件接合至第一封装件；以及底部填充物，位于第一封装件和第二封装件之间并且环绕一组连接件，底部填充物具有基本垂直于第一管芯的背面的侧壁。
优选地，底部填充物包括液体环氧树脂、可变形凝胶、硅橡胶、非导电膜、聚合物、聚苯并唑、聚酰亚胺、阻焊剂或它们的组合。
优选地，底部填充物具有位于第一管芯上方的第一开口，第一开口的宽度小于第一管芯的宽度。
优选地，第一封装件具有第一宽度且第二封装件具有第二宽度，第二宽度小于第一宽度。
附图说明
当阅读附图时，根据以下详细的描述来理解本发明的各个方面。注意，根据行业的标准实践，各个部件没有按比例绘制。事实上，为了讨论的清楚，各个部件的尺寸可以任意增加或减小。
图1A至图1J示出了根据一些实施例的形成第一封装件的中间步骤的截面图。
图2A至图2C示出了根据一些实施例的将第二封装件附接至图1A至图1J所示的第一封装件并将封装件分割成半导体封装件的中间步骤的截面图。
图3A至图3C示出了根据一些实施例的半导体封装件的截面图。
图4A和图4B示出了根据一些其他实施例的形成半导体封装件的中间步骤的截面图。
图5A至图5C示出了根据一些其他实施例的半导体封装件的截面图。
图6、图7A和图7B示出了根据一些其他实施例的形成半导体封装件的中间步骤的截面图。
图8示出了根据一些实施例的半导体封装件的截面图。
具体实施方式
以下公开提供了许多不同的用于实施本发明主题的不同特征的实施例或实例。以下描述部件或配置的具体实例以简化本发明。当然，这些仅仅是实例而不用于限制。例如，在以下的描述中，在第二部件上方或之上形成第一部件可以包括第一部件和第二部件被形成为直接接触的实施例，并且也可以包括可以在第一部件和第二部件形成附件部件使得第一部件和第二部分没有直接接触的实施例。此外，本发明可以在各个实例中重复参考标号和/或字母。这些重复是为了简化和清楚，其本身并不表示所讨论的各个实施例和/或结构之间的关系。
此外，为了易于描述，可以使用空间相对术语(诸如“在…下方”、“之下”、“下部”、“上方”、“上部”等)以描述图中所示一个元件或部件与另一个元件或部件的关系。除图中所示的定向之外，空间相对术语还包括使用或操作中设备的不同定向。装置可以以其他方式定向(旋转90度或处于其他定向)，本文所使用的空间相对描述可因此进行类似的解释。
将参照特定的条件下的实施例(即，三维(3D)集成扇出(InFO)堆叠封装(PoP)器件)来描述实施例。然而，还可以将其他实施例应用于其他电连接的部件，包括但不限于堆叠封装组件、管芯-管芯组件、晶圆-晶圆组件、管芯-衬底组件、装配中的组件、处理中的衬底、中介片、衬底等，或者安装输入部件、板、管芯或其他部件，或者用于连接的任何类型的集成电路或电部件的封装或安装组合。
图1A至图1J示出了根据一些实施例的形成两个第一半导体封装件100的中间步骤的截面图。图1A中的第一半导体封装件包括载体衬底102上方的粘合层104、粘合层104上方的介电层106以及介电层106上方的晶种层108。载体衬底102可以为任何适当的衬底，其(在制造工艺的中间操作期间)为载体衬底102上方的各层提供机械支撑。载体衬底102可以为包括玻璃、硅(例如，硅晶圆)、氧化硅、金属板、陶瓷材料等的晶圆。
粘合层104可以设置在(例如，层压在)载体衬底102上。粘合层104可以由诸如紫外线(UV)胶的胶、光热转换(LTHC)材料形成，或者可以为薄片形成的层压层。
介电层106形成在粘合层104上方。介电层106可以为氮化硅、碳化硅、氧化硅、低k电介质(诸如，掺碳氧化物)、超低k电介质(诸如，掺多孔碳的二氧化硅)、聚合物(诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并唑(PBO)等)或它们的组合，尽管还可以使用其他相对较软的有机介电材料。介电层106可通过化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、旋涂电介质工艺等或它们的组合来沉积。
晶种层108形成在介电层106上方。晶种层108可由铜、钛、镍、金等或它们的组合来制成。晶种层108可通过PVD、CVD、ALD等或它们的组合来沉积。
图1B示出了图案化晶种层108以及形成电连接件110。晶种层108可通过蚀刻工艺或任何其他适当的图案化工艺来进行图案化。
电连接件110可形成在晶种层108上方并且在基本垂直于介电层106的表面的方向上从晶种层108处延伸出来。在一些实施例中，电连接件110通过电镀形成。在这些实施例中，电连接件110由铜、铝、镍、金、银、铂、锡等或它们的组合制成，并且可具有包括多层的复合结构。在这些实施例中，诸如光刻胶的牺牲层112形成在载体衬底上方。在一些实施例中，在晶种层108上形成并图案化光刻胶112，然后在图案化的光刻胶112中形成电连接件110。光刻胶112可通过诸如旋涂工艺的湿式工艺或诸如施加干膜的干式工艺来形成。在光刻胶112中形成多个开口以露出下面的晶种层108。然后，执行镀步骤以对电连接件110进行镀操作。
在可选实施例中，电连接件110可以为柱状凸块，其通过在介电层106上方进行引线接合并且切割结合引线以使结合引线的一部分附接至对应的接合球而形成。例如，电连接件110可包括下部和上部，其中，下部可以是以引线接合形成的接合球(未示出)，上部可以是剩余的结合引线(未示出)。电连接件110的上部可具有均匀的宽度和均匀的形状，其在整个上部的顶部部分、中间部分和下部部分都是均匀的。电连接件110可由非焊接金属材料形成，其可通过引线接合器进行接合。在一些实施例中，电连接件110由铜线、金线等或它们的组合制成，并且可具有包括多层的复合结构。在引线接合实施例中，可以省略晶种层108和牺牲层112。
电连接件110可形成用于第一封装件的背侧再分布层。该背侧再分布层可用于将另一封装件或部件(参见图2A)连接至第一封装件。
图1C示出了去除牺牲层112。牺牲层112可通过适当的去除工艺(诸如，灰化或蚀刻工艺)来去除。
图1D示出了将管芯120附接至介电层106。管芯120的第一侧可利用粘合层126附接至介电层106。粘合层126可以为任何适当的粘合剂，诸如，管芯附接膜等。管芯120可以为单个管芯或者可以为多于两个的管芯。管芯120可包括诸如中央处理单元(CPU)的逻辑管芯、图形处理单元(GPU)等或它们的组合。在一些实施例中，管芯120包括管芯堆叠件(未示出)。其可包括逻辑管芯和存储管芯。管芯120可包括输入/输出(I/O)管芯(诸如，宽I/O管芯)，其在第一封装件10和随后附接的第二封装件200(参见图2A)之间提供连接。
管芯120包括位于管芯120的第二侧上的接触区域124。在一些实施例中，接触区域124为接合焊盘。接合焊盘124可以形成在管芯120的第二侧上方。在一些实施例中，接合焊盘124通过在管芯120的第二侧上的介电层(未示出)中形成凹槽(未示出)来形成。可形成凹槽以允许接合焊盘124嵌入到介电层中。在其他实施例中，省略凹槽，因为接合焊盘124可形成在介电层上。接合焊盘124将管芯120电和/或物理连接至随后接合的第二封装件200(参见图2A)和/或电连接件110。在一些实施例中，接合焊盘124包括由铜、钛、镍、金、锡等或它们的组合制成的薄晶种层(未示出)。接合焊盘124的导电材料可以沉积在薄晶种层上方。导电材料可通过电化学镀工艺、CVD、ALD、PVD等或它们的组合来形成。在一个实施例中，接合焊盘124的导电材料为铜、钨、铝、银、金、锡等或它们的组合。
在一个实施例中，接触区域124为包括三层导电材料(诸如，钛层、铜层和镍层)的凸块下金属(UBM)。然而，本领域技术人员应该意识到，可以具有许多适合于形成UBM124的适当的材料和层的配置，诸如，铬/铬-铜合金/铜/金的配置、钛/钛钨/铜的配置或者铜/镍/金的配置。可用于UBM124的任何适当的材料或材料层都包括在本申请的范围内。
图1E示出了管芯120和电连接件110的封装。在一些实施例中，管芯120和电连接件110通过模制材料130进行封装。模制材料130可以例如使用压缩模制而模制在管芯和电连接件110上。在一些实施例中，模制材料130由模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合来制作。可以执行固化步骤以固化模制材料130，其中，固化可以为热固化、UV固化等或它们的组合。
在一些实施例中，如图1E所示，管芯120、接触区域124和电连接件110可埋入模制材料130中，并且在固化模制材料130之后，对模制材料130执行诸如研磨的平面化步骤。平面化步骤用于去除模制材料130的过量部分，其中过量部分位于接触区域124和电连接件110的顶面上方。在一些实施例中，接触区域124的表面和电连接件110的表面110A露出，并且与模制材料130的表面130A和管芯120的表面120A平齐。电连接件110可称为模制通孔(TMV)、封装通孔(TPV)和/或InFO通孔(TIV)，并且在下文被称为TIV110。
在其他实施例中，接触区域124是从管芯120的第二侧部分地延伸到管芯120中的通孔，或者在一些实施例中，是完全延伸穿过管芯120的通孔。通孔124可以通过蚀刻工艺在管芯120中形成孔(未示出)而形成并且用诸如铜、铝、镍、金、银、铂、锡等或它们的组合的导电材料来填充孔，并且孔可具有包括多层的复合结构。管芯120还可以包括晶种层、阻挡层、衬层等或它们的组合。
图1F示出了在管芯120、TIV110和模制材料130上方形成再分布层131。再分布层131可包括一个或多个金属层(有时被称为M1和/或MN)，其中，金属层M1是直接与管芯120相邻的金属层，而金属层MN(有时称为顶部金属层MN)是距离管芯120最远的金属层。在整个描述中，术语“金属层”是同一层中的金属线132的集合。再分布层131可包括一个或多个钝化层134，其中，一个或多个金属层(M1至MN)被设置在一个或多个钝化层134中。
钝化层134可以为氮化硅、碳化硅、氧化硅、低k电介质(诸如，掺碳氧化物)、极低k电介质(诸如，掺多孔碳的二氧化硅)、聚合物(诸如，环氧树脂、聚酰亚胺、BCB、PBO)、阻焊剂(SR)等或它们的组合，尽管还可以使用其他相对较软的有机介电材料，并且可以通过CVD、PVD、ALD、旋涂电介质工艺、层压工艺等或它们的组合来沉积。钝化层134可经受固化步骤以固化钝化层134，其中，固化可以为热固化、UV固化等或它们的组合。
金属层132可使用单和/或双镶嵌工艺、先通孔工艺或先金属工艺来形成。金属层132和通孔可由诸如铜、铝、钛等或它们的组合的导电材料形成，可以具有或不具有阻挡层。
镶嵌工艺是指嵌入在另一层内的图案化的层的形成使得两个层的顶面共面。仅形成沟槽或通孔的镶嵌工艺已知为单镶嵌工艺。同时形成沟槽和通孔的镶嵌工艺已知为双镶嵌工艺。
在示例性实施例中，使用双镶嵌工艺形成金属层132。在该实例中，M1层可首先通过在最下部的钝化层134上形成蚀刻停止层(未示出)然后在蚀刻停止层上形成下一钝化层134来形成。一旦沉积了下一钝化层134，就可以蚀刻掉下一钝化层134的各部分以形成凹槽形部件(诸如，沟槽和通孔)，其可以填充导电材料以连接再分布层134的不同区域并且容置金属线132和通孔。对于剩余的金属各层可重复该处理直至MN层。
再分布层131可称为第一封装件100的前侧再分布层。前侧再分布层131可用于通过连接件136将第一封装件100连接至一个或多个封装件、封装衬底、部件等或它们的组合(参见图1G)。
金属层132的个数和钝化层134的个数仅是为了示意的目的而不用于限制。还可以具有大于或小于所示的一个金属层的其他数目的层。还可以具有不同于图1F所示的其他数目的钝化层、其他数目的金属层。
图1G示出了在再分布层131上方形成一组导电连接件136并且将其电连接至再分布层131。导电连接件136可以为焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镍铂浸金技术(ENEPIG)形成的凸块等。导电连接件136可包括导电材料，诸如，焊料、铜、铝、金、镍、银、铂、锡等或它们的组合。在导电连接件136为焊料凸块的实施例中，导电连接件136首先通过常用的方法(诸如，蒸发、电镀、印刷、焊料转移、焊球置放等)形成焊料层来形成。一旦焊料层形成在结构上，就执行回流以使材料成形为期望的凸块形状。在另一实施例中，导电连接件136为通过溅射、印刷、电镀、无电镀、CVD等形成的金属柱(诸如，铜柱)。金属柱可以是无焊料的，并且具有基本垂直的侧壁。在一些实施例中，金属盖层(未示出)形成在金属柱连接件136的顶部上。金属盖层可包括镍、锡、锡-铅、金、银、铂、铟、镍-铂-金、镍-金等或它们的组合，并且可以通过镀工艺来形成。
尽管未示出，但可以存在连接至再分布层的UBM，导电连接件136连接至UBM(未示出)。UBM可通过首先形成一组开口(未示出)来形成，这组开口穿过顶部的钝化层134直至露出金属层MN中的金属线。UBM可延伸穿过钝化层134中的这些开口，并且还沿着钝化层134的表面延伸。UBM可包括三个导电材料层，诸如，钛层、铜层和镍层。然而，本领域技术人员应该意识到，可以存在许多适合于形成UBM的适当的材料和层的配置，诸如，铬/铬-铜合金/铜/金的配置、钛/钛钨/铜的配置或铜/镍/金的配置。任何可用于UBM的适当的材料层都完全包括在本申请的范围内。
图1H示出了根据一个实施例的去除载体衬底102和粘合层104以露出介电层106。在该实施例中，在去除载体衬底102和粘合层104的同时第一封装件被置于框138上，其中导电连接件136与框138邻接。
图1I示出了根据另一实施例的去除载体衬底102和粘合层104以露出介电层106。在该实施例中，在去除载体衬底102和粘合层104的同时第一封装件被置于第二载体衬底140上，其中导电连接件136与第二载体衬底140邻接。该实施例可包括第二载体衬底140上的可剥离胶142，导电连接件136嵌入至可剥离胶142中。可剥离胶142可帮助确保第一封装件100固定至第二载体衬底140。在去除载体衬底102之后，可通过剥离方法(包括热工艺、化学剥离工艺、激光去除、UV处理等或它们的组合)去除可剥离胶142。
图1J示出了介电层106的去除。介电层106可通过适当的去除工艺(诸如，蚀刻工艺)去除。在去除介电层106之后，露出管芯120和TIV110的一部分。TIV110的背面110B被露出，其可以包括晶种层108。此外，管芯120的背面120B被露出，其可以包括粘合层126。在一些实施例中，在去除介电层106之后，TIV110可通过例如蚀刻工艺被开槽。在一些实施例中，去除粘合层126以露出管芯120的表面。在其他实施例中，当将管芯120附接至载体衬底102(参见图1C)时，不使用粘合层126。在一些实施例中，表面130B和120B基本共面且高于表面110B。换句话说，TIV110可凹陷在模制材料130中。
图2A至图2C示出了根据一些实施例的将第二封装件附接至图1A至图1J所示的第一封装件并且将封装件分割为半导体封装件的中间步骤的截面图。参照图2A，利用一组导电连接件210将第二封装件200接合至第一封装件100，形成半导体封装件300。
第二封装件200均包括衬底202以及连接至衬底202的一个或多个堆叠的管芯212(212A和212B)。衬底202可由半导体材料(诸如，硅、锗、金刚石等)制成。可选地，还可以使用化合材料(诸如，硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、它们的组合等)。此外，衬底202可以为绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如，外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。在一个可选实施例中，衬底202是基于诸如玻璃纤维增强树脂核的绝缘核。一个示例性核材料是诸如FR4的玻璃纤维树脂。用于核材料的可选材料包括双马来酰亚胺-三嗪(BT)树脂，或者可选地，包括其他印刷电路板(PCB)材料或膜。诸如味之素层积膜(ABF)的层积膜或其它层压件可用于衬底202。衬底202可称为封装衬底202。
衬底202可包括有源和无源器件(图2A中未示出)。本领域技术人员应该意识到，诸如晶体管、电容器、电阻器、它们的组合等的各种器件可用于满足半导体封装件300的设计的结构和功能要求。可使用任何适当的方法来形成这些器件。
衬底202还可以包括金属化层(未示出)和通孔208。金属化层可形成在有源和无源器件上方，并且被设计为连接各个器件以形成功能电路。金属化层可由介电层(例如低k介电材料)和导电材料(例如，铜)层交替形成，其中通孔将各个导电材料层互连，并且可通过任何适当的工艺(诸如沉积、镶嵌、双镶嵌等)来形成金属化层。在一些实施例中，衬底202基本没有有源和无源器件。
衬底202可在衬底202的第一侧上具有接合焊盘204以连接至堆叠管芯212，以及在衬底202的第二侧上具有接合焊盘206以连接至导电连接件210，其中第二侧与衬底202的第一侧相对。在一些实施例中，接合焊盘204和206通过在衬底202的第一侧和第二侧上的介电层(未示出)中形成凹槽(未示出)来形成。可形成凹槽以允许接合焊盘204和206嵌入到介电层中。在其他实施例中，省略凹槽，因为接合焊盘204和206可形成在介电层上。在一些实施例中，接合焊盘204和206包括由铜、钛、镍、金、铂等或它们的组合制成的薄晶种层(未示出)。接合焊盘204和206的导电材料可沉积在薄晶种层上方。导电材料可通过电化学镀工艺、无电镀工艺、CVD、ALD、PVD等或它们的组合来形成。在一个实施例中，接合焊盘204和206的导电材料为铜、钨、铝、银、金等或它们的组合。
在一个实施例中，接合焊盘204和206为UBM，UBM包括三个导电材料层，诸如，钛层、铜层和镍层。然而，本领域技术人员应该意识到，还可以具有许多适合于形成UBM204和206的适当的材料和层的配置，诸如，铬/铬-铜合金/铜/金的配置、钛/钛钨/铜的配置或者铜/镍/金的配置。可用于UBM204和206的任何适当的材料或材料层都完全包括在本申请的范围内。在一些实施例中，通孔208延伸穿过衬底202，并且将至少一个接合焊盘204连接至接合焊盘206。
在所示实施例中，堆叠管芯212通过接合引线214连接至衬底202，尽管还可以使用诸如导电凸块的其他连接件。在一个实施例中，堆叠管芯212是堆叠的存储管芯。例如，堆叠存储管芯212可包括低功率(LP)双数据速率(DDR)存储模块，诸如，LPDDR1、LPDDR2、LPDDR3或类似的存储模块。
在一些实施例中，堆叠管芯212和接合引线214可通过模制材料216封装。例如使用压缩模制可将模制材料216模制在堆叠管芯212和接合引线214上。在一些实施例中，模制材料216是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可执行固化步骤以固化模制材料216，其中，固化可以是热固化、UV固化等或它们的组合。
在一些实施例中，堆叠管芯212和接合引线214埋入模制材料216中，并且在固化模制材料216之后，执行诸如研磨的平面化步骤以去除模制材料216的过量部分，并且为第二封装件200提供基本平坦的表面。
在形成第二封装件200之后，第二封装件200通过导电连接件210、接合焊盘206和TIV110接合至第一封装件100。在一些实施例中，堆叠存储管芯212可通过接合引线214、接合焊盘204和206、通孔208、导电连接件210和TIV110连接至管芯210。
导电连接件210可类似于上述导电连接件136，因此这里省略其描述，尽管导电连接件210和136不是必须相同。在一些实施例中，在接合导电连接件210之前，导电连接件210涂有诸如免清洁焊剂的焊剂(未示出)。导电连接件210可浸入焊剂中，或者焊剂可喷向导电连接件210。在另一实施例中，焊剂可施加于TIV110的表面。
第二封装件200和第一封装件100之间的接合可以是焊料接合或直接的金属-金属(诸如，铜-铜或锡-锡)接合。在一个实施例中，第二封装件200通过回流工艺接合至第一封装件100。在该回流工艺期间，导电连接件210与接合焊盘206和TIV110接触，以将第二封装件200物理连接和电连接至第一封装件100。在接合工艺之后，金属间化合物(IMC)218可形成在TIV110和导电连接件210之间的界面处，并且还形成在导电连接件210和接合焊盘206(未示出)之间的界面处。
图2B示出了在第一封装件100和第二封装件200之间以及在各导电连接件200之间形成底部填充物220。底部填充物220可由液体环氧树脂、可变形凝胶、硅橡胶、非导电膜、聚合物、PBO、聚酰亚胺、阻焊剂或它们的组合形成。底部填充物220为导电连接件210提供结构支撑，并且可以在导电连接件210接合在第一封装件100和第二封装件200之间之后使用毛细力分配底部填充物220。在这些实施例中，底部填充物220包括倒角(fillet)，其中，侧壁220A斜交于管芯120的背面120B。在一些实施例中，形成底部填充物220以在管芯120上方形成开口222。
图2C示出了分割的半导体封装件300。半导体封装件300可从框138处移除并且放置在诸如切割带的结构232的上方。半导体封装件300可通过切割工具234(诸如，管芯锯、激光等或它们的组合)进行分割。
图1A至图1J以及图2A至图2C中的第一封装件100和第二封装件200的数量仅是为了示意的目的而不用于限制。还可以具有大于或小于所示两个封装件的其他数量的封装件。
图3A至图3C示出了根据依稀实施例的半导体封装件300的截面图。参照图3A，该实施例具有包括倒角的底部填充物220。第一封装件100具有宽度W100，第二封装件具有宽度W200，并且底部填充物220具有介于第一和第二封装件100和200之间的外宽W220。底部填充物220中的开口222具有宽度W222，并且管芯120具有宽度W120。在一个实施例中，宽度W220小于或等于宽度W100，宽度W200小于或等于宽度W220，以及宽度W222小于或等于宽度W120。在另一实施例中，宽度W220小于宽度W100，宽度W200小于宽度W220，以及宽度W222小于宽度W120。底部填充物220在第一和第二封装件100和200之间具有高度H220(有时称为站立高度)。在一个实施例中，高度H220在约1μm至约200μm的范围内。
图3B示出了半导体封装件300的另一个实施例。该实施例类似于图3A的实施例，除了在底部填充物220中没有开口(参见图3A中的222)。开口222可通过仅在半导体封装件300的外缘周围而不在半导体封装件300的中央区域形成底部填充物220来形成。关于该实施例，这里将不再重复与先前描述的实施例类似的内容。
图3C示出了半导体封装件300的另一个实施例。该实施例与图3B中的实施例类似，除了在第一封装件100和底部填充物220之间夹置有缓冲层230。关于该实施例，这里将不再重复与先前描述的实施例类似的内容。
缓冲层230形成在管芯120(如果存在的话还有粘合层126)、TIV110和模制材料130上方。缓冲层230可由聚合物(诸如，聚酰亚胺、PBO等)形成。缓冲层230还可为LTHC材料。在一个实施例中，缓冲层230被形成为具有约0.1μm至约20μm的厚度。
通过从第一封装件100去除介电层106，可以减少第一封装件100的翘曲，因此可以改善第一封装件100和第二封装件200之间的共面性和站立高度控制。此外，免清洁焊剂的使用消除了第一封装件100和第二封装件200之间的焊剂残留的问题。此外，通过在切割工艺之前形成底部填充物220，保护导电连接件210不受切割工艺的碎片所引起的电路故障(例如，导电连接件之间的短路)的影响。此外，通过使第二封装件的宽度小于第一封装件100的宽度而在半导体封装件300之间为底部填充物220给出更大的空间，防止了两个半导体封装件300之间的底部填充物的污染以及相邻的第二封装件200之间的底部填充物的渗出。
图4A和图4B示出了根据一些其他实施例的形成半导体封装件300的中间步骤的截面图。该实施例类似于图1A至图1J以及图2A至图2C的实施例，除了在第一封装件100接合至第二封装件200之前形成并图案化底部填充物220。关于该实施例，将不再重复与先前描述的实施例类似的内容。
图4A示出了已经完成图1A至图1J所示的步骤之后的中间制造步骤。在图1J的步骤之后，底部填充物220形成在管芯120、模制材料130和TIV110上方。底部填充物220可通过CVD、PVD或ALD沉积，通过诸如旋涂工艺、丝印工艺的湿式工艺或者通过诸如滚压干膜的干式工艺来形成。在形成底部填充物220之后，底部填充物220被图案化以在TIV110上方形成开口224，以露出TIV110(和晶种层108，如果存在的话)的一部分。在一些实施例中，底部填充物220被图案化以在管芯120(和粘合层126，如果存在的话)上方形成开口222。可通过使用可接受的光刻技术和蚀刻(诸如，激光蚀刻工艺)来图案化底部填充物220。开口222被形成为具有宽度W222而开口224被形成为具有宽度W224。在一个实施例中，宽度W222小于或等于宽度W120，以及宽度W224小于或等于TIV110的宽度W110。在另一实施例中，宽度W222小于宽度W120，并且宽度W224小于宽度W110。在包括缓冲层230(参见图3C和图5C)的实施例中，开口224中的缓冲层130的开口宽度小于或等于宽度W224。底部填充物220可形成为具有1μm至约200μm的范围内的高度H220。在该实施例中，底部填充物220具有基本垂直于管芯120的背面120B的侧壁220A。在一些实施例中，底部填充物220被图案化，使得在相邻的第一封装件100之间的划线中不存在底部填充物220。
图4B示出了将第二封装件200附接至图4A所示的第一封装件100。这类似于上面参照图2A所述的工艺，除了在接合工艺期间存在底部填充物220。关于该实施例，不再重复与先前描述的实施例类似的内容。然后，封装件200和100将如上面参照图2C所描述的进行分割。
图5A至图5C示出了根据一些其他实施例的半导体封装件300的截面图。这些实施例类似于图3A至图3C所述的实施例，除了这些实施例中在将封装件接合到一起之前形成了底部填充物220以及底部填充物220的侧壁220A基本垂直于管芯120的背面且不具有倒角。关于该实施例，不再重复与先前描述的实施例类似的内容。
参照图5A，底部填充物220具有在管芯120上方的开口222。图5B示出了底部填充物220不具有在管芯120上方的开口222。图5C示出了其中缓冲层230位于第一封装件100上方的半导体封装件300。
通过从第一封装件100去除介电层106且在接合封装件之前形成底部填充物220，可以减少第一封装件100的翘曲，因此可以改进第一封装件100和第二封装件200之间的共面性和站立高度。此外，通过在分割工艺之前形成底部填充物220，保护导电连接件210不受分割工艺的碎片所引起的电路故障(例如，导电连接件之间的短路)的影响。此外，通过使第二封装件200小于第一封装件100而在半导体封装件300之间为底部填充物220提供更大的空间，防止了两个半导体封装件300之间的底部填充物的污染以及底部填充物在相邻的第二封装件200之间溢出的问题。
图6、图7A和图7B示出了根据一些其他实施例的形成半导体封装件的中间步骤的截面图。该实施例类似于上面参照图1J示出的实施例，除了利用研磨工艺而非蚀刻工艺来去除介电层106。关于该实施例，将不再重复与先前描述的实施例类似的内容。
在该实施例中，研磨工艺可以是化学机械抛光(CMP)工艺。研磨工艺可以去除晶种层108和粘合层126。在一些实施例中，表面130B、120B和110B基本共面。在一些其他实施例中，表面130B和120B基本共面，而表面110B凹陷在模制材料130中。
该实施例的处理可继续进行图2A至图2C所描述的附接第二封装件200以及分割。该实施例可采用图2A至图3C以及图4A和图5C所提出的任一底部填充物方案。
图7A示出了根据图6中的第一封装件100且利用图2A至图3C中的具有倒角的底部填充物方案而形成的半导体封装件300的截面图。尽管底部填充物220被示出具有开口222，但可以省略开口222。图7B示出了根据图6中的第一封装件100且利用图4A至图5C的非倒角底部填充物方案而形成的半导体封装件300的截面图。
图8示出了根据一些实施例的半导体封装件400的截面图。半导体封装件400包括安装至封装衬底402的半导体封装件300。半导体封装件300可以为上述半导体封装件300的任何实施例。半导体封装件300使用导电连接件136安装至封装衬底402。
封装衬底402可由诸如硅、锗、金刚石等的半导体材料制成。可选地，还可以使用化合物材料，诸如，硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷铟化镓、它们的组合等。因此，封装衬底402可以为SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底402基于诸如玻璃纤维增强树脂核的绝缘核。一个示例性核材料为诸如FR4的玻璃纤维。用于核材料的可选材料包括双马来酰亚胺-三嗪(BT)树脂，或者可选地，包括其他PCB材料或膜。诸如ABF的层积膜或其它层压件可用于衬底202。
衬底402可包括有源和无源器件(图8中未示出)。本领域技术人员应该意识到，诸如晶体管、电容器、电阻器、它们的组合等的各种器件可用于满足半导体封装件400的设计的结构和功能要求。可使用任何适当的方法来形成这些器件。
封装衬底402还可以包括金属化层404(未示出)和通孔。金属化层404可形成在有源和无源器件上方，并且被设计为连接各个器件以形成功能电路。金属化层404可由介电层(例如低k介电材料)和导电材料层(例如，铜)交替来形成，其中通孔将各个导电材料层，并且可通过任何适当的工艺(诸如沉积、镶嵌、双镶嵌等)来形成金属化层404。在一些实施例中，封装衬底402基本没有有源和无源器件。
半导体封装件400包括位于半导体封装件300和衬底402之间以及各导电连接件136之间的底部填充物406。底部填充物406可由液体环氧树脂、可变形凝胶、硅橡胶、非导电膜、聚合物、PBO、聚酰亚胺、阻焊剂或它们的组合形成。底部填充物406为导电连接件136提供结构支撑，并且可以在将导电连接件136接合在半导体封装件300和衬底402之间之后使用毛细力分配底部填充物406。在这些实施例中，底部填充物406包括倒角，并且可以沿半导体封装件向上延伸以邻接第一封装件100、底部填充物220和第二封装件200的侧壁。
通过从第一封装件去除介电层以及在接合封装件之前形成底部填充物，可以减少第一封装件的翘曲，因此可以改进第一封装件和第二封装件之间的共面性和站立高度。此外，通过在分割工艺之前形成底部填充物，保护导电连接件不受分割工艺的碎片所引起的电路故障(例如，导电连接件之间的短路)的影响。此外，通过使第二封装件小于第一封装件而在半导体封装件之间为底部填充物提供更大的空间，防止了两个半导体封装件之间的底部填充物的污染以及底部填充物在相邻的第二封装件之间溢出的问题。
一个实施例是一种方法，包括形成第一封装件。形成第一封装件包括：在载体衬底上方形成第一介电层；在第一介电层上方形成第一电连接件；将第一管芯附接为与第一电连接件相邻且位于第一介电层上方；在第一管芯和所述第一电连接件上方形成再分布层；在再分布层上方形成第二电连接件，第二电连接件连接至第一管芯和第一电连接件中的至少一个；去除载体衬底以露出第一介电层；以及去除第一介电层以露出第一管芯和第一电连接件的一部分。该方法还包括：利用接合结构将第二封装件接合至第一封装件，接合结构连接至第一电连接件；以及在第一封装件和第二封装件之间形成底部填充物。
另一个实施例是一种方法，包括：形成第一管芯封装件，第一管芯封装件包括第一管芯、第一电连接件和第一再分布层，第一再分布层连接至第一管芯和第一电连接件；在第一管芯封装件上方形成底部填充物；图案化底部填充物以具有露出第一电连接件的一部分的开口；以及利用接合结构将第二管芯封装件接合至第一管芯封装件，接合结构连接至底部填充物的开口中的第一电连接件。
又一实施例是一种半导体封装件，包括第一封装件。第一封装件包括：第一管芯；封装物，环绕第一管芯；以及封装通孔，延伸穿过封装物。该半导体封装件还包括第二封装件，其中包括第二管芯，第二封装件通过一组连接件接合至第一封装件；以及底部填充物，位于第一封装件和第二封装件之间并环绕一组连接件，底部填充物具有基本垂直于第一管芯的背面的侧壁。
上面论述了多个实施例的特征使得本领域技术人员能够更好地理解本发明的各个方面。本领域技术人员应该理解，他们可以容易地以本公开为基础设计或修改用于执行与本文所述实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员还应该意识到，这些等效结构不背离本发明的精神和范围，并且可以在不背离本发明的精神和范围的情况下做出各种变化、替换和改变。

Claims (10)

1.一种方法，包括：
形成第一封装件，包括：
在载体衬底上方形成第一介电层；
在所述第一介电层上方形成第一电连接件；
将第一管芯附接为与所述第一电连接件相邻且位于所述第一介电层上方；
在所述第一管芯和所述第一电连接件上方形成再分布层；
在所述再分布层上方形成第二电连接件，所述第二电连接件连接至所述第一管芯和所述第一电连接件中的至少一个；
去除所述载体衬底以露出所述第一介电层；和
去除所述第一介电层以露出所述第一管芯和所述第一电连接件的一部分；
利用接合结构将第二封装件接合至所述第一封装件，所述接合结构连接至所述第一电连接件；以及
在所述第一封装件和所述第二封装件之间形成底部填充物。
2.根据权利要求1所述的方法，其中，在所述第一封装件和所述第二封装件之间形成所述底部填充物包括：
在利用所述接合结构将所述第一封装件接合至所述第一封装件之后，在所述第一封装件和所述第二封装件之间注入所述底部填充物，所述底部填充物环绕所述接合结构。
3.根据权利要求2所述的方法，其中，在所述第一封装件和所述第二封装件之间注入所述底部填充物之后，所述第一管芯的一部分透过所述底部填充物露出。
4.根据权利要求1所述的方法，其中，在所述第一封装件和所述第二封装件之间形成所述底部填充物包括：
在利用所述接合结构将所述第一封装件接合至所述第二封装件之前，在所述第一封装件上方形成所述底部填充物；和
图案化所述底部填充物，以至少露出所述第一电连接件的一部分。
5.根据权利要求4所述的方法，其中，图案化所述底部填充物还包括：图案化所述底部填充物以露出所述第一管芯的一部分。
6.根据权利要求1所述的方法，其中，在所述第一封装件和所述第二封装件之间形成所述底部填充物包括：形成液体环氧树脂、可变形凝胶、硅橡胶、非导电膜、聚合物、聚苯并唑、聚酰亚胺、阻焊剂或它们的组合。
7.根据权利要求1所述的封装件方法，其中，去除所述第一介电层还包括：蚀刻所述第一介电层以露出所述第一管芯和所述第一电连接件的一部分。
8.一种方法，包括：
形成第一管芯封装件，所述第一管芯封装件包括第一管芯、第一电连接件和第一再分布层，所述第一再分布层连接至所述第一管芯和所述第一电连接件；
在所述第一管芯封装件上方形成底部填充物；
图案化所述底部填充物以具有露出所述第一电连接件的一部分的开口；以及
利用接合结构将第二管芯封装件接合至所述第一管芯封装件，所述接合结构连接至所述底部填充物的所述开口中的所述第一电连接件。
9.根据权利要求8所述的方法，还包括：将所述第一管芯封装件和所述第二管芯封装件与相邻的管芯封装件分割开以形成半导体封装件，所述半导体封装件包括所述第一管芯封装件和所述第二管芯封装件。
10.一种半导体封装件，包括：
第一封装件，包括：
第一管芯；
封装物，环绕所述第一管芯；和
封装通孔，延伸穿过所述封装物；
第二封装件，包括第二管芯，所述第二封装件通过一组连接件接合至所述第一封装件；以及
底部填充物，位于所述第一封装件和所述第二封装件之间并且环绕所述一组连接件，所述底部填充物具有基本垂直于所述第一管芯的背面的侧壁。
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783779A (zh) * 2016-12-02 2017-05-31 华进半导体封装先导技术研发中心有限公司 一种高堆叠扇出型系统级封装结构及其制作方法
CN107180795A (zh) * 2016-03-11 2017-09-19 台湾积体电路制造股份有限公司 包括电压调节器的集成扇出封装件及其形成方法
CN107845625A (zh) * 2016-09-19 2018-03-27 台湾积体电路制造股份有限公司 芯片封装结构
CN107946277A (zh) * 2016-10-13 2018-04-20 台湾积体电路制造股份有限公司 半导体装置以及半导体装置制造方法
CN108231601A (zh) * 2016-12-15 2018-06-29 台湾积体电路制造股份有限公司 半导体装置的制造方法
CN108428669A (zh) * 2018-03-07 2018-08-21 西安电子科技大学 三维异质集成系统的制作方法
CN109786274A (zh) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN110299326A (zh) * 2018-03-23 2019-10-01 台湾积体电路制造股份有限公司 用于形成半导体器件的方法和封装件
CN110556346A (zh) * 2018-05-30 2019-12-10 台湾积体电路制造股份有限公司 半导体结构
US10748870B2 (en) 2015-11-30 2020-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer COWOS structure
US11049779B2 (en) 2018-10-12 2021-06-29 Dyi-chung Hu Carrier for chip packaging and manufacturing method thereof
US11205615B2 (en) 2017-11-15 2021-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
CN116759389A (zh) * 2023-08-16 2023-09-15 长电集成电路(绍兴)有限公司 模拟封装模块及其制备方法、芯片封装结构的制备方法
CN116759390A (zh) * 2023-08-16 2023-09-15 长电集成电路(绍兴)有限公司 一种模拟芯片及其制备方法

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9543170B2 (en) * 2014-08-22 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
TWI581387B (zh) * 2014-09-11 2017-05-01 矽品精密工業股份有限公司 封裝結構及其製法
TWI559829B (zh) * 2014-10-22 2016-11-21 矽品精密工業股份有限公司 封裝結構及其製法
KR20170044919A (ko) * 2015-10-16 2017-04-26 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
WO2017122449A1 (ja) * 2016-01-15 2017-07-20 ソニー株式会社 半導体装置および撮像装置
KR102566996B1 (ko) * 2016-09-09 2023-08-14 삼성전자주식회사 FOWLP 형태의 반도체 패키지 및 이를 가지는 PoP 형태의 반도체 패키지
US10529697B2 (en) * 2016-09-16 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US9768133B1 (en) * 2016-09-22 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
KR102566145B1 (ko) 2016-10-18 2023-08-16 삼성전자주식회사 반도체 패키지의 제조 방법
US10170341B1 (en) 2017-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Release film as isolation film in package
DE102017012352B4 (de) 2017-06-30 2024-01-18 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren mit einem Trennfilm als Isolierfilm im Gehäuse und Gehäuse
US10438930B2 (en) * 2017-06-30 2019-10-08 Intel Corporation Package on package thermal transfer systems and methods
FR3070091B1 (fr) * 2017-08-08 2020-02-07 3Dis Technologies Systeme electronique comprenant une couche de redistribution inferieure et procede de fabrication d'un tel systeme electronique
US10636775B2 (en) * 2017-10-27 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US10566261B2 (en) 2017-11-15 2020-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages with embedded heat dissipation structure
DE102018106163A1 (de) * 2017-11-30 2019-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrierte Fan-out-Packages und Verfahren zu deren Herstellung
US11177142B2 (en) 2017-11-30 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for dicing integrated fan-out packages without seal rings
EP3547360A1 (de) * 2018-03-29 2019-10-02 Siemens Aktiengesellschaft Halbleiterbaugruppe und verfahren zur herstellung der halbleiterbaugruppe
US10546845B2 (en) * 2018-04-20 2020-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package on package structure
US10937743B2 (en) * 2018-04-30 2021-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Mixing organic materials into hybrid packages
US10832985B2 (en) * 2018-09-27 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Sensor package and method
DE102018132447B4 (de) * 2018-12-17 2022-10-13 Infineon Technologies Ag Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung
US11063019B2 (en) * 2019-07-17 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure, chip structure and method of fabricating the same
KR20210016119A (ko) 2019-07-31 2021-02-15 삼성전자주식회사 반도체 패키지
KR102609302B1 (ko) * 2019-08-14 2023-12-01 삼성전자주식회사 반도체 패키지의 제조 방법
US11211352B2 (en) * 2019-10-01 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure to prevent metal redeposit and to prevent bond pad consumption and corrosion
US11646293B2 (en) 2020-07-22 2023-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method
US11527518B2 (en) * 2020-07-27 2022-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Heat dissipation in semiconductor packages and methods of forming same
US11804445B2 (en) * 2021-04-29 2023-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming chip package structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040169275A1 (en) * 2003-02-27 2004-09-02 Motorola, Inc. Area-array device assembly with pre-applied underfill layers on printed wiring board
US20110285005A1 (en) * 2010-05-18 2011-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US20120061854A1 (en) * 2010-09-14 2012-03-15 Seng Guan Chow Integrated circuit packaging system with package-on-package and method of manufacture thereof
US20130105989A1 (en) * 2009-08-21 2013-05-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect
CN103367291A (zh) * 2012-03-28 2013-10-23 台湾积体电路制造股份有限公司 封装件层叠结构及其形成方法
CN103972191A (zh) * 2013-01-31 2014-08-06 台湾积体电路制造股份有限公司 具有环绕封装通孔端部的开口的管芯封装件及层叠封装件

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001094045A (ja) * 1999-09-22 2001-04-06 Seiko Epson Corp 半導体装置
US7026223B2 (en) * 2002-03-28 2006-04-11 M/A-Com, Inc Hermetic electric component package
JP4204989B2 (ja) 2004-01-30 2009-01-07 新光電気工業株式会社 半導体装置及びその製造方法
US7218007B2 (en) * 2004-09-28 2007-05-15 Intel Corporation Underfill material to reduce ball limiting metallurgy delamination and cracking potential in semiconductor devices
US7196427B2 (en) * 2005-04-18 2007-03-27 Freescale Semiconductor, Inc. Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element
KR100800478B1 (ko) * 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
US8017436B1 (en) * 2007-12-10 2011-09-13 Amkor Technology, Inc. Thin substrate fabrication method and structure
US9355962B2 (en) * 2009-06-12 2016-05-31 Stats Chippac Ltd. Integrated circuit package stacking system with redistribution and method of manufacture thereof
US8115293B2 (en) * 2009-12-08 2012-02-14 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8541872B2 (en) * 2010-06-02 2013-09-24 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
US8426961B2 (en) * 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
KR20120031697A (ko) * 2010-09-27 2012-04-04 삼성전자주식회사 패키지 적층 구조 및 그 제조 방법
US8703534B2 (en) * 2011-01-30 2014-04-22 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
KR101817159B1 (ko) * 2011-02-17 2018-02-22 삼성전자 주식회사 Ｔｓｖ를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법
US8530277B2 (en) * 2011-06-16 2013-09-10 Stats Chippac Ltd. Integrated circuit packaging system with package on package support and method of manufacture thereof
US8455989B2 (en) * 2011-07-01 2013-06-04 Texas Instruments Incorporated Package substrate having die pad with outer raised portion and interior recessed portion
US8587132B2 (en) * 2012-02-21 2013-11-19 Broadcom Corporation Semiconductor package including an organic substrate and interposer having through-semiconductor vias
US8901755B2 (en) * 2012-03-20 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming conductive layer over metal substrate for electrical interconnect of semiconductor die
US20130256894A1 (en) * 2012-03-29 2013-10-03 International Rectifier Corporation Porous Metallic Film as Die Attach and Interconnect
KR101867955B1 (ko) 2012-04-13 2018-06-15 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US8889484B2 (en) 2012-10-02 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for a component package
US9543170B2 (en) * 2014-08-22 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040169275A1 (en) * 2003-02-27 2004-09-02 Motorola, Inc. Area-array device assembly with pre-applied underfill layers on printed wiring board
US20130105989A1 (en) * 2009-08-21 2013-05-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect
US20110285005A1 (en) * 2010-05-18 2011-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US20120061854A1 (en) * 2010-09-14 2012-03-15 Seng Guan Chow Integrated circuit packaging system with package-on-package and method of manufacture thereof
CN103367291A (zh) * 2012-03-28 2013-10-23 台湾积体电路制造股份有限公司 封装件层叠结构及其形成方法
CN103972191A (zh) * 2013-01-31 2014-08-06 台湾积体电路制造股份有限公司 具有环绕封装通孔端部的开口的管芯封装件及层叠封装件

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10748870B2 (en) 2015-11-30 2020-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer COWOS structure
US11244924B2 (en) 2015-11-30 2022-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
CN107180795B (zh) * 2016-03-11 2019-09-06 台湾积体电路制造股份有限公司 包括电压调节器的集成扇出封装件及其形成方法
CN107180795A (zh) * 2016-03-11 2017-09-19 台湾积体电路制造股份有限公司 包括电压调节器的集成扇出封装件及其形成方法
US11063016B2 (en) 2016-03-11 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US10497668B2 (en) 2016-03-11 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
CN107845625A (zh) * 2016-09-19 2018-03-27 台湾积体电路制造股份有限公司 芯片封装结构
US11410956B2 (en) 2016-09-19 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump
CN107946277A (zh) * 2016-10-13 2018-04-20 台湾积体电路制造股份有限公司 半导体装置以及半导体装置制造方法
CN107946277B (zh) * 2016-10-13 2022-05-06 台湾积体电路制造股份有限公司 半导体装置以及半导体装置制造方法
US10964673B2 (en) 2016-10-13 2021-03-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method of the same
CN106783779B (zh) * 2016-12-02 2019-06-14 华进半导体封装先导技术研发中心有限公司 一种高堆叠扇出型系统级封装结构及其制作方法
CN106783779A (zh) * 2016-12-02 2017-05-31 华进半导体封装先导技术研发中心有限公司 一种高堆叠扇出型系统级封装结构及其制作方法
CN108231601B (zh) * 2016-12-15 2022-11-11 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN108231601A (zh) * 2016-12-15 2018-06-29 台湾积体电路制造股份有限公司 半导体装置的制造方法
US11205615B2 (en) 2017-11-15 2021-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10586763B2 (en) 2017-11-15 2020-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
CN109786274B (zh) * 2017-11-15 2021-06-15 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN109786274A (zh) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN108428669B (zh) * 2018-03-07 2020-11-17 西安电子科技大学 三维异质集成系统及其制作方法
CN108428669A (zh) * 2018-03-07 2018-08-21 西安电子科技大学 三维异质集成系统的制作方法
CN113113318A (zh) * 2018-03-23 2021-07-13 台湾积体电路制造股份有限公司 用于形成半导体器件的方法和封装件
CN110299326B (zh) * 2018-03-23 2021-03-09 台湾积体电路制造股份有限公司 用于形成半导体器件的方法和封装件
CN110299326A (zh) * 2018-03-23 2019-10-01 台湾积体电路制造股份有限公司 用于形成半导体器件的方法和封装件
US11942464B2 (en) 2018-03-23 2024-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
CN110556346A (zh) * 2018-05-30 2019-12-10 台湾积体电路制造股份有限公司 半导体结构
CN110556346B (zh) * 2018-05-30 2022-03-15 台湾积体电路制造股份有限公司 半导体结构及其形成方法
US11646281B2 (en) 2018-05-30 2023-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures
US11049779B2 (en) 2018-10-12 2021-06-29 Dyi-chung Hu Carrier for chip packaging and manufacturing method thereof
CN116759389A (zh) * 2023-08-16 2023-09-15 长电集成电路(绍兴)有限公司 模拟封装模块及其制备方法、芯片封装结构的制备方法
CN116759390A (zh) * 2023-08-16 2023-09-15 长电集成电路(绍兴)有限公司 一种模拟芯片及其制备方法

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