CN103972191A - 具有环绕封装通孔端部的开口的管芯封装件及层叠封装件 - Google Patents

具有环绕封装通孔端部的开口的管芯封装件及层叠封装件 Download PDF

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CN103972191A
CN103972191A CN201310261078.4A CN201310261078A CN103972191A CN 103972191 A CN103972191 A CN 103972191A CN 201310261078 A CN201310261078 A CN 201310261078A CN 103972191 A CN103972191 A CN 103972191A
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layer
package
tpv
semiconductor device
approximately
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CN103972191B (zh
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林俊成
洪瑞斌
郑礼辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了用于形成具有环绕封装通孔(TPV)的端部的开口的TPV以及具有利用TPV的接合结构的叠层封装(PoP)器件的机构的各个实施例。诸如通过采用激光钻孔去除环绕TPV的端部的材料来形成开口。环绕管芯封装件的TPV的端部的开口使形成在与另一管芯封装件之间的接合结构的焊料能够保留在开口中而不滑动，因此增加了接合结构的成品率和可靠性。还可以添加聚合物以填充环绕TPV的开口、甚至管芯封装件之间的空间，从而减少接合结构在应力下的开裂。

Description

具有环绕封装通孔端部的开口的管芯封装件及层叠封装件
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及半导体器件。
背景技术
半导体器件用于多种电子应用中，举例来说，诸如个人电脑、手机、数码相机和其它电子设备。通常通过在半导体衬底上方按顺序沉积的绝缘或介电层、导电层和半导体材料层，以及使用光刻法图案化各种材料层以在半导体衬底上形成电路部件和元件来形成半导体器件。
半导体产业通过继续减小最小部件尺寸来不断地改进各种电子部件(例如晶体管、二极管、电阻器、电容器等)的集成密度，从而允许更多的部件集成到给定区域中。在一些应用中，这些较小的电子部件也需要比过去的封装件利用更少面积和/或更低高度的较小封装件。
因此，开始开发新的封装技术，诸如叠层封装(POP)，其中，具有器件管芯的顶部封装件与具有另一器件管芯的底部封装件接合。通过采用新的封装技术，可以增大封装件的集成度。用于半导体的这些相对新型的封装技术面临着制造挑战。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体器件，包括：半导体管芯；介电材料，邻近所述半导体管芯；以及封装通孔(TPV)，设置在所述介电材料中，所述介电材料中的开口环绕所述TPV的端部以暴露所述端部，并且所述开口的至少一部分位于所述TPV的端部和模塑料之间。
在该半导体器件中，所述TPV的端部在所述开口的底部之上延伸的距离为约1μm至约70μm。
在该半导体器件中，所述TPV的端部包括喷镀晶种层和导电层，并且所述喷镀晶种层覆盖所述导电层的端面。
在该半导体器件中，所述TPV的端部包括喷镀晶种层和导电层，并且所述喷镀晶种层仅覆盖所述导电层的端面的一部分。
在该半导体器件中，所述开口的深度为约2μm至约100μm。
在该半导体器件中，所述开口具有圆角表面轮廓。
在该半导体器件中，所述开口具有成角度的表面轮廓。
在该半导体器件中，所述成角度的表面轮廓具有约90度的角度。
在该半导体器件中，所述开口包括与所述TPV的线性侧壁相交的所述介电材料的线性侧壁。
在该半导体器件中，所述介电材料的线性侧壁和垂直于所述TPV的线性侧壁的线之间的角度为约10度至约85度。
在该半导体器件中，所述介电材料包括模塑料层和位于所述模塑料层上方的钝化层，并且所述钝化层和所述模塑料层环绕所述TPV的端部。
在该半导体器件中，所述钝化层环绕所述开口的侧壁的表面与所述模塑料的侧壁的表面是连续的。
在该半导体器件中，所述开口的侧壁与所述TPV的端部的侧壁平行。
在该半导体器件中，所述介电材料包括位于第二介电层上方的第一介电层，所述开口延伸穿过所述第一介电层并延伸至所述第二介电层中，所述第二介电层的顶面在开口中形成平台。
根据本发明的另一方面，提供了一种半导体器件，包括：半导体管芯；一个或多个介电层，邻近所述半导体管芯；一个或多个封装通孔(TPV)，设置在所述一个或多个介电层中，所述一个或多个TPV从所述一个或多个介电层的第一面延伸到所述一个或多个介电层的第二面；以及凹槽，位于所述一个或多个介电层中且环绕对应的所述一个或多个TPV的端部，所述凹槽暴露所述一个或多个TPV的对应端部的侧壁的至少一部分。
根据本发明的又一方面，提供了一种半导体器件，包括：第一管芯封装件，所述第一管芯封装件包括：第一半导体管芯；位于所述第一半导体管芯相对面上的介电材料；和位于所述介电材料中的通孔(TV)，所述介电材料中的开口环绕所述TV的端部以暴露所述端部；以及第二管芯封装件，所述第二管芯封装件包括：第二半导体管芯；和外部连接件；其中，所述第二管芯封装件的所述外部连接件使用焊料接合至所述第一管芯封装件的所述TV的端部以形成接合结构，所述焊料至少部分地位于所述开口内。
该半导体器件进一步包括：在所述外部连接件和所述TV的端部之间所形成的金属间化合物(IMC)层，其中，所述IMC层覆盖所述TV的端部。
在该半导体器件中，所述TV的端部从所述开口的底部伸出的距离为约1μm至约70μm。
该半导体器件进一步包括：介于所述第一管芯封装件和所述第二管芯封装件之间的聚合物层，所述焊料的至少一部分嵌入所述聚合物层中。
该半导体器件进一步包括：介于所述第一管芯封装件和所述第二管芯封装件之间的底部填充物，所述底部填充物部分地填充所述开口。
附图说明
为了更充分地理解实施例及其优点，现将结合附图所进行的下列描述作为参考，其中：
图1A是根据一些实施例的封装结构的透视图；
图1B是根据一些实施例的管芯封装件接合至另一管芯封装件的截面图；
图2A至图2O示出根据一些实施例制备叠层封装(POP)器件的顺序工艺流程的截面图；
图3A至图3H示出根据一些实施例的环绕封装通孔(TPV)的暴露顶部的各种结构的截面图；以及
图4A至图4C示出根据一些实施例的各种接合结构的截面图。
具体实施方式
在下面详细论述本发明的实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的发明概念。所论述的具体实施例仅是示例性的，而不用于限制本发明的范围。
自从发明了集成电路以来，半导体产业由于不断改进各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度而经历了持续的快速增长。通常，集成密度的这种改进源于最小部件尺寸的不断减小，从而允许更多的部件集成到给定的区域中。
这些集成改进在本质上基本是二维(2D)的，原因在于被集成部件所占用的体积基本上位于半导体晶圆的表面上。虽然光刻方面的显著改进为2D集成电路形成带来了相当大的改进，但是对于在二维上可以达到的密度仍具有物理限制。这些限制中的一种是制造这些部件所需的最小尺寸。此外，当将更多的元件置于一个芯片中时，需要更复杂的设计。
因此为了解决上述限制而创建了三维集成电路(3D IC)。在3D IC的一些形成工艺中，形成两个或更多个晶圆，每一个晶圆都包括集成电路。对晶圆进行切割以形成管芯。对具有相同或不同器件的管芯进行封装，然后在器件对准的情况下进行接合。封装通孔(TPV)也被称为模塑通孔(through-molding-vias，TMV)，越来越多地用作实现3D IC的方法。诸如TPV的通孔(TV)经常用于3D IC和堆叠管芯中以提供电连接和/或辅助热耗散。除了TPV和TMV之外，TV还包括硅通孔(TSV)和其它适用的结构。
图1A是根据一些实施例的封装件100的透视图，其中封装件100包括接合的封装件110和另一封装件120，另一封装件120进一步与另一衬底130接合。管芯封装件110和120中的每一个都至少包括半导体管芯(未示出)。半导体管芯包括如在半导体集成电路制造中应用的半导体衬底，并且可以在半导体衬底中和/或半导体衬底上形成集成电路。半导体衬底是指包含半导体材料的任何构造，包括(但不限于)：块状硅、半导体晶圆、绝缘体上硅(SOI)衬底或硅锗衬底。也可以使用包括III族、IV族和V族元素的其它半导体材料。半导体衬底可以进一步包括多个隔离部件(未示出)，诸如浅沟槽隔离(STI)部件或局部硅氧化(LOCOS)部件。隔离部件可以限定和隔离各种微电子元件。可以在半导体衬底中形成的各种微电子元件的实例包括：晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高电压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管(PFET/NFET)等)；电阻器；二极管；电容器；电感器；以及其它合适的元件。执行各种工艺来形成各种微电子元件，各种工艺包括沉积、蚀刻、注入、光刻、退火和/或其它合适的工艺。互连微电子元件以形成集成电路器件，诸如逻辑器件、存储器件(例如，SRAM)、RF器件、输入/输出(I/O)器件、芯片上系统(SoC)器件、它们的组合以及其它合适类型的器件。根据一些实施例，封装件120包括封装通孔(TPV)并用作中介层。
衬底130可以由双马来酰亚胺三嗪(BT)树脂、FR-4(由编织玻璃纤维布和具有耐燃性的环氧树脂粘结剂组成的复合材料)、陶瓷、玻璃、塑料、胶带、膜或可以具有用于接收导电端子所需的导电焊盘或接合焊盘的其它支撑材料制成。在一些实施例中，衬底130是多层电路板。封装件110通过连接件115接合至封装件120，并且封装件120通过外部连接件145接合至衬底130。在一些实施例中，外部连接件145是诸如接合焊料凸块的接合凸块结构，或者是与连接焊料层接合的铜柱。本文所述的焊料可以含铅或者可以不含铅。
图1B示出了根据一些实施例的位于管芯封装件120上方的管芯封装件110的截面图。如图1B所示，封装件110包括两个半导体管芯112和113，其中管芯113设置在管芯112上方。然而，封装件110可以包括一个半导体管芯或两个以上的半导体管芯。在一些实施例中，在管芯112和113之间具有胶合层(未示出)。半导体管芯112和113可以包括如上面关于半导体管芯所述的多种微电子元件。半导体管芯112与衬底115接合。衬底115可以包括上面关于衬底130所述的各种材料和/或部件。根据一些实施例，半导体管芯112通过接合引线114与衬底115中的导电元件(未示出)电连接。类似地，半导体管芯113通过接合引线116与衬底115中的导电元件电连接。封装件110还包括模塑料111，模塑料覆盖半导体管芯112和113，以及还覆盖接合引线114和116。封装件110还包括用于外部连接的一些连接件117。连接件117形成在金属焊盘118上，金属焊盘118通过互连结构119与接合引线114和116电连接，互连结构119可以包括通孔和金属线。
根据一些实施例，如图1B所示，管芯封装件120包括半导体管芯121和TPV122，其中，TPV122环绕管芯121。封装件120还包括再分配结构125，再分配结构125包括一个或多个再分配层(RDL)123。再分配层(RDL)123是金属互连层，其可以包括金属线和通孔；并且再分配层(RDL)123被(一种或多种)介电材料包围。RDL123能够使管芯121扇出。如图1B所示，诸如球栅阵列(BGA)的外部连接件126与再分配结构125上的金属焊盘(未示出)连接。如图1B所示，TPV122与封装件110的连接件117连接。管芯121和外部连接件126位于再分配结构125的相对侧上。管芯121通过连接件127与再分配结构125连接。
在一些实施例中，管芯封装件110的连接件117由焊料制成。在一些实施例中，连接件117包括在焊料柱的端部处具有焊料的铜柱。连接件117的焊料与TPV122的暴露铜表面接合，TPV122填充有铜。然而，暴露的铜表面在暴露于空气时会形成氧化铜。结果，如在图1B的TPV122D所示出，氧化铜层141会形成在TPV122的表面上。虽然可以在TPV122的表面上施加助焊剂来去除形成在TPV122的表面上的氧化铜层，但是在一些实施例中，去除工艺是不一致的。结果，氧化铜层141或者氧化铜层141的至少一部分保留在一些TPV122(诸如TPV122D)上。连接件117的焊料不能很好地与氧化铜层141接合；因此，接合处会不牢固，从而会影响成品率和可靠性。
虽然助焊剂确实从诸如TPV122A、122B和122C的TPV去除氧化铜层，但是连接件117的焊料和TPV的铜之间的直接接触会形成金属间化合物(IMC)，诸如Cu:Sn。图1B示出根据一些实施例形成在连接件260的焊料和TPV122A、122B和122C的铜之间的IMC层142。由于改变了封装件120上的不同元件的热膨胀系数(CTE)，封装件120在封装工艺期间和/或在封装工艺之后会弯曲。这种弯曲(或翘曲)对在封装件120和封装件110之间通过接合连接件117和TPV122形成的接合结构会产生应力。应力会导致接合结构260(通过连接件117和TPV122形成的)的在TPV122和连接件117之间的界面所形成的IMC层142附近发生开裂，从而影响叠层封装(PoP)结构的成品率和可靠性。因此，需要在管芯封装件之间形成无上述问题的接合结构的机构。
图2A至图2O示出根据一些实施例制备叠层封装(PoP)器件的顺序工艺流程的截面图。图2A示出位于载具201上方的粘合层(或胶合层)202。根据一些实施例，载具201由玻璃制成。然而，对于载具201也可以使用其它材料。在一些实施例中，在载具201上方沉积或层压粘合层202。粘合层202可以由胶形成，或者可以是诸如箔的层压材料。在一些实施例中，粘合层202是感光的，并且在完成所涉及的封装工艺之后通过对载具201照射紫外(UV)光或激光很容易地与载具201分开。例如，粘合层202可以是由3M Company(St.Paul，Minnesota)制造的光热转换(LTHC)涂层。在一些其它实施例中，粘合层202是热敏性的。
在一些实施例中，在粘合层202上方形成钝化层208。钝化层208是电介质并且用作管芯封装件上的钝化层。在一些实施例中，钝化层208由诸如聚酰亚胺、聚苯并恶唑(PBO)的聚合物或者阻焊剂(solder resist)制成。钝化层208改进了形成在载具201上方的喷镀晶种层(在下文中描述的)的粘着性。如果喷镀晶种层能够很好地粘附至粘合层202，则可以省略钝化层208的形成。
根据一些实施例，如图2B所示，然后在钝化层208上形成喷镀晶种层204。在一些实施例中，喷镀晶种层204由铜制成并且通过物理汽相沉积(PVD)形成。然而，也可以使用其它的导电膜。例如，喷镀晶种层204可以由Ti、Ti合金、Cu和/或Cu合金制成。Ti合金和Cu合金可以包括银、铬、镍、锡、金、钨和它们的组合。在一些实施例中，喷镀晶种层204的厚度在约0.05μm至约1.0μm的范围内。在一些实施例中，喷镀晶种层204包括扩散阻挡层，在沉积喷镀晶种层之前形成该扩散阻挡层。喷镀晶种层204还可以用作与下层的粘着层。在一些实施例中，扩散阻挡层由Ti制成，其厚度在约0.01μm至约0.1μm的范围内。然而，扩散阻挡层可以由诸如TaN的其它材料或其它适用材料的制成，并且厚度范围不限于上面所述的范围。在一些实施例中，通过PVD形成扩散阻挡层。
根据一些实施例，如图2C所示，在沉积喷镀晶种层204之后，在喷镀晶种层204上方形成光刻胶层205。可以通过诸如旋涂工艺的湿法工艺或者通过诸如干膜的干法工艺来形成光刻胶层205。在形成光刻胶层205之后，对光刻胶层205进行图案化以形成开口206，该开口被填充后形成上文图1B中所述的TPV。所涉及的工艺包括光刻和抗蚀剂显影。在一些实施例中，开口206的宽度W在约40μm至约260μm的范围内。在一些实施例中，开口206的深度D在约5μm至约300μm的范围内。
根据一些实施例，此后，如图2D所示，在喷镀晶种层204上方喷镀导电层207以填充开口206。在一些实施例中，导电层207由铜或铜合金制成。在一些实施例中，层207的厚度D在约5μm至约300μm的范围内。
在喷镀间隙填充工艺之后，通过蚀刻工艺去除光刻胶层205，该蚀刻工艺可以是干法工艺或者湿法工艺。在一些实施例中，在去除光刻胶205之前，使用平坦化工艺来去除形成在光刻胶层205的表面203上方的多余的导电层207。图2E示出根据一些实施例在去除光刻胶205并且开口206中的导电层207被暴露作为(导电)柱122’之后的载具201上的结构的截面图。
在去除光刻胶层205且导电层207被示出为柱122’之后，去除暴露的喷镀晶种层204或喷镀晶种层204未位于导电层207下方的部分。通过蚀刻，诸如通过湿蚀刻去除喷镀晶种层204。为了去除铜，可以使用磷酸(H3PO4)和过氧化氢(H2O2)的水溶液。如果喷镀晶种层204包括扩散阻挡层，诸如Ti层，则可以使用HF水溶液。图2E示出保留位于导电层207下方的喷镀晶种层204并去除其余部分(或暴露部分)。
根据一些实施例，此后，如图2F所示，在载具201上方通过胶合层210将半导体管芯121附接到表面209。根据一些实施例，胶合层210由管芯附接膜(DAF)制成。DAF可以由环氧树脂、酚树脂、丙烯酸橡胶、二氧化硅填充物或它们的组合制成。图2F示出管芯121的连接件127背对表面209，该表面209位于钝化层208上方。然后在载具201上方的喷镀晶种层204的表面上施加液态模塑料材料来填充导电柱122’和管芯121之间的空间并覆盖管芯121和导电柱122’。然后实施热工艺来硬化模塑料材料并将其转换成模塑料123。根据一些实施例，如图2G所示，在形成环绕导电柱的模塑料123之后，导电柱122’成为TPV122”。
此后，实施平坦化工艺以去除多余的模塑料123，从而暴露TPV122”和管芯121的连接件127。在一些实施例中，平坦化工艺是研磨工艺。在一些其它实施例中，平坦化工艺是化学机械抛光(CMP)工艺。根据一些实施例，在图2H中示出平坦化后结构。
根据一些实施例，在平坦化工艺之后，如图2I所示，在图2H的结构上方的表面211上方形成再分配结构215。图2I示出第二再分配结构215包括RDL213，RDL213可以通过一个或多个诸如层212和214的钝化层绝缘。RDL213可以包括金属线和导电通孔。RDL213由导电材料制成并且与TPV122”和管芯121的连接件127直接接触。在一些实施例中，RDL213由铝、铝合金、铜或铜合金制成。然而，RDL213可以由其它类型的导电材料制成。钝化层212和214由(一种或多种)介电材料制成并且对于在接合外部连接件126与衬底130期间所产生的接合应力提供应力消除。在一些实施例中，钝化层212和214由诸如聚酰亚胺、聚苯并恶唑(PBO)或苯丙环丁烯(BCB)的聚合物制成。对钝化层214进行图案化以形成开口(未示出)，从而暴露部分RDL213以形成接合焊盘(未示出)。在一些实施例中，在接合焊盘上方形成凸块底部金属(UBM)层(未示出)。UBM层还可以内衬钝化层214的开口的侧壁。在一些实施例中，RDL213可以是单层。
在于2012年3月22日提交的名称为“Bump Structures for Multi-ChipPackaging”的第13/427,753号美国申请(代理人案卷号TSMC2011-1339)和于2011年12月28日提交的名称为“Packaged Semiconductor Device andMethod of Packaging the Semiconductor Device”的第13/338,820号美国申请(代理人案卷号TSMC2011-1368)中描述了再分配结构和接合结构及其形成方法的实例。上面提到的两个申请全都以其全文内容结合到本文中作为参考。
根据一些实施例，如图2J所示，在形成再分配结构215之后，在再分配结构215的接合焊盘(未示出)上安装外部连接件216(或者将外部连接件接合至再分配结构的接合焊盘)。根据一些实施例，对载具201上的管芯进行电测试以检查管芯的功能性以及还检查TPV122”、再分配结构215和接合的外部连接件216的形成的质量。在一些实施例中，还实施可靠性测试。
根据一些实施例，如图2K所示，在将外部连接件216安装在接合焊盘上之后，将图2J中的结构进行翻转并附接至胶带219。根据一些实施例，胶带219是感光的，并且通过对胶带219照射紫外(UV)光可以很容易地将其与管芯121的管芯封装件分开。在将图2J的结构附接至胶带219之后，去除粘合层202。根据一些实施例，使用激光器来提供热量以去除粘合层202。图2L示出在去除粘合层202之后的图2K的结构。
根据一些实施例，如图2M所示，在去除粘合层202之后，去除模塑料123和钝化层208环绕TPV122”的顶部(远离连接件216的部分或者端部)的部分。在一些实施例中，使用激光工具来去除(通过钻孔)环绕TPV122”的顶部的材料，诸如模塑料123和钝化层208，从而暴露顶部。图3A至图3H示出环绕TPV122”的暴露顶部的结构的各个实施例，在下文中对其进行更详细的描述。
在去除模塑料123和钝化层208环绕TPV122”的顶部的部分之后，完成半导体管芯121的封装工艺，半导体管芯121被封装为封装管芯120’。根据一些实施例，然后将胶带219上的封装管芯120’分割成单独的封装管芯120’。分割通过管芯切割实现。在完成分割之后，从封装管芯去除胶带219。图2N示出根据一些实施例在去除胶带219之后的封装管芯120’。图2N中的区域X包括TPV122”。在图3A至图3H中示出了区域X中的结构的各个实施例，并在下文中进行描述。
然后，将单独的封装管芯120’接合至其它管芯封装件以形成叠层封装(PoP)结构。根据一些实施例，如图2O所示，将管芯封装件110放置在管芯封装件120’上方并接合至管芯封装件120’。将管芯封装件110的外部连接件117接合至管芯封装件120’的TPV122”，从而形成接合结构260’。每个TPV122”都包括主体和喷镀晶种层204，主体由铜制成，而喷镀晶种层204可以由铜、Ti、或它们的组合制成。连接件117与PTV122”的接合涉及回流工艺，从而会导致紧挨着TPV122”的外部(和先前暴露的)轮廓形成IMC层142’。如果在喷镀晶种层204中包含IMC层142’，则IMC层142’含有铜、焊料和Ti。在一些实施例中，IMC层142’的厚度在约0.5μm至约10μm的范围内。
通过去除环绕TPV122”的顶部的材料以形成环绕TPV122”的顶部的开口220，形成在每个TPV122”上的IMC层142’不是二维(2D)表面层，诸如图1B的IMC层142在应力下在角部处很容易开裂。相反，如图2O所示，IMC层142’是覆盖TPV122”伸出到模塑料123上方的部分的表面的三维(3D)层。这种3D层较牢固并且在应力下不可能开裂。结果，由连接件117和TPV122”所形成的接合结构比没有开口220的那些接合结构(诸如图1B所示的接合结构)更强。图2O中的区域Y包括具有连接件117和TPV122”的接合结构260’。在图4A至图4C中示出区域Y中的结构的各个实施例并在下文进行描述。
图3A示出根据一些实施例的图2N的区域X的放大图。区域X包括通过模塑料123环绕的TPV122”。TPV122”与RDL213连接，如上所述，RDL213通过钝化层212和214绝缘。图3A示出TPV122”包括位于导电层207上方的喷镀晶种层204。诸如通过激光钻孔去除覆盖喷镀晶种层204和导电层207的顶部的钝化层208和模塑料123，从而形成开口300A。如果喷镀晶种层204和导电层207由相同的诸如铜或铜合金的导电材料制成，则TPV122”会表现为由一种材料制成且无明显的界面。
开口300A在钝化层208的表面301之下具有深度D1。在一些实施例中，D1在约2μm至约100μm的范围内。开口300A在喷镀晶种层204的表面302A之下具有深度D2。在一些实施例中，D2在约1μm至约70μm的范围内。开口300A的下部从TPV122”的侧壁表面304到模塑料123的侧壁表面303具有宽度W1。在一些实施例中，W1在约2μm至约50μm的范围内。开口300A的顶部宽度W2宽于TPV122”的宽度W。在一些实施例中，W2在约30μm至约300μm的范围内。
图3A示出开口300A的侧壁303是基本上竖直的并且基本上垂直于开口300A的底面。此外，侧壁的表面是连续的和光滑的。可选地，根据一些实施例，如图3B所示，在开口300B的模塑料123处的角部可以是圆角。开口300B的剩余部分(诸如D1、D2、W1和W2的范围)与开300类似。
图3A和图3B示出钝化层208的侧壁和模塑料123的侧壁的连接302A和302B是光滑的。通过控制激光钻孔工艺来实现侧壁之间的光滑连接302A和302B，该激光钻孔工艺的工艺参数包括钻孔能量、钻孔角度和钻孔时间。对钻孔工艺进行调节以去除钝化层208和模塑料123，但不去除喷镀晶种层204或导电层207。在一些实施例中，钻孔能量在约0.1mJ至约30mJ的范围内。在一些实施例中，钻孔角度为与钝化层208的表面301的法线所成角度，其在约0度(垂直于表面301)至约85度的范围内。在一些实施例中，对于每个开口300A或300B，钻孔时间在约1μs至约150μs的范围内。
如上所述，图3A和图3B示出钝化层208的侧壁和模塑料123的侧壁的连接302A和302B是光滑的。可选地，这两层的侧壁之间的连接可以是不光滑的。图3C示出根据一些实施例的模塑料123的侧壁303是基本上竖直的开口300C。然而，钝化层208的侧壁倾斜与平行于钝化层208的表面302的表面的角度θ。在一些实施例中，角度θ在约10度至约85度的范围内。结果，钝化层208和模塑料123的开300C的侧壁之间的连接302C不光滑并且具有尖角。开300C中的最宽的部分具有宽度W3。在一些实施例中，W3在约30μm至约300μm的范围内。开300C的剩余部分(诸如D1、D2、W1和W2的范围)与图3A中的那些范围类似。可以调节激光钻孔工艺以形成图3C所示的轮廓。钝化层208和模塑料123的其它侧壁轮廓也是可能的。
图3D示出根据一些实施例的钝化层208和模塑料123的侧壁倾斜与平行于钝化层208的表面301的表面的角度α的开口300D。在一些实施例中，角度α在约10度至约85度的范围内。图3D的剩余部分(诸如D1、D2和W3的范围)与图3C类似。
图3E示出根据一些实施例的具有位于模塑料123上的倾斜侧壁和位于钝化层208上的基本上竖直的侧壁的开口300E。在模塑料123的侧壁和钝化层208的侧壁之间的连接302E上具有平台(ledge)。平台的距离W4在约3μm至约40μm的范围内。图3E的剩余部分(诸如D1、D2、W1、W2、W3和角度α的范围)与图3C和图3D中的描述的那些范围类似。
图3F示出根据一些实施例的其中喷镀晶种层204F大于导电层207的开口300F。除了喷镀晶种层204F比导电层207宽，图3F中的结构与图3A中的结构类似。宽度(或突出的宽度)差W5在约0.001μm至约1μm的范围内。如图2E所示，是在去除未被导电层207覆盖的喷镀晶种层204期间形成喷镀晶种层204F的突出部分。可以对去除工艺的蚀刻时间进行控制以保留喷镀晶种层204未被导电层207覆盖的小部分。图3F的剩余部分(诸如D1、D2、W1和W2的范围)与图3A中所述的那些范围类似。然而，图3B至图3E中所述的其它轮廓也可以适用于图3F的实施例中。
图3G示出根据一些实施例的其中喷镀晶种层204G相对于导电层207是缩进的开口300G。除了喷镀晶种层204G比导电层207窄之外，图3G类似于图3F。凹槽W6在约0.001μm至约1μm的范围内。如图2E所示，可以在去除未被导电层207覆盖的喷镀晶种层204期间通过过蚀刻形成该凹槽。类似地，图3B至图3E所述的其它轮廓也可以适用于图3G的实施例中。
图3H示出根据一些实施例的具有基本上位于模塑料123上而不位于钝化层208上的侧壁的开口300H。在这种情况下，去除钝化层208。根据一些实施例，在形成开口300H之前去除钝化层208。图3H的剩余部分(诸如D2、W1和W2的范围)与图3A中所述的那些范围类似。在图3B(开口的下部圆角)、图3D(倾斜侧壁)、图3F(突出喷镀晶种层)和图3G(凹凹进的喷镀晶种层)中所述的其它轮廓也可以适用于图3H的实施例中。
如上所述，图2O中的区域Y包括具有来自上管芯封装件110的连接件117和下管芯封装件120’的TPV122”的接合结构260’。以下描述Y区域中的结构的各个实施例。图4A示出根据一些实施例的连接件117接合至TPV122”未嵌入模塑料123和钝化层208中的顶部的接合结构260’。在接合之前，TPV122”附近的结构是上面所述的图3D的结构和图3E的结构之间的混合结构。开口300’具有位于钝化层208和模塑料123上的倾斜侧壁。钝化层208从模塑料123的边缘往回凹陷，如图4A所示。在接合工艺(热工艺)之后，由喷镀晶种层204中的诸如Cu、Ti或这二者的材料和连接件117的焊料材料形成IMC层142’。根据接合工艺，导电层207的一部分(铜)可以位于IMC层142’中。IMC层142’环绕TPV122”的伸出部分进行覆盖。IMC层142’具有顶部和侧部，顶部基本上是平坦的，侧部形成环绕伸出的TPV122”的环。IMC层142’的厚度在约0.2μm至约8μm的范围内。连接件117的上部与接合焊盘118可以形成另一IMC层143。IMC层143的厚度取决于接合焊盘118的材料。诸如Ni、Au、Ag的一些材料不会与连接件117中的焊料形成IMC层143或者形成非常薄的IMC层143。因此，在一些实施例中，IMC层143可以不存在。
由于开口300’环绕TPV122”的伸出部分，连接件117的放置会更准确并且连接件117不会水平滑动从而错过部分TPV122”。在将连接件117放置并接合至与模塑料123齐平的TPV122(诸如图1B所示的那些TPV122)时，会发生连接件117的水平滑动。这种水平滑动会导致连接件117与邻近的TPV122短路。此外，形成的IMC层142’被成形为帽状物(3D结构)而不是表面(2D结构)。结果，IMC142’不会轻易成为接合结构的最弱点，并且也不会如图1B的接合结构260那样容易开裂。这个观察结果得到了研究的支持。接合结构260’的成品率和可靠性优于接合结构260。
图4B示出根据一些实施例嵌入聚合物层270中的接合结构260”的一部分。如上面所提到的，诸如通过激光钻孔去除了环绕TPV122”的顶部的模塑料123。在模塑料123上方可以存在或者可以不存在钝化层208。钝化层208的存在是可选的。环绕接合结构260”的下部形成聚合物层270。在将管芯封装件110接合至管芯封装件120’之前，可以在管芯封装件120’的表面上施加助焊剂，并且助焊剂覆盖TPV122”和模塑料123的暴露表面。施加的助焊剂防止暴露的喷镀晶种层204和导电层207被环境以及在接合工艺期间发生氧化。助焊剂在其施加于封装件120’的表面上时是含聚合物的液体，并且在接合工艺完成之后，诸如通常通过清洁液去除助焊剂。然而，助焊剂可以保留在封装件120’的表面上并且成为聚合物层270，该聚合物层270在应力下屈服并且可以防止接合结构260’开裂。在助焊剂中包含的聚合物可以是环氧聚合物或者其它类型的聚合物。聚合物层270的厚度DF在约0.5μm至约30μm的范围内。如果不存在钝化层208，则从模塑料123的表面开始测量厚度DF；如果存在钝化层208，则从钝化层208的表面开始测量厚度DF。在封装件110面向封装件120’的表面305和模塑料123的表面306之间相隔距离DS。根据一些实施例，DF小于DS。
图4C示出根据一些实施例的嵌入底部填充物275中的接合结构260’。如上面所提到的，诸如通过激光钻孔去除了环绕TPV122”的顶部的模塑料123。在模塑料123上方可以存在或者可以不存在钝化层208。钝化层208的存在是可选的。在连接件117接合至TPV122”之后，形成环绕接合结构260’的底部填充物275。底物填充物275包含聚合物，诸如UF3808和UF3810(二者均为基于环氧的底部填充物材料)。如图4C所示，底部填充物275填充管芯封装件110和120’之间的空间。由聚合物制成的底部填充物275在应力下屈服并且保护接合结构260’不开裂。
提供了形成具有环绕封装通孔(TPV)的端部的开口的封装通孔(TPV)以及具有利用TPV的接合结构的叠层封装(PoP)器件的机构的一些实施例。通过诸如采用激光钻孔去除环绕TPV的端部的材料来形成开口。环绕管芯封装件的TPV的端部的开口使在与另一管芯封装件之间形成的接合结构的焊料能够保留在开口中而不滑动，因此增加接合结构的成品率和可靠性。也可以添加聚合物来填充环绕TPV的开口、甚至填充管芯封装件之间的空间以减少接合结构在应力下的开裂。
在一些实施例中，提供了一种半导体器件。半导体器件包括半导体管芯和邻近半导体管芯的介电材料。半导体器件还包括设置在介电材料中的封装通孔(TPV)。介电材料中的开口环绕TPV的端部从而暴露端部，并且其中开口的至少一部分位于TPV的端部和模塑料之间。
在一些实施例中，提供了一种半导体器件。半导体器件包括半导体管芯和邻近半导体管芯的一个或多个介电层。半导体管芯还包括设置在一个或多个介电层中的一个或多个封装通孔(TPV)。一个或多个TPV从一个或多个介电层的第一面延伸到一个或多个介电层的第二面。半导体器件还包括位于一个或多个介电层中且环绕对应的一个或多个TPV的端部的凹槽。凹槽暴露对应的一个或多个TPV的端部的侧壁的至少一部分。
在又一些实施例中，提供了一种半导体器件。该半导体器件包括第一管芯封装件。第一管芯封装件包括第一半导体管芯和位于该第一半导体管芯相对面上的介电材料。第一管芯封装件还包括位于介电材料中的通孔(TV)，并且介电材料中的开口环绕TV的端部以暴露端部。半导体器件还包括第二管芯封装件。第二管芯封装件包括第二半导体管芯和外部连接件。第二管芯封装件的外部连接件使用焊料接合至第一管芯封装件的TV的端部以形成接合结构。焊料至少部分地位于开口内。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的实施例的精神和范围的情况下，进行各种改变、替换和更改。而且，本申请的范围并不仅限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明将很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外，每条权利要求构成单独的实施例，并且各个权利要求和实施例的组合也在本发明的范围内。

Claims (10)

1.一种半导体器件，包括：
半导体管芯；
介电材料，邻近所述半导体管芯；以及
封装通孔(TPV)，设置在所述介电材料中，所述介电材料中的开口环绕所述TPV的端部以暴露所述端部，并且所述开口的至少一部分位于所述TPV的端部和模塑料之间。
2.根据权利要求1所述的半导体器件，其中，所述TPV的端部在所述开口的底部之上延伸的距离为约1μm至约70μm。
3.根据权利要求1所述的半导体器件，其中，所述TPV的端部包括喷镀晶种层和导电层，并且所述喷镀晶种层覆盖所述导电层的端面。
4.根据权利要求1所述的半导体器件，其中，所述TPV的端部包括喷镀晶种层和导电层，并且所述喷镀晶种层仅覆盖所述导电层的端面的一部分。
5.根据权利要求1所述的半导体器件，其中，所述开口的深度为约2μm至约100μm。
6.根据权利要求1所述的半导体器件，其中，所述开口具有圆角表面轮廓。
7.根据权利要求1所述的半导体器件，其中，所述开口具有成角度的表面轮廓。
8.根据权利要求7所述的半导体器件，其中，所述成角度的表面轮廓具有约90度的角度。
9.一种半导体器件，包括：
半导体管芯；
一个或多个介电层，邻近所述半导体管芯；
一个或多个封装通孔(TPV)，设置在所述一个或多个介电层中，所述一个或多个TPV从所述一个或多个介电层的第一面延伸到所述一个或多个介电层的第二面；以及
凹槽，位于所述一个或多个介电层中且环绕对应的所述一个或多个TPV的端部，所述凹槽暴露所述一个或多个TPV的对应端部的侧壁的至少一部分。
10.一种半导体器件，包括：
第一管芯封装件，所述第一管芯封装件包括：
第一半导体管芯；
位于所述第一半导体管芯相对面上的介电材料；和
位于所述介电材料中的通孔(TV)，所述介电材料中的开口环绕所述TV的端部以暴露所述端部；以及
第二管芯封装件，所述第二管芯封装件包括：
第二半导体管芯；和
外部连接件；
其中，所述第二管芯封装件的所述外部连接件使用焊料接合至所述第一管芯封装件的所述TV的端部以形成接合结构，所述焊料至少部分地位于所述开口内。
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