KR20180089332A - 패키지 구조체 및 이의 형성 방법 - Google Patents

패키지 구조체 및 이의 형성 방법 Download PDF

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KR20180089332A
KR20180089332A KR1020180070347A KR20180070347A KR20180089332A KR 20180089332 A KR20180089332 A KR 20180089332A KR 1020180070347 A KR1020180070347 A KR 1020180070347A KR 20180070347 A KR20180070347 A KR 20180070347A KR 20180089332 A KR20180089332 A KR 20180089332A
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layer
insulating layer
conductive structure
package
oxide
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KR1020180070347A
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KR102026568B1 (ko
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첸-후아 유
체이-충 푸
징-쳉 린
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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Abstract

패키지 구조체 및 이를 형성하는 방법이 제공된다. 패키지 구조체는 기판과 기판 위에 형성된 반도체 다이를 포함한다. 또한, 패키지 구조체는 반도체 다이를 덮는 패키지층과 패키지층 내에 형성된 도전성 구조체를 포함한다. 패키지 구조체는 도전성 구조체 상에 형성된 제1 절연층을 포함하고, 제1 절연층은 1가 금속 산화물을 포함한다. 제2 절연층은 제1 절연층과 패키지층 사이에 형성다. 제2 절연층은 1가 금속 산화물을 포함하고, 제2 절연층 내의 1가 금속 산화물의 중량비는 제1 절연층 내의 1가 금속 산화물의 중량비보다 더 크다.

Description

패키지 구조체 및 이의 형성 방법{PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME}
[관련 출련에 대한 교차 참조]
본 출원은, 전문이 본 명세서에 참조로서 편입되는, 2015년 12월 16일 출원되고, 함께 계류 중이고, 공동 양수된 미국 특허 출원 No. 14/970,962에 관한 것이다(대리인 도켓 No. 0941-3295PUS1).
반도체 소자는 개인용 컴퓨터, 휴대 전화, 디지털 카메라 및 다른 전자 장치와 같은 다양한 전자 애플리케이션에서 사용된다. 반도체 소자는 일반적으로 반도체 기판 위에 절연층 또는 유전층, 도전층 및 반도체층을 순차적으로 부착하고, 그 위에 회로 부품 및 요소를 형성하기 위하여 리소그라피를 이용하여 다양한 재료층을 패터닝함으로써 제조된다. 많은 집적 회로는 일반적으로 단일 반도체 웨이퍼 상에 제조되고, 웨이퍼 상의 개별 다이는 스크라이브 선을 따라 집적 회로 사이를 자르는(sawing) 것으로 싱귤레이트된다. 개별 다이는 일반적으로 개별적으로, 멀티 칩 모듈로, 또는 다른 종류의 패키징으로 패키징된다.
소자 다이를 갖는 상부 패키지가 다른 소자 다이를 갖는 하부 패키지에 접합되는 PoP(package on package)와 같은 새로운 패키징 기술이 개발되기 사작하였다. 새로운 패키징 기술을 채택함으로써, 상이하거나 유사한 기능을 갖는 다양한 패키지가 함께 통합될 수 있다.
기존의 패키지 구조체 및 패키지 구조체를 제조하는 방법이 대체로 의도된 목적에 대하여 적합하지만, 모든 면에서 완전히 만족스러은 것은 아니었다.
본 개시 내용의 양태들은 이어지는 발명을 실시하기 위한 구체적인 내용으로부터 첨부된 도면과 함께 숙독될 때 가장 잘 이해된다. 업계에서의 표준 관행에 따라, 다양한 특징부들은 배율에 맞추어 작도되지 않은 것이 주목되어야 한다. 사실, 다양한 특징부의 치수는 논의의 명료성을 위하여 임의로 증가되거나 또는 감소될 수 있다.
도 1a 내지 1n은 본 개시 내용의 일부 실시예에 따라 패키지 구조체를 형성하는 다양한 단계를 나타내는 단면도를 도시한다.
도 1hb는 본 개시 내용의 일부 실시예에 따라 도전성 구조체 상에 수행된 습식 공정을 나타내는 단면도를 도시한다.
도 2a는 본 개시 내용의 일부 실시예에 따라 플라즈마 공정 또는 습식 공정 전의 도전성 구조체를 나타내는 상면도를 도시한다.
도 2b는 본 개시 내용의 일부 실시예에 따라 플라즈마 공정 또는 습식 공정 후의 도전성 구조체를 나타내는 상면도를 도시한다.
도 3a는 본 개시 내용의 일부 실시예에 따라 플라즈마 공정 또는 습식 공정 전의 도전성 구조체를 나타내는 상면도를 도시한다.
도 3b는 본 개시 내용의 일부 실시예에 따라 플라즈마 공정 또는 습식 공정 후의 도전성 구조체를 나타내는 상면도를 도시한다.
다음의 개시 내용은 제공된 내용의 다양한 특징을 구현하기 위한 많은 상이한 실시예 또는 예를 제공한다. 컴포넌트 및 장치의 특정 예가 본 개시 내용을 간략화하기 위하여 아래에서 설명된다. 물론, 이들은 단순히 예이며, 한정하는 것으로 의도되지 않는다. 예를 들어, 이어지는 설명에서 제2 특징 위 또는 그 상의 제1 특징의 형성은 제1 및 제2 특징이 직접 접촉하여 형성되는 실시예를 포함할 수 있으며, 또한, 제1 및 제2 특징이 직접 접촉하지 않을 수 있도록, 추가 특징들이 제1 및 제2 특징 사이에 형성될 수 있는 실시예를 포함할 수 있다. 또한, 본 개시 내용은 다양한 예에서 도면 부호 및/또는 기호를 반복할 수 있다. 이러한 반복은 단순 명료의 목적을 위한 것이며, 자체로 논의된 다양한 실시예 및/또는 구성 사이의 관계를 말하는 것은 아니다.
실시예들의 일부 변형예가 설명된다. 다양한 도면과 예시적인 실시예의 전체에 걸쳐, 유사한 도면 부호는 유사한 요소를 지시하는데 사용된다. 추가 동작이 방법의 전, 방법 동안 또는 방법 후에 제공될 수 있고, 설명되는 동작의 일부는 방법의 다른 실시예에 대하여 교체되거나 생략될 수 있다.
패키지 구조체 및 이를 형성하는 방법에 대한 실시예가 제공된다. 도 1a 내지 1n은 본 개시 내용의 일부 실시예에 따라 패키지 구조체(100)를 형성하는 다양한 단계를 나타내는 단면도를 도시한다. 패키지 구조체(100)는 웨이퍼 레벨 패키지(wafer level package; WLP)에 적용된다.
도 1a에 도시된 바와 같이, 기판(102)이 제공된다. 기판(102)은 임시 지지 기판이다. 일부 실시예에서, 기판(102)은 반도체 재료, 세라믹 재료, 폴리머 재료, 금속 재료, 다른 적용 가능한 재료 또는 이들의 조합으로 이루어진다. 일부 실시예에서, 기판(102)은 유리 기판이다. 일부 실시예에서, 기판(102)은 실리콘 웨이퍼와 같은 반도체 기판이다.
접착층(104)이 기판(102) 상에 형성된다. 일부 실시예에서, 접착층은 접착제(glue) 또는 포일(foil)로 이루어진다. 일부 다른 실시예에서, 접착층(104)은 광 조사에 의해 기판(102)으로부터 쉽게 분리되는 감광 재료로 이루어진다. 일부 실시예에서, 접착층(104)은 감열 재료로 이루어진다.
그 후에, 베이스층(106)이 접착층(104) 상에 형성된다. 일부 실시예에서, 베이스층(106)은 폴리머층 또는 폴리머 함유층으로 이루어진다. 베이스층(106)은 PBO(poly-p-phenylenebenzobisthiazole) 층, PI(polyimide) 층, SR(solder resist) 층, ABF(Ajinomoto buildup film), DAF(die attach film), 다른 적용 가능한 재료 또는 이들의 조합일 수 있다. 일부 실시예에서, 접착층(104) 및 베이스층(106)은 기판(102) 위에 부착되거나 측정된다.
그 후에, 본 개시 내용의 일부 실시예에 따라, 도 1b에 도시된 바와 같이 시드층(108)이 베이스층(106) 위에 형성된다. 일부 실시예에서, 시드층(108)은 구리(Cu), 티타늄(Ti), 구리 합급, 티타늄 합금 또는 이들의 조합으로 이루어진다. 일부 실시예에서, 시드층(108)은 CVD(chemical vapor deposition) 공정, PVD(physical vapor deposition) 공정, 다른 적용 가능한 공정 또는 이들의 조합과 같은 부착(deposition) 공정에 의해 형성된다.
시드층(108)이 베이스층(106) 상에 형성된 후에, 본 개시 내용의 일부 실시예에 따라, 도 1c에 도시된 바와, 같이 마스크층(110)이 시드층(108) 상에 형성된다. 개구(112)가 마스크층(110) 내에 형성된다. 시드층(108)은 개구(112)에 의해 노출된다. 개구(112)는 도전성 구조체(이후에 형성되고, 도 1d에 도시됨)의 위치를 정의하는데 사용된다. 일부 실시예에서, 마스크층(110)은 포토레지스트 재료로 이루어진다. 개구(112)는 패터닝 공정에 의해 형성된다. 패터닝 공정은 포토리소그라피 공정 및 에칭 공정을 포함한다. 포토리소그라피 공정의 예는 소프트 베이킹, 마스크 정렬, 노광, 후노광 베이킹, 포토레지스트 현상, 린싱(rinsing) 및 건조(예를 들어, 하드 베이킹)를 포함한다. 에칭 공정은 건식 에칭 또는 습식 에칭 공정일 수 있다.
그 후에, 본 개시 내용의 일부 실시예에 따라, 도 1d에 도시된 바와 같이, 도전성 구조체(114)가 마스크층(110) 내에 형성된다. 도전성 구조체(114)는 개구(112) 내로 충전된다. 도전성 구조체(114)는 구리(Cu), 알루미늄(Al), 텅스텐(W), 니켈(Ni), 이들의 합금 또는 이들의 조합과 같은 금속 재료로 이루어질 수 있다. 도전성 구조체(114)를 위에서 본 형상은 직사각형, 정사각형, 원 또는 이와 유사한 것일 수 있다. 도전성 구조체(114)의 높이는 마스크층(110)의 두께에 따른다. 일부 실시예에서, 도전성 구조체(114)는 도금 공정에 의해 형성된다.
그 후에, 본 개시 내용의 일부 실시예에 따라, 도 1e에 도시된 바와 같이, 마스크층(110)이 제거되고, 시드층(108)의 일부를 제거하기 위하여 에칭 공정이 수행된다. 에칭 공정 동안, 도전성 구조체(114)는 마스크로서 사용된다. 그 결과, 도전성 구조체(114) 및 남아 있는 시드층(108)은 조합하여 관통 InFO 비아(through InFO via; TIV)(116)라 하며, 관통 비아(116)라고도 한다. 일부 실시예에서, 도전성 구조체(114) 및 시드층(108)은 동일한 재료로 이루어지고, 따라서 그 사이에는 구별 가능한 계면이 없다.
그 후에, 본 개시 내용의 일부 실시예에 따라, 도 1f에 도시된 바와 같이, 반도체 다이(120)가 접착층(122)을 통해 베이스층(106) 위에 형성된다. 도전성 구조체(114)의 높이는 반도체 다이(120)의 높이보다 더 높다. 도전성 구조체(114)의 상면은 반도체 다이(120)의 상면보다 더 높다.
일부 실시예에서, 접착층(122)은 다이 부착 필름(die attach film; DAF)이다. 반도체 다이(120)는 반도체 기판(124), 유전층(126), 도전성 패드(128), 패시베이션층(130) 및 커넥터(132)를 포함한다. 도전성 패드(128)는 유전층(126) 내에 형성되고, 커넥터(132)는 패시베이션층(130) 내에 형성된다. 커넥터(132)는 도전성 패드(128)에 전기적으로 연결된다.
다른 소자 요소가 반도체 다이(120) 내에 형성될 수 있다. 소자 요소는 트랜지스터(예를 들어, MOSFET(metal oxide semiconductor field effect transistor), CMOS(complementary metal oxide semiconductor) 트랜지스터, BJT(bipolar junction transistor), 고전압 트랜지스터, 고주파수 트랜지스터, PFET/NFET(p-channel 및/또는 n-channel field effect transistor) 등), 다이오드 및/또는 다른 적용 가능한 요소를 포함한다. 부착, 에칭, 주입(implantation), 포토리소그라피, 어닐링(annealing) 및/또는 다른 적용 가능한 공정과 같은 다양한 공정이 소자 요소를 형성하기 위하여 수행된다.
도 1g에 도시된 바와 같이, 제1 절연층(136a)이 도전성 구조체(114) 상에 동시에 형성된다. 제1 절연층(136a)은 도전성 구조체(114)를 둘러싼다. 다른 말로 하면, 도전성 구조체(114)와 시드층(108)은 제1 절연층(136a)에 의해 둘러싸인다.
도전성 구조체(114)는 금속 재료를 포함하고, 제1 절연층(136a)은 이 금속 재료의 금속 원소와 동일한 금속 원소를 포함한다. 일부 실시예에서, 제1 절연층(136a)은 자연(native) 산화물층이다. 일부 실시예에서, 도전성 구조체(114)는 구리(Cu)를 포함하고, 제1 절연층(136a)은 산화구리(II)(CuO) 및 산화구리(I)(Cu2O)을 포함한다.
제1 절연층(136a)이 도전성 구조체(114)와 패키지층(도 1i에 도시된 패키지층(140)과 같이 나중에 형성됨) 사이에 형성된다는 것이 주목되어야 한다. 그러나, 제1 절연층(136a)과 패키지층 사이의 박리가 가열 공정과 같은 후속 공정 동안 발생할 수 있다. 예를 들어, 가열 동작 동안, 열이 스트레스를 야기할 수 있고, 이는 패키지층의 박리를 초래할 수 있다.
일부 실시예에서, 본 개시 내용의 일부 실시예에 따라, 플라즈마 공정(11)이 도전성 구조체(114)에 수행되어, 제1 절연층의 외부 부분을 제2 절연층(136b)으로 변환한다. 예를 들어, 도 1ha에 도시된 바와 같이, 제2 절연층(136b)은 도전성 구조체(114) 위에 형성된다. 플라즈마 공정(11)을 수행하기 전의 제1 절연층(136a)의 표면과 비교하여, 플라즈마 공정(11)이 수행된 후에 제2 절연층(136b) 상의 거칠어진 표면이 획득된다. 제1 절연층(136a')은 제1 두께(T1)를 가지고, 제2 절연층(136b)은 제2 두께(T2)를 가진다. 일부 실시예에서, 제2 두께(T2)에 대한 제1 두께(T1)의 비(T1/T2)는 대략 1/1에서 대략 1/0.2까지의 범위에 있다.
플라즈마 공정(11) 후에, 절연층(136)은 제1 절연층(136a')과 제2 절연층(136b)을 포함한다. 제1 절연층(136a')은 제2 절연층(136b)보다 도전성 구조체(114)에 더 가깝다. 다른 말로 하면, 제1 절연층(136a')은 도전성 구조체(114)와 직접 접촉하여 형성되고, 제2 절연층(136b)은 패키지층(140)(도 1i에 도시됨)과 직접 접촉하여 형성된다. 도 1ha에 도시된 바와 같이, 절연층(136) 내의 점선은 2개의 층을 개략적으로 정의하는데 사용된다. 다른 말로 하면, 절연층(136)은 도전성 구조체(114)와 접촉하는 내면 근처의 제2 위치에서보다 절연층(136)의 외면 근처의 제1 위치에 더 많은 1가 금속 산화물을 포함한다. "외면 근처(near an outer surface)"라는 설명은 제2 절연층(136b)의 두께 범위 내에 있다는 것을 의미하고, "내면 근처(near an inner surface)"라는 설명은 제1 절연층(136a') 내의 두께 내에 있다는 것을 의미한다.
일부 실시예에서, 2개의 층(136a, 136b) 내의 1가 금속 산화물 및 2가 금속 산화물의 조성은 상이하다. 예를 들어, 1가 금속 산화물과 2가 금속 산화물의 중량비는 제1 절연층(136a')과 제2 절연층(136b)에서 상이하다. 제2 층(136b)을 형성함으로써 박리 문제를 방지하기 의하여 접착이 개선될 수 있다.
도전성 구조체(114)는 금속 재료를 포함하고, 제1 절연층(136a')과 제2 절연층(136b)은 이 금속 재료의 금속 원소와 동일한 금속 원소를 포함한다. 더욱 구체적으로, 제1 절연층(136a') 및 제2 절연층(136b)은 모두 1가 금속 산화물과 2가 금속 산화물을 포함하고, 제2 절연층(136b)은 더 높은 비의 1가 금속 산화물을 포함한다. 예를 들어, 도전성 구조체(114)는 구리(Cu)를 포함하고, 제1 절연층(136a')과 제2 절연층(136b)은 산화구리(II)(CuO)와 산화구리(I)(Cu2O)을 포함한다.
제2 절연층(136b) 내의 1가 금속 산화물의 중량비가 제1 절연층(136a') 내의 1가 금속 산화물의 중량비보다 더 크다는 것이 주목되어야 한다. 일부 실시예에서, 도전성 구조체(114)는 구리(Cu)를 포함하고, 제2 절연층(136b) 내의 산화구리(I)(Cu2O)의 중량비는 제1 절연층(136a') 내의 산화구리(I)(Cu2O)의 중량비보다 더 크다. 일부 실시예에서, 제2 절연층(136b) 내의 산화구리(I)(Cu2O)의 중량비는 대략 30%에서 대략 60%까지의 범위 내에 있다. 일부 실시예에서, 제1 절연층(136a') 내의 산화구리(I)(Cu2O)의 중량비는 대략 20%에서 대략 28%까지의 범위 내에 있다. 일부 실시예에서, 제2 절연층(136b) 내의 산화구리(I)(Cu2O)의 중량비는 제1 절연층(136a') 내의 산화구리(I)(Cu2O)의 중량비의 대략 1.5 내지 3배이다.
일부 다른 실시예에서, 제2 절연층(136b) 내의 산화구리(I)(Cu2O)와 산화구리(II)(CuO)의 중량비는 제2 절연층(136b)의 내면에서 외면으로 점진적으로 증가한다. 내면은 제1 절연층(136a')과 제2 절연층(136b) 사이의 계면이다. 외면은 제2 절연층(136b)과 패키지층(140) 사이의 계면이다. 일부 실시예에서, 산화구리(I)(Cu2O)와 산화구리(II)(CuO)의 중량비 제1 절연층(136a')에서 실질적으로 일정하다.
또한, 제2 절연층(136b)의 표면 거칠기는 제1 절연층(136a')의 표면 거칠기보다 더 크다. 높은 거칠기는 접촉 면적을 증가시키고, 따라서 접착 강도를 개선한다. 도전성 구조체(114)와 패키지층(140) 사이의 접착은 도전성 구조체(114)의 표면을 처리함으로써 개선된다.
다른 말로 하면, 1가 금속 산화물은, 2가 금속 산화물과 비교하여, 도전성 구조체(114)와 이어서 형성된 패키지층(140) 사이의 더 나은 접합 특성을 제공한다.
일부 실시예에서, 플라즈마 공정(11)은 프리-클리닝(pre-cleaning) 공정 및 메인 플라즈마 공정을 수행하는 것을 포함한다. 프리-클리닝 공정은 도전성 구조체(114)의 표면을 세정하고 일부 오염물을 제거하도록 구성된다. 오염물이 제거되지 않으면, 이는 도전성 구조체(114)와 패키지층(140) 사이의 접착을 방해하고 감소시킨다. 메인 플라즈마 공정은 제1 절연층(136a)의 컴포넌트를 변화시키도록 구성된다. 따라서, 제1 절연층(136a') 위에 형성된 제2 절연층(136b)이 획득된다.
일부 실시예에서, 클리닝 공정은 대략 200 sccm에서 대략 600 sccm까지의 범위의 유량의 질소(N2) 가스를 이용하는 것을 포함한다. 일부 실시예에서, 클리닝 공정은 대략 20 Pa에서 대략 70 Pa까지의 범위의 압력에서 수행된다. 일부 실시예에서, 클리닝 공정은 대략 10초 내지 대략 70초까지의 범위의 기간 동안 수행된다. 프리-클리닝 공정이 전술한 범위 내의 기간 동안 수행될 때, 오염물은 완전히 제거된다.
일부 실시예에서, 메인 플라즈마 공정은 대략 100 sccm에서 대략 300 sccm까지의 범위의 유량의 산소(O2) 가스를 이용하는 것을 포함한다. 또한, 산소(O2) 가스에 더하여, 메인 플라즈마 공정은 대략 100 sccm에서 대략 300 sccm까지의 범위의 유량의 아르곤(Ar) 가스를 이용하는 것을 포함한다. 또한, 아르곤(Ar) 가스는 표면 거칠기를 증가시키는데 사용된다. 일부 실시예에서, 메인 플라즈마 공정은 대략 20 Pa에서 대략 40 Pa까지의 범위의 압력에서 수행된다. 일부 실시예에서, 메인 플라즈마 공정은 대략 5초 내지 대략 50초까지의 범위의 기간 동안 수행된다. 메인 플라즈마 공정이 전술한 범위 내의 기간 동안 수행될 때, 제2 절연층(136b) 내의 1가 금속 산화물의 비가 증가된다.
일부 다른 실시예에서, 습식 공정(13)이 도전성 구조체(114)에 수행되어, 절연층(136a)의 외부 부분을 제2 절연층(136b)으로 변환한다. 본 개시 내용의 일부 실시예에 따라, 도 1hb에 도시된 바와 같이, 제2 절연층(136b)이 도전성 구조체(114) 위에 형성된다.
일부 실시예에서, 습식 공정(13)은 화학 배스(chemical bath)(20) 내에 기판(102)을 배치하는 것을 포함한다. 화학 배스(20)는 입력부(202)와 출력부(204)를 포함한다. 입력부(202)는 화학 용액을 위한 입력부를 제공하는데 사용되고, 출력부(204)는 화학 용액의 출력부를 제공하는데 사용된다. 프로펠러(206)는 화학 용액을 교반하여 순환시키는데 사용되고, 따라서 기판(102)은 화학 용액과 균일하게 반응될 수 있다.
습식 공정(13) 후에, 제1 절연층(136a')과 제2 절연층(136b)을 포함하는 절연층(136)이 획득된다. 제1 절연층(136a')은 1가 금속 산화물과 2가 금속 산화물을 포함한다. 제2 절연층(136b)은 1가 금속 산화물과 2가 금속 산화물을 포함한다. 일부 실시예에서, 1가 금속 산화물은 산화구리(I)(Cu2O)이고, 2가 금속 산화물은 산화구리(II)(CuO) 또는 수산화구리(Cu(OH)2)다.
제2 절연층(136b) 내의 1가 금속 산화물의 중량비는 제1 절연층(136a') 내의 1가 금속 산화물의 중량비보다 더 크다는 것이 주목되어야 한다. 일부 실시예에서, 제2 절연층(136b) 내의 1가 금속 산화물의 비는 대략 30 wt%에서 60 wt%까지의 범위에 있다. 일부 실시예에서, 제1 절연층(136a') 내의 1가 금속 산화물의 비는 대략 20 wt%에서 28 wt%까지의 범위에 있다.
일부 실시예에서, 화학 용액은 과산화수소(H2O2) 용액을 포함한다. 일부 실시예에서, 과산화수소(H2O2) 용액은 대략 20 wt%에서 60 wt%까지의 범위의 농도를 갖는다. 일부 실시예에서, 화학 배스(20)는 실온에서 수행된다. 일부 실시예에서, 화학 배스(20)는 대략 20도에서 대략 40도까지의 범위의 온도에서 수행된다.
습식 공정(13) 후에, 선택적인 클리닝 공정이 절연층(136)에 수행된다. 클리닝 공정은 화학 배스(20)로부터 유래할 수 있는 일부 오염물을 제거하는데 사용된다. 오염물이 절연층(136) 위에 남아 있다면, 오염물은 패키지층(140)의 접착을 방해할 수 있다. 일부 실시예에서, 클리닝 공정은 대략 200 sccm에서 대략 700 sccm까지 범위의 유량의 질소(N2)를 포함한다.
과산화수소(H2O2) 용액은 준비하기 쉽고 화학 배스(20)는 화학 배스(20)를 가열하지 않고 실온에서 수행될 수 있다는 것이 주목되어야 한다. 따라서, 습식 공정(13)을 수행하기 위한 비용은 상대적으로 낮다. 습식 공정(13)은 대량 생산에 사용될 수 있다.
전술한 바와 같이, 플라즈마 공정(11)을 수행하거나 습식 공정(13)을 수행함으로써 도전성 구조체(114)와 패키지층(140) 사이의 접착이 개선된다. 박리 문제가 방지된다. 따라서, 패키지 구조체(100)의 신뢰성과 성능이 더 개선된다.
그 후에, 본 개시 내용의 일부 실시예에 따라, 도 1i에 도시된 바와 같이 패키지층(140)이 반도체 다이(120)와 절연층(136) 위에 형성된다. 일부 실시예에서, 패키지층(140)은 반도체 다이(120)를 완전히 캡슐화하여 덮는다. 패키지층(140)의 상면은 도전성 구조체(114)의 상면과 반도체 다이(120)의 상면보다 더 높다.
일부 실시예에서, 패키지층(140)은 액체 에폭시, 변형 가능한 겔, 실리콘 고무 또는 이와 유사한 것과 같은 몰딩 화합물로 이루어진다. 일부 실시예에서, 몰딩 화합물은 베이스층(106), 반도체 다이(120) 및 절연층(136) 위에 제공되고, 따라서 열 공정이 몰딩 화합물을 경화하기 위하여 수행된다.
패키지층(140)이 형성된 후에, 본 개시 내용의 일부 실시예에 따라, 도 1j에 도시된 바와 같이, 반도체 다이(120)와 관통 InFO 비아(TIV)(116)를 노출시키기 위하여 평탄화 공정이 수행된다. 평탄화 공정 후에 반도체 다이(120)의 상면은 도전성 구조체(114)와 레벨이 실질적으로 동일하다. 일부 실시예에서, 평탄화 공정은 그라인딩(grinding) 공정, CMP(chemical mechanical polishing) 공정, 에칭 공정, 다른 적용 가능한 공정 또는 이들의 조합을 포함한다.
평탄화 공정 후에, 본 개시 내용의 일부 실시예에 따라, 도 1k에 도시된 바와 같이, 재분배(redistribution) 구조체(146)가 패키지층(140) 위에 형성된다. 재분배 구조체(146)는 패시베이션층(142) 내에 형성된 재분배 라인(redistribution lines; RDL)(144)을 포함한다. RDL(144)은 반도체 다이(120) 및 관통 InFO 비아(TIV)(116)에 전기적으로 연결된다.
일부 실시예에서, 재분배 라인(RDL)(144)은 구리(Cu), 구리 합금, 알루미늄(Al), 알루미늄 합금, 텅스텐(W), 텅스텐 합금, 티타늄(Ti), 티타늄 합금, 탄탈룸(Ta) 또는 탄탈룸 합금과 같은 금속으로 이루어진다. 일부 실시예에서, RDL(144)은 도금, 무전해 도금, 스퍼터링 또는 CVD(chemical vapor deposition)에 의해 형성된다. 일부 실시예에서, 패시베이션층(142)은 PBO(polybenzoxazole), BCB(benzocyclobutene), 실리콘, 아크릴레이트, 실록산 또는 이들의 조합으로 이루어진다. 일부 다른 실시예에서, 패시베이션층(142)은 실리콘 산화물, 도핑되지 않은 실리케이트 유리, 실리콘 산화질화물, SR(solder resist), 실리콘 질화물, HDMS(hexamethyldisilazane)와 같은 무기 재료로 이루어진다.
그 후에, 전기 커넥터(148)가 재분배 구조체(146) 위에 형성된다. 일부 실시예에서, 전기 커넥터(148)는 솔더 볼, 금속 필라(pillar), 다른 적용 가능한 커넥터를 포함한다. 일부 실시예에서, UBM(under bump metallurgy) 층(미도시)이 전기 커넥터(148) 아래에 형성된다.
그 후에, 본 개시 내용의 일부 실시예에 따라, 도 1l에 도시된 바와 같이, 기판(102)과 접착층(104)이 제거되고, 도 1k의 구조가 뒤집어져 캐리어(152)에 부착된다. 그 결과, 베이스층(106)이 위로 바라보고 노출된다. 캐리어(152)는 감광성 또는 감열성인 테이프를 포함하며, 전기 커넥터(148)로부터 쉽게 분리된다.
그 후에, 본 개시 내용의 일부 실시예에 따라, 도 1m에 도시된 바와 같이, 베이스층(106)의 일부가 제거되어 개구(154)를 형성한다. 일부 실시예에서, 시드층(108)의 일부가 제거되고, 시드층(108)이 노출된다. 일부 다른 실시예에서, 시드층(108)은 제거되지 않거나 완전히 제거된다. 일부 다른 실시예에서, 개구(154)는 레이저 드릴링 공정, 에칭 공정 또는 다른 적용 가능한 공정에 의해 형성된다.
개구(154)가 형성된 후에, 본 개시 내용의 일부 실시예에 따라, 도 1n에 도시된 바와 같이, 전기 커넥터(158)가 개구(154) 내로 충전된다. 그 후에, 상부 패키지(160)가 전기 커넥터(158)에 접합된다. 상부 패키지(160)는 패키지 기판(162)과 반도체 다이(164)를 포함한다. 일부 실시예에서, 반도체 다이(164)는 SRAM(Random Access Memory) 다이, DRAM(Dynamic Random Access Memory) 다이 또는 이와 유사한 것과 같은 메모리 다이를 포함한다.
그 후에, 반도체 구조체(100)는 다른 구조체 또는 소자를 형성하기 위하여 다른 공정을 계속 받을 수 있다. 그 후에, 도 1n에 도시된 바와 같은 구조체를 칩 패키지로 분리하기 위하여 다이싱(dicing) 공정이 수행된다.
도 2a는 본 개시 내용의 일부 실시예에 따라 플라즈마 공정(11) 또는 습식 공정(13) 전의 도전성 구조체(114)를 나타내는 상면도를 도시한다. 도 2a에 도시된 바와 같이, 제1 절연층(136a)은 도전성 구조체(114)를 둘러싸고, 도전성 구조체(114)의 위에서 본 형상은 원이다.
도 2b는 본 개시 내용의 일부 실시예에 따라 플라즈마 공정(11) 또는 습식 공정(13) 후의 도전성 구조체(114)를 나타내는 상면도를 도시한다. 플라즈마 공정(11) 또는 습식 공정(13)을 수행한 후에, 제1 절연층(136a') 위에 형성된 제2 절연층(136b)이 획득된다. 제2 절연층(136b)은 패키지층(140)과 직접 접촉할 것이다. 제2 절연층(136b)의 표면 거칠기는 도전성 구조체(114)와 패키지층(140) 사이의 접합을 개선하기 위하여 증가된다.
전술한 바와 같이, 절연층(136)은 도전성 구조체(114)와 접촉하는 내면 근처의 제2 위치에서보다 절연층(136)의 외면 근처의 제1 위치에 더 많은 1가 금속 산화물을 포함한다. "외면 근처(near an outer surface)"라는 설명은 제2 절연층(136b)의 두께 범위 내에 있다는 것을 의미하고, "내면 근처(near an inner surface)"라는 설명은 제1 절연층(136a') 내의 두께 내에 있다는 것을 의미한다.
도 3a는 본 개시 내용의 일부 실시예에 따라 도전성 구조체(114)를 나타내는 상면도를 도시한다. 도 3a에 도시된 바와 같이, 제1 절연층(136a)은 도전성 구조체(114)를 둘러싸고, 도전성 구조체(114)의 위에서 본 형상은 직사각형이다.
도 3b는 본 개시 내용의 일부 실시예에 따라 플라즈마 공정(11) 또는 습식 공정(13) 후의 도전성 구조체(114)를 나타내는 상면도를 도시한다. 제2 절연층(136b) 내의 1가 금속 산화물의 중량비는 제1 절연층(136a') 내의 1가 금속 산화물의 중량비보다 더 크다. 제2 절연층(136b)의 비를 변경함으로써 접합 강도가 개선된다. 그 결과, 패키지 구조체(100)의 신뢰성과 성능이 더 개선된다.
패키지 구조체 및 이를 형성하는 방법을 위한 실시예가 제공된다. 반도체 다이는 기판 위에 형성되고, 패키지층은 반도체 다이를 덮는다. 도전성 구조체는 패키지층 내에 형성되고, 절연층은 도전성 구조체와 패키지층 사이에 형성된다. 플라즈마 공정 또는 습식 공정이 도전성 구조체에 수행되어 제1 절연층과 제2 절연층을 포함하는 절연층을 형성한다. 제2 절연층은 패키지층과 직접 접촉하고 접착을 개선하기 위하여 더 큰 표면 거칠기를 갖는다. 접착이 개선될 때, 박리 문제가 방지된다. 따라서, 패키지 구조체의 성능도 개선된다.
일부 실시예에서, 패키지 구조체가 제공된다. 패키지 구조체는 기판과 기판 위에 형성된 반도체 다이를 포함한다. 또한, 패키지 구조체는 반도체 다이를 덮는 패키지층과 패키지층 내에 형성된 도전성 구조체를 포함한다. 패키지 구조체는 도전성 구조체 상에 형성된 제1 절연층을 포함하고, 제1 절연층은 1가 금속 산화물을 포함한다. 패키지 구조체는 제1 절연층과 패키지층 사이에 형성된 제2 절연층을 포함한다. 제2 절연층은 1가 금속 산화물을 포함하고, 제2 절연층 내의 1가 금속 산화물의 중량비는 제1 절연층 내의 1가 금속 산화물의 중량비보다 더 크다.
일부 실시예에서, 패키지 구조체가 제공된다. 패키지 구조체는 기판과 기판 위에 형성된 반도체 다이를 포함한다. 또한, 패키지 구조체는 반도체 다이에 인접한 패키지층과 패키지층 내에 형성된 도전성 구조체를 포함한다. 패키지 구조체는 도전성 구조체 상에 형성된 절연층을 더 포함한다. 절연층은 도전성 구조체와 접촉하는 내면 근처의 제2 위치에서보다 절연층의 외면 근처의 제1 위치에서 더 많은 1가 금속 산화물을 포함한다.
일부 실시예에서, 패키지 구조체 형성 방법이 제공된다. 방법은, 기판 위에 도전성 구조체를 형성하는 단계와, 기판 위에 반도체 다이를 형성하는 단계를 포함한다. 반도체 다이는 도전성 구조체에 의해 둘러싸인다. 방법은 도전성 구조체에 습식 공정 또는 플라즈마 공정을 수행하여 도전성 구조체 위에 절연층을 형성하는 단계를 더 포함한다. 절연층은 제1 절연층 위에 제2 절연층을 포함하며, 제1 절연층과 제2 절연층은 모두 1가 금속 산화물을 포함한다. 제2 절연층 내의 1가 금속 산화물의 중량비는 제1 절연층 내의 1가 금속 산화물의 중량비보다 더 크다. 또한, 방법은 반도체 다이 및 제2 절연층 위에 패키지층을 형성하는 단계를 포함한다.
전술한 바는 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 개시 내용의 양태를 더 잘 이해할 수 있도록 여러 실시예들의 특징들을 약술한다. 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자는 여기에서 소개된 실시예들의 동일한 목적을 수행하고 동일한 이점을 획득하기 위하여 다른 공정 및 구조를 설계하거나 수정하기 위한 기본으로서 본 개시 내용을 용이하게 이용할 수 있다. 또한, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자는 이러한 균등한 구조가 본 개시 내용의 기술적 사상 및 범위로부터 벗어나지 않고, 본 개시 내용의 기술적 사상 및 범위를 벗어나지 않으면서 다양한 변화, 대체 및 변경을 할 수 있다는 것을 이해하여야 한다.

Claims (10)

  1. 패키지 구조체(package structure) 형성 방법에 있어서,
    기판 위에 도전성 구조체를 형성하는 단계;
    상기 기판 위에 반도체 다이를 형성하는 단계 - 상기 반도체 다이는 상기 도전성 구조체에 의해 둘러싸임 -;
    상기 도전성 구조체 위에 절연층을 형성하기 위해 상기 도전성 구조체 위에 습식 공정을 수행하는 단계 - 상기 절연층은 제1 절연층 위의 제2 절연층을 포함하고, 상기 제1 절연층 및 상기 제2 절연층은 둘 다 1가 금속 산화물을 포함하며, 상기 제2 절연층 내의 상기 1가 금속 산화물의 중량비는 상기 제1 절연층 내의 상기 1가 금속 산화물의 중량비보다 큼 -; 및
    상기 제2 절연층 및 상기 반도체 다이 위에 패키지층을 형성하는 단계
    를 포함하는, 패키지 구조체 형성 방법.
  2. 제1항에 있어서,
    상기 도전성 구조체 상에 상기 습식 공정을 수행하는 단계는:
    화학 배스(chemical bath) 내에 상기 기판을 배치하는 단계 - 상기 화학 배스는 과산화수소(H2O2) 용액을 포함함 - 를 포함하는 것인, 패키지 구조체 형성 방법.
  3. 제2항에 있어서,
    상기 과산화수소(H2O2) 용액은 20 wt%에서 60 wt%까지의 범위의 농도를 갖는 것인, 패키지 구조체 형성 방법.
  4. 제1항에 있어서,
    상기 도전성 구조체 상에 상기 습식 공정을 수행한 후, 상기 도전성 구조체 상에 클리닝 공정을 수행하는 단계 - 상기 클리닝 공정은 질소(N2) 가스를 이용하는 것을 포함함 - 를 더 포함하는 것인, 패키지 구조체 형성 방법.
  5. 제1항에 있어서,
    상기 패키지층 위에 형성되는 재분배층을 형성하는 단계 - 상기 재분배층은 상기 반도체 다이에 전기적으로 연결됨 - 을 더 포함하는 것인, 패키지 구조체 형성 방법.
  6. 기판 상에 도전성 구조체를 형성하는 단계;
    상기 도전성 구조체 상에 산화물층을 형성하는 단계 - 상기 산화물층은 1가 금속 산화물 및 2가 금속 산화물 둘 다를 포함하고, 1가 금속 산화물 대 2가 금속 산화물의 제1 중량비를 가짐 -; 및
    상기 산화물층의 일부분을 제2 산화물층으로 변환하는 단계 - 상기 제2 산화물층은 상기 제1 중량비보다 큰 1가 금속 산화물 대 2가 금속 산화물의 중량비를 가짐 -
    를 포함하고,
    상기 산화물층의 일부분을 제2 산화물층으로 변환하는 단계는 상기 산화물층을 습식 공정에 노출시키는 것을 포함하는, 방법.
  7. 제6항에 있어서,
    상기 습식 공정은 과산화수소 배스를 포함하는 것인, 방법.
  8. 제6항에 있어서,
    패키지층 내에 상기 도전성 구조체를 캡슐화하고, 상기 도전성 구조체의 상면을 노출시키기 위해 상기 산화물층, 상기 제2 산화물층 및 상기 패키지층의 일부분을 제거하는 단계를 더 포함하는, 방법.
  9. 제6항에 있어서,
    상기 도전성 구조체는 하향식 보기(top down view)로 보았을 때 원형 형상을 갖는 것인, 방법.
  10. 패키지 구조체 형성 방법에 있어서,
    기판 상에 도전성 구조체를 성막하는 단계;
    상기 도전성 구조체 상에 자연 산화물이 형성되도록 하는 단계;
    상기 자연 산화물의 일부분을 제2 산화물층으로 변환하는 단계; 및
    패키지 재료 내에 상기 도전성 구조체를 캡슐화하는 단계 - 상기 자연 산화물 및 상기 제2 산화물층은 상기 도전성 구조체 및 상기 패키지 재료 사이에 개재됨 -
    를 포함하고,
    상기 자연 산화물의 일부분을 제2 산화물층으로 변환하는 단계는 상기 자연 산화물을 습식 공정에 노출시키는 것을 포함하는 것인, 패키지 구조체 형성 방법.
KR1020180070347A 2015-12-16 2018-06-19 패키지 구조체 및 이의 형성 방법 KR102026568B1 (ko)

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US10224293B2 (en) 2019-03-05
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US9508664B1 (en) 2016-11-29
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