CN107039381A - 半导体器件结构及其形成方法 - Google Patents

半导体器件结构及其形成方法 Download PDF

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Publication number
CN107039381A
CN107039381A CN201611074839.5A CN201611074839A CN107039381A CN 107039381 A CN107039381 A CN 107039381A CN 201611074839 A CN201611074839 A CN 201611074839A CN 107039381 A CN107039381 A CN 107039381A
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metal
oxide
layer
conductive
dielectric layer
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CN201611074839.5A
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CN107039381B (zh
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林俊成
余振华
卢思维
齐彦尧
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体器件结构。半导体器件结构包括衬底。半导体器件结构包括位于衬底上方的导电结构。半导体器件结构包括位于导电结构上方的多个第一金属氧化物纤维。半导体器件结构包括位于衬底上方并且覆盖导电结构和多个第一金属氧化物纤维的介电层。介电层填充多个第一金属氧化物纤维之间的间隙。本发明还提供了半导体器件结构的形成方法。

Description

半导体器件结构及其形成方法
技术领域
本发明的实施例一般地涉及半导体技术领域，更具体地，涉及半导体器件结构及其形成方法。
背景技术
半导体器件用于诸如个人电脑、手机、数码相机和其它电子设备的各种电子应用中。通常通过以下步骤来制造半导体器件：在半导体衬底上方相继沉积绝缘或介电层、导电层和半导体层；以及使用光刻来图案化该多个材料层，以形成电路组件和元件。
用于半导体器件中的提高性能的一个重要的驱动力是电路的更高的集成度。这通过使给定芯片上的器件尺寸微型化或缩小来实现。公差在能够缩小芯片的尺寸上起着重要作用。
然而，虽然用于形成半导体器件的现有的制造工艺对于它们的预期目的通常已经足够，但是随着器件持续按比例缩小，它们不能在所有方面都已完全令人满意。
发明内容
根据本发明的一方面，提供了一种半导体器件结构，包括：衬底；导电结构，位于所述衬底上方；多个第一金属氧化物纤维，位于所述导电结构上方；以及介电层，位于所述衬底上方并且覆盖所述导电结构和所述多个第一金属氧化物纤维，其中，所述介电层填充所述多个第一金属氧化物纤维之间的间隙。
根据本发明的另一方面，提供了一种半导体器件结构，包括：衬底；第一导电结构，位于所述衬底上方；金属氧化物层，位于所述第一导电结构上方；多个第一金属氧化物纤维，连接至所述金属氧化物层，其中，所述多个第一金属氧化物纤维和所述金属氧化物层由相同的材料制成；以及介电层，位于所述衬底上方并且覆盖所述第一导电结构、所述金属氧化物层和所述多个第一金属氧化物纤维。
根据本发明的又一方面，提供了一种用于形成半导体器件结构的方法，包括：在衬底上方形成导电结构；在所述导电结构上方形成多个第一金属氧化物纤维；以及在所述衬底上方形成介电层以覆盖所述导电结构和所述多个第一金属氧化物纤维，其中，所述介电层填充所述所述第一金属氧化物纤维之间的间隙。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明的各个实施例。应该强调的是，根据工业中的标准实践，各个部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意地增加或减少。
图1A至图1H是根据一些实施例的用于形成半导体器件结构的工艺的各个阶段的截面图。
图2A至图2F是根据一些实施例的用于形成半导体器件结构的工艺的各个阶段的截面图。
图3A至图3O是根据一些实施例的用于形成半导体器件结构的工艺的各个阶段的截面图。
图4是根据本发明的一些实施例的半导体器件结构的截面图。
具体实施方式
以下公开内容提供了多种不同实施例或实例，用于实现所提供主题的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。应该理解，可以在方法之前、期间和之后提供附加的操作，并且对于方法的其他实施例，可以替换或删除描述的一些操作。
图1A至图1H是根据一些实施例的用于形成半导体器件结构100的工艺的各个阶段的截面图。如图1A所示，根据一些实施例，提供衬底110。根据一些实施例，衬底110包括半导体衬底。根据一些实施例，半导体衬底包括半导体晶圆(诸如硅晶圆)或芯片。可选地或者额外地，衬底110可以包括元素半导体材料、化合物半导体材料和/或合金半导体材料。
元素半导体材料的实例可以是，但不限于，晶体硅、多晶硅、非晶硅、锗、和/或金刚石。化合物半导体材料的实例可以是，但不限于，碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟。合金半导体材料的实例可以是，但不限于，SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP。
如图1A所示，根据一些实施例，介电层120形成在衬底110上方。根据一些实施例，介电层120包括聚合物(如，聚酰亚胺)、氧化物(如，SiO2)、硼硅酸盐玻璃(BPSG)、旋涂玻璃(SOG)、未掺杂的硅酸盐玻璃(USG)、氟化硅酸盐玻璃(FSG)、高密度等离子体(HDP)氧化物、或等离子体增强的TEOS(PETEOS)。
根据一些实施例，介电层120包括由诸如低介电常数或超低介电常数(ELK)材料的多种介电材料制成的多层。根据一些实施例，通过旋涂、化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、或其他适用的工艺来形成介电层120。
如图1A所示，根据一些实施例，导电结构130形成在介电层120上方。根据一些实施例，导电结构130包括布线层或多个布线层，诸如再分布层或多个再分布层。为了简洁，图1A仅示出了一个布线层，但本发明不限于此。在一些其他实施例中，导电结构130包括导电通孔结构或其他合适的导电结构。
根据一些实施例，导电结构130电连接至位于衬底110上方或中的器件(未示出)。根据一些实施例，导电结构130具有顶面132、侧壁134、和底面136。根据一些实施例，顶面132背离衬底110。根据一些实施例，侧壁134围绕顶面132和底面136。
导电结构130包括铜(Cu)或其他合适的导电材料，其能够被氧化为纤维状的金属氧化物。根据一些实施例，使用镀敷工艺(或沉积工艺)、光刻工艺和蚀刻工艺来形成导电结构130。根据一些实施例，镀敷工艺包括电镀工艺或无电镀工艺。根据一些实施例，沉积工艺包括物理汽相沉积工艺和化学汽相沉积工艺。在一些实施例中，在导电结构130上方执行表面清洗工艺以去除导电结构上方的原生的氧化物层(未示出)。
如图1B所示，根据一些实施例，在导电结构130上方形成金属氧化物纤维140。根据一些实施例，金属氧化物纤维140形成在导电结构130的顶面132和侧壁134上方。根据一些实施例，金属氧化物纤维140中的每一个都具有直接连接至导电结构130的端部142。根据一些实施例，金属氧化物纤维140与导电结构130直接接触。
在一些实施例中，两个邻近的金属氧化物纤维140彼此直接接触。根据一些实施例，随机地形成金属氧化物纤维140。根据一些实施例，导电结构130包括金属材料(如，铜)，并且金属氧化物纤维140由金属材料的氧化物制成。根据一些实施例，金属材料的氧化物包括氧化铜。
根据一些实施例，金属氧化物纤维140的形成包括氧化导电结构130的表面部分。根据一些实施例，导电结构130的表面部分邻近顶面132和侧壁134。根据一些实施例，表面部分的氧化工艺包括在导电结构130的表面部分上(或在顶面132上和侧壁134上)执行热氧化工艺或化学氧化工艺。
根据一些实施例，化学氧化工艺使用氧化溶液(如，H2O2)。根据一些实施例，化学氧化工艺包括将导电结构130浸没在氧化溶液中。根据一些实施例，在含氧环境中执行热氧化工艺。
根据一些实施例，在约100℃至约300℃的范围内的处理温度下执行热氧化工艺。如果处理温度低于100℃，则可以基本不形成金属氧化物纤维140。如果处理温度高于300℃，则可以不利地影响形成在衬底10中或上方的器件。
在一些实施例中，导电结构130的底面136未暴露于氧化工艺。因此，根据一些实施例，金属氧化物纤维140未形成在导电结构130与介电层120之间。
如图1C所示，根据一些实施例，在介电层120上方形成介电层150。根据一些实施例，介电层150覆盖导电结构130和金属氧化物纤维140。根据一些实施例，介电层150填充金属氧化物纤维140之间的间隙G1。
根据一些实施例，介电层150围绕金属氧化物纤维140中的每一个。根据一些实施例，金属氧化物纤维140穿过(penetrate into，又称进入)介电层150。根据一些实施例，金属氧化物纤维140嵌在介电层150中。根据一些实施例，金属氧化物纤维140与介电层150直接接触。
由于从导电结构130形成金属氧化物纤维140，所以金属氧化物纤维140与导电结构130之间的附着力大于介电层150与导电结构130之间的附着力。金属氧化物纤维140与介电层150之间的边界区较大，这改善了金属氧化物纤维140与介电层150之间的附着性。由于金属氧化物纤维140连接在导电结构130与介电层150之间，所以金属氧化物纤维140能够防止导电结构130与介电层150之间的分层。因此，提高了半导体器件结构100的产量和可靠性。
根据一些实施例，金属氧化物纤维140具有的平均长度大于金属氧化物纤维140的平均直径。根据一些实施例，金属氧化物纤维140的平均长度在约20nm至约500nm的范围内。如果金属氧化物纤维140的平均长度小于20nm，则金属氧化物纤维140与介电层150之间的边界区会没有大到足以改善金属氧化物纤维140与介电层150之间的附着。如果金属氧化物纤维140的平均长度大于500nm，则金属氧化物纤维140易于损坏。
根据一些实施例，金属氧化物纤维140的平均直径在约1nm至约90nm的范围内。如果金属氧化物纤维140的平均直径小于1nm，则金属氧化物纤维140易于损坏。如果金属氧化物纤维140的平均直径大于90nm，则金属氧化物纤维140与介电层150之间的边界区没有大到足以改善金属氧化物纤维140与介电层150之间的附着性。根据一些实施例，金属氧化物纤维140还称为纳米金属氧化物纤维。
在一些实施例中，金属氧化物纤维140的平均长度与平均直径的比率在约2至约80的范围内。这样，金属氧化物纤维140可以具有介于金属氧化物纤维140与介电层150之间的足够大的边界区并且仍具有足够的机械强度。
根据一些实施例，介电层150包括聚合物(如，聚酰亚胺)、氧化物(如，SiO2)、硼硅酸盐玻璃(BPSG)、旋涂玻璃(SOG)、未掺杂的硅酸盐玻璃(USG)、氟化硅酸盐玻璃(FSG)、高密度等离子体(HDP)氧化物、或等离子体增强的TEOS(PETEOS)。根据一些实施例，金属氧化物纤维140和介电层150由不同的材料制成。
根据一些实施例，介电层150包括由诸如低介电常数或超低介电常数(ELK)材料的多种介电材料所制成的多层。根据一些实施例，通过旋涂、化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、或其他适用的工艺来形成介电层150。
如图1D所示，根据一些实施例，去除介电层150的一部分和位于介电层150的部分下方的金属氧化物纤维140。根据一些实施例，去除工艺包括光刻工艺和蚀刻工艺。
根据一些实施例，在去除工艺之后，形成贯通孔152。根据一些实施例，通孔152暴露了导电结构130的部分。根据一些实施例，贯通孔152中基本上没有金属氧化物纤维。
如图1E中所示，根据一些实施例，导电层160形成在介电层150上方并且延伸进贯通孔152。根据一些实施例，导电层160电连接至导电结构130。根据一些实施例，导电层160包括再分布层和导电通孔结构。
根据一些实施例，导电层160具有顶面162和侧壁164。根据一些实施例，侧壁164围绕顶面162。导电层160包括铜或其他合适的导电材料。根据一些实施例，使用镀敷工艺(或沉积工艺)、光刻工艺和蚀刻工艺来形成导电层160。
如图1E所示，根据一些实施例，在导电层160上方形成金属氧化物纤维170。根据一些实施例，金属氧化物纤维170还称为纳米金属氧化物纤维。根据一些实施例，金属氧化物纤维170形成在导电层160的顶面162和侧壁164上方。
根据一些实施例，金属氧化物纤维170未形成在导电层160与下方的介电层150之间。根据一些实施例，金属氧化物纤维170中的每一个都具有直接连接至导电层160的端部172。根据一些实施例，金属氧化物纤维170与导电层160直接接触。在一些实施例中，两个邻近的金属氧化物纤维170彼此直接接触。
根据一些实施例，金属氧化物纤维170的平均长度在约20nm至约500nm的范围内。根据一些实施例，金属氧化物纤维170的平均直径在从约1nm至约90nm的范围内。根据一些实施例，导电层160包括金属材料(如，铜)，并且金属氧化物纤维170由金属材料的氧化物制成。根据一些实施例，金属材料的氧化物包括氧化铜。根据一些实施例，金属氧化物纤维140和170为电介质纤维。
根据一些实施例，金属氧化物纤维170的形成包括氧化导电层160的表面部分。根据一些实施例，导电层160的表面部分邻近顶面162和侧壁164。根据一些实施例，表面部分的氧化工艺包括在导电层160的表面部分上执行热氧化工艺或化学氧化工艺。
根据一些实施例，化学氧化工艺使用氧化溶液(如，H2O2)。根据一些实施例，化学氧化工艺包括将导电层160浸没在氧化溶液中。根据一些实施例，在含氧环境中执行热氧化工艺。根据一些实施例，在约100℃至约300℃的范围内的处理温度下执行热氧化工艺。
如图1F所示，根据一些实施例，在介电层150上方形成介电层180。根据一些实施例，介电层180覆盖导电层160和金属氧化物纤维170。根据一些实施例，介电层180填充金属氧化物纤维170之间的间隙G2。
根据一些实施例，介电层180围绕金属氧化物纤维170中的每一个。根据一些实施例，金属氧化物纤维170穿过介电层180。根据一些实施例，金属氧化物纤维170嵌在介电层180中。根据一些实施例，金属氧化物纤维170与介电层180直接接触。
根据一些实施例，介电层180包括聚合物(如，聚酰亚胺)、氧化物(如，SiO2)、硼磷硅酸盐玻璃(BPSG)、旋涂玻璃(SOG)、未掺杂的硅酸盐玻璃(USG)、氟化硅酸盐玻璃(FSG)、高密度等离子体(HDP)氧化物、或等离子体增强的TEOS(PETEOS)。
根据一些实施例，介电层180包括由诸如低介电常数或超低介电常数(ELK)材料的多种介电材料制成的多层。根据一些实施例，通过旋涂、化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、或其他适用的工艺来形成介电层180。
如图1G所示，根据一些实施例，去除介电层180的一部分和位于介电层180的部分下方的金属氧化物纤维170。根据一些实施例，去除工艺包括光刻工艺和蚀刻工艺。根据一些实施例，在去除工艺后，在介电层180中形成贯通孔182并且暴露导电层160的一部分。
如图1G中所示，根据一些实施例，接合焊盘190形成在介电层180上方并且延伸进贯通孔182中。根据一些实施例，接合焊盘190电连接至导电层160和导电结构130。接合焊盘190包括铜、铝、钨、镍、钯、金或其他合适的导电材料。根据一些实施例，使用镀敷工艺(或沉积工艺)、光刻工艺和蚀刻工艺来形成接合焊盘190。
如图1H所示，根据一些实施例，导电凸块C形成在接合焊盘190上方。根据一些实施例，导电凸块C包括锡(Sn)或其他合适的材料。根据一些实施例，导电凸块C的形成包括在接合焊盘190上方形成焊膏并且使焊膏回流。根据一些实施例，回流温度在约100℃至约300℃的范围内。
根据一些实施例，金属氧化物纤维140能够防止在回流工艺期间由导电结构130与介电层150之间的热膨胀系数(CTE)失配导致的导电结构130与介电层150之间的分层。根据一些实施例，金属氧化物纤维170能够防止在回流工艺期间由导电结构160与介电层180之间的热膨胀系数失配导致导电结构160与介电层180之间的分层。
图2A至图2F是根据一些实施例的用于形成半导体器件结构200的工艺的各个阶段的截面图。应该注意，根据一些实施例，除了半导体器件结构200还具有位于导电结构130上方的金属氧化物层210之外，半导体器件结构200与图1A至图1H的半导体器件结构100类似。
在本实施例以及以上所述的实施例中，相同的参考标号用于指示相同或类似的元件。因此，通过参考图1A至图1H的实施例的相关描述来提供具有相同的参考标号的元件的材料和制造方法。
如图2A所示，根据一些实施例，提供衬底110。如图2A所示，根据一些实施例，介电层120形成在衬底110上方。如图2A所示，根据一些实施例，导电结构130形成在介电层120上方。根据一些实施例，导电结构130包括布线层或多个布线层，诸如再分布层或多个再分布层。为了简洁，图2A仅示出了一个布线层，但本发明不限于此。在一些实施例中，导电结构130包括导电通孔结构或其他合适的导电结构。
根据一些实施例，导电结构130电连接至位于衬底110上方或中的器件(未示出)。根据一些实施例，导电结构130具有顶面132和侧壁134。根据一些实施例，顶面132背离衬底110。根据一些实施例，侧壁134围绕顶面132。导电结构130包括铜或其他合适的导电材料。
如图2A所示，根据一些实施例，在导电结构130上方形成金属氧化物层210和金属氧化物纤维140。根据一些实施例，金属氧化物层210共形地覆盖导电结构130的顶面132和侧壁134。根据一些实施例，金属氧化物层210连续地覆盖导电结构130的顶面132和侧壁134。
根据一些实施例，金属氧化物纤维140形成在金属氧化物层210上方。根据一些实施例，金属氧化物纤维140一起形成金属氧化物纤维层。根据一些实施例，金属氧化物纤维层具有的密度小于金属氧化物层210的密度。根据一些实施例，金属氧化物纤维140中的每一个都具有连接至金属氧化物层210的端部142。
根据一些实施例，金属氧化物纤维140与金属氧化物层210直接接触。根据一些实施例，金属氧化物纤维140和金属氧化物层210未形成在导电结构130与下方的介电层120之间。在一些实施例中，金属氧化物层210的厚度T在约2nm至约50nm的范围内。在一些实施例中，金属氧化物纤维140的平均长度大于金属氧化物层210的厚度T。
在一些实施例中，两个邻近的金属氧化物纤维140彼此直接接触。根据一些实施例，金属氧化物纤维140和金属氧化物层210由相同的材料制成。根据一些实施例，导电结构130包括金属材料(如，铜)，并且金属氧化物纤维140和金属氧化物层210由金属材料的氧化物制成。根据一些实施例，金属材料的氧化物包括氧化铜。
根据一些实施例，金属氧化物纤维140和金属氧化物层210的形成包括氧化导电结构130的表面部分。根据一些实施例，导电结构130的表面部分邻近顶面132和侧壁134。根据一些实施例，表面部分的氧化工艺包括在导电结构130的表面部分上(或在顶面132上和侧壁134上)执行热氧化工艺或化学氧化工艺。
根据一些实施例，化学氧化工艺使用氧化工艺(如，H2O2)。根据一些实施例，化学氧化工艺包括将导电结构130浸没在氧化溶液中。根据一些实施例，在含氧环境中执行热氧化工艺。
根据一些实施例，在约100℃至约300℃的范围内的处理温度下执行热氧化工艺。如果处理温度低于100℃，则可以基本不形成金属氧化物纤维140。如果处理温度高于300℃，则可以不利地影响形成在衬底10中或上方的器件。
在一些实施例中，金属氧化物层210包括原生氧化物和非原生氧化物，通过前述热氧化物工艺或前述化学氧化工艺形成该金属氧化物层。在一些实施例中，金属氧化物层210包括原生氧化物层。
如图2B所示，根据一些实施例，在介电层120上方形成介电层150。根据一些实施例，介电层150覆盖导电结构130、金属氧化物纤维140和金属氧化物层210。根据一些实施例，介电层150填充金属氧化物纤维140之间的间隙G1。
根据一些实施例，介电层150围绕金属氧化物纤维140中的每一个。根据一些实施例，金属氧化物纤维140穿过介电层150。根据一些实施例，金属氧化物纤维140嵌在介电层150中。根据一些实施例，金属氧化物纤维140与介电层150直接接触。
由于从导电结构130形成金属氧化物层210，所以金属氧化物层210与导电结构130之间的附着力大于介电层150与导电结构130之间的附着力。金属氧化物纤维140与介电层150之间的边界区较大，这改善了金属氧化物纤维140与介电层150之间的附着性。
由于金属氧化物纤维140和金属氧化物层120连接在导电结构130与介电层150之间，所以防止了导电结构130与介电层150之间的分层。因此，提高了半导体器件结构200的产量和可靠性。
根据一些实施例，金属氧化物纤维140具有的平均长度大于金属氧化物纤维140的平均直径。根据一些实施例，金属氧化物纤维140的平均长度在约20nm至约500nm的范围内。根据一些实施例，金属氧化物纤维140的平均直径在约1nm至约90nm的范围内。根据一些实施例，金属氧化物纤维140还称为纳米金属氧化物纤维。
如图2C所示，根据一些实施例，去除介电层150的一部分、下方的金属氧化物纤维140、以及该介电层150的一部分下方的金属氧化物层210。根据一些实施例，去除工艺包括光刻工艺和蚀刻工艺。
根据一些实施例，在去除工艺之后，形成贯通孔152。根据一些实施例，通孔152暴露了导电结构130的部分。根据一些实施例，贯通孔152中基本没有金属氧化物纤维。
如图2C中所示，根据一些实施例，导电层160形成在介电层150上方并且延伸进贯通孔152。根据一些实施例，导电层160电连接至导电结构130。根据一些实施例，导电层160包括布线层和导电通孔结构。
根据一些实施例，导电层160具有顶面162和侧壁164。根据一些实施例，侧壁164围绕顶面162。导电层160包括铜或其他合适的导电材料。根据一些实施例，使用镀敷工艺(或沉积工艺)、光刻工艺和蚀刻工艺来形成导电层160。
如图2C所示，根据一些实施例，在导电层160上方形成金属氧化物层220和金属氧化物纤维170。根据一些实施例，金属氧化物纤维170还称为纳米金属氧化物纤维。根据一些实施例，金属氧化物纤维170和金属氧化物层210形成在导电层160的顶面162和侧壁164上方。
根据一些实施例，金属氧化物纤维170和金属氧化物层220未形成在导电层160与下方的介电层150之间。根据一些实施例，金属氧化物纤维170中的每一个都具有直接连接至金属氧化物层220的端部172。根据一些实施例，金属氧化物纤维170与金属氧化物层220直接接触。在一些实施例中，两个邻近的金属氧化物纤维170彼此直接接触。
根据一些实施例，金属氧化物纤维170的平均长度在约20nm至约500nm的范围内。根据一些实施例，金属氧化物纤维170的平均直径在约1nm至约90nm的范围内。根据一些实施例，导电层160包括金属材料(如，铜)，并且金属氧化物纤维170和金属氧化物层220由该金属材料的氧化物制成。根据一些实施例，金属材料的氧化物包括氧化铜。
根据一些实施例，金属氧化物纤维170和金属氧化物层220的形成包括氧化导电层160的表面部分。根据一些实施例，导电层160的表面部分邻近顶面162和侧壁164。根据一些实施例，表面部分的氧化工艺包括在导电层160的表面部分上执行热氧化工艺或化学氧化工艺。
根据一些实施例，化学氧化工艺使用氧化溶液(如，H2O2)。根据一些实施例，化学氧化工艺包括将导电层160浸没在氧化溶液中。根据一些实施例，在含氧环境中执行热氧化工艺。根据一些实施例，在约100℃至约300℃的范围内的处理温度下执行热氧化工艺。
如图2D所示，根据一些实施例，在介电层150上方形成介电层180。根据一些实施例，介电层180覆盖导电层160、金属氧化物纤维170和金属氧化物层220。根据一些实施例，介电层180填充金属氧化物纤维170之间的间隙G2。
根据一些实施例，介电层180围绕金属氧化物纤维170中的每一个。根据一些实施例，金属氧化物纤维170穿过介电层180。根据一些实施例，金属氧化物纤维170嵌在介电层180中。根据一些实施例，金属氧化物纤维170与介电层180直接接触。
如图2E所示，根据一些实施例，去除介电层180的一部分、下方的金属氧化物纤维170、以及该介电层180的一部分下方的金属氧化物层220。根据一些实施例，在去除工艺后，贯通孔182形成在介电层180中并且暴露导电层160的一部分。
如图2E中所示，根据一些实施例，接合焊盘190形成在介电层180上方并且延伸进贯通孔182。根据一些实施例，接合焊盘190电连接至导电层160和导电结构130。
如图2F所示，根据一些实施例，导电凸块C形成在接合焊盘190上方。根据一些实施例，导电凸块C包括锡(Sn)或其他合适的材料。根据一些实施例，导电凸块C的形成包括在接合焊盘190上方形成焊膏并且回流焊膏。根据一些实施例，回流温度在约100℃至约300℃的范围内。
根据一些实施例，金属氧化物纤维140和金属氧化物层210能够防止在回流工艺期间由导电结构130与介电层150之间的热膨胀系数(CTE)失配导致的导电结构130与介电层150之间的分层。
根据一些实施例，金属氧化物纤维170和金属氧化物层220能够防止在回流工艺期间由导电结构160与介电层180之间的热膨胀系数失配导致的导电结构160与介电层180之间的分层。
图3A至图3O是根据一些实施例的用于形成半导体器件结构300的工艺的各个阶段的截面图。如图3A所示，根据一些实施例，提供载体衬底310。根据一些实施例，载体衬底310配置为在随后的处理步骤期间提供暂时的机械和结构支撑。根据一些实施例，载体衬底310包括玻璃、氧化硅、氧化铝、它们的组合等。
根据一些实施例，如图3A所示，在载体衬底310上方形成粘合层320。根据一些实施例，粘合层320包括任何合适的粘合材料，诸如紫外光(UV)胶，该UV胶在暴露于UV光时失去其粘合特性。使用层压工艺、旋涂工艺或另一个合适的工艺形成粘合层320。
根据一些实施例，如图3A所示，在粘合层320上方形成保护层330。根据一些实施例，保护层330配置为在随后的工艺期间提供用于接合的结构支撑并且有助于减少管芯偏移和球开裂问题。根据一些实施例，保护层330包括聚合物材料，诸如聚苯并恶唑(PBO)、聚酰亚胺、或环氧树脂。根据一些实施例，使用旋涂工艺或化学汽相沉积工艺形成保护层330。
根据一些实施例，如图3A所示，在保护层330上方形成导电层340。导电层340包括铜或其他合适的导电材料。根据一些实施例，使用物理汽相沉积工艺或化学汽相沉积工艺形成导电层340。
如图3B所示，根据一些实施例，形成掩模层350。根据一些实施例，掩模层350具有暴露导电层340的多部分的多个贯通孔352。掩模层350包括光刻胶材料或其他合适的材料。
如图3C所示，根据一些实施例，在贯通孔352中形成导电通孔结构360。根据一些实施例，导电通孔结构360还称为导电结构。导电通孔结构360包括铜或其他合适的导电材料。
根据一些实施例，导电通孔结构360的形成包括执行电镀工艺。在一些其他的实施例中，未形成导电层340，并且导电通孔结构360的形成包括执行沉积工艺和平坦化工艺。
如图3D所示，根据一些实施例，去除掩模层350。根据一些实施例，通过将掩模层350浸没在化学溶液中来去除掩模层350。例如，化学溶液包括乳酸乙酯、苯甲醚、甲基乙酸丁酯、醋酸戊酯、甲酚酚醛树脂、和/或重氮光敏化合物。
如图3D所示，根据一些实施例，去除由导电通孔结构360暴露的导电层340。根据一些实施例，去除工艺包括湿蚀刻工艺或干蚀刻工艺。
如图3E中所示，根据一些实施例，金属氧化物纤维372和374分别形成在导电层340和导电通孔结构360上方。根据一些实施例，金属氧化物纤维372形成在导电层340的侧壁342上方。
根据一些实施例，金属氧化物纤维374形成在导电通孔结构360的顶面362和侧壁364上方。根据一些实施例，金属氧化物纤维374未形成在导电层340与导电通孔结构360之间。
根据一些实施例，金属氧化物纤维372中的每一个都具有直接连接至导电层340的端部372a。根据一些实施例，金属氧化物纤维372与导电层340直接接触。根据一些实施例，金属氧化物纤维374中的每一个都具有直接连接至导电通孔结构360的端部374a。根据一些实施例，金属氧化物纤维374与导电通孔结构360直接接触。
在一些实施例中，两个邻近的金属氧化物纤维372和374彼此直接接触。根据一些实施例，导电层340包括金属材料(如，铜)，并且金属氧化物纤维372由金属材料的氧化物(如，氧化铜)制成。根据一些实施例，导电通孔结构360包括金属材料(如，铜)，并且金属氧化物纤维374由金属材料的氧化物(如，氧化铜)制成。
根据一些实施例，金属氧化物纤维372和374的形成包括氧化导电层340和导电通孔结构360的表面部分。根据一些实施例，导电层340的表面部分邻近侧壁342。
根据一些实施例，导电通孔结构360的表面部分邻近导电通孔结构360的顶面362和侧壁364。根据一些实施例，表面部分的氧化工艺包括在导电层340和导电通孔结构360的表面部分上执行热氧化工艺或化学氧化工艺。
根据一些实施例，化学氧化工艺使用氧化溶液(如，H2O2)。根据一些实施例，化学氧化工艺包括将导电层340和导电通孔结构360浸没在氧化溶液中。根据一些实施例，在含氧环境中执行热氧化工艺。
如图3F所示，根据一些实施例，提供芯片380。根据一些实施例，芯片380也被称为半导体衬底。如图3F所示，根据一些实施例，介电层390形成在芯片380上方。如图3F所示，根据一些实施例，在介电层390中形成接合焊盘410。根据一些实施例，接合焊盘410电连接至形成在芯片380中/上方的器件(未示出)。
如图3F所示，根据一些实施例，在接合焊盘410上方分别形成互连结构420。根据一些实施例，互连结构420包括导电柱或导电凸块。
如图3F所示，根据一些实施例，介电层430形成在介电层390上方并且围绕互连结构420。如图3F所示，根据一些实施例，在保护层330上方设置芯片380。如图3F所示，根据一些实施例，粘合层440定位在保护层330与芯片380之间以将芯片380接合至保护层330。
如图3G所示，根据一些实施例，模塑料层450形成在保护层330上方以覆盖导电层340、导电通孔结构360、金属氧化物纤维372和374、互连结构420、介电层390和430、粘合层440、以及芯片380。
根据一些实施例，金属氧化物纤维372和374穿过模塑料层450。根据一些实施例，模塑料层450包括聚合物材料。根据一些实施例，使用模制工艺形成模塑料层450。
如图3H所示，根据一些实施例，去除模塑料层450、导电通孔结构360的顶部、金属氧化物纤维374的一部分。根据一些实施例，去除工艺包括化学机械抛光工艺。根据一些实施例，在去除工艺之后，模塑料层450围绕芯片380。
如图3I所示，根据一些实施例，介电层460形成在模塑料层450和介电层430上方。根据一些实施例，介电层460具有暴露导电通孔结构360和互连结构420的多个开口462。
如图3I所示，根据一些实施例，导电层470形成在介电层460上方并且延伸至开口462中以与导电通孔结构360和互连结构420电连接。根据一些实施例，导电层470包括布线层和导电通孔结构。根据一些实施例，导电层470也被称为导电结构。根据一些实施例，导电层470包括铜或其他合适的导电材料。
如图3J所示，根据一些实施例，在导电层470上方形成金属氧化物纤维480。根据一些实施例，金属氧化物纤维480还称为纳米金属氧化物纤维。根据一些实施例，金属氧化物纤维480形成在导电层470的顶面472和侧壁474上方。根据一些实施例，金属氧化物纤维480未形成在导电层470与下方的介电层460之间。
根据一些实施例，导电层470包括金属材料(如，铜)，并且金属氧化物纤维480由该金属材料的氧化物(如，氧化铜)制成。根据一些实施例，金属氧化物纤维480的形成包括氧化导电层470的表面部分。根据一些实施例，表面部分的氧化工艺包括在导电层470的表面部分上执行热氧化工艺或化学氧化工艺。
如图3K所示，根据一些实施例，在介电层460上方形成介电层490。根据一些实施例，介电层490具有暴露导电层470的多部分的开口492。如图3K所示，根据一些实施例，接合焊盘B形成在介电层490上方并且延伸至开口492中以与导电层470电连接。接合焊盘B包括铜、铝、钨、镍、钯、金或其他合适的导电材料。
如图3L所示，根据一些实施例，在接合焊盘B上方分别形成导电凸块C。根据一些实施例，导电凸块C包括锡(Sn)或其他合适的材料。根据一些实施例，导电凸块C的形成包括在接合焊盘B上方形成焊膏并且回流焊膏。
在回流工艺期间，根据一些实施例，金属氧化物纤维372能够防止由导电层340与模塑料层450之间的热膨胀系数失配导致的导电层340与模塑料层450之间的分层。
类似地，根据一些实施例，金属氧化物纤维374能够防止由导电通孔结构360与模塑料层450之间的热膨胀系数失配导致的导电通孔结构360与模塑料层450之间的分层。
根据一些实施例，金属氧化物纤维480能够防止由导电层470与介电层490之间的热膨胀系数失配导致的导电层470与介电层490之间的分层。
如图3M所示，根据一些实施例，上下翻转芯片380。如图3M所示，根据一些实施例，去除载体衬底310和粘合层320。如图3N所示，根据一些实施例，去除保护层330的多部分以形成在保护层330中形成多个开口332。根据一些实施例，开口332暴露导电层340。根据一些实施例，去除工艺包括光刻工艺和蚀刻工艺。
如图3O所示，根据一些实施例，芯片封装件500设置在芯片380和模塑料层450上方以与导电层340接合。根据一些实施例，芯片封装件500包括芯片510、电路衬底520、导电凸块530和540、以及底部填充物层550。根据一些实施例，芯片510设置在电路衬底520上方。根据一些实施例，芯片510通过其间的导电凸块530接合至该电路衬底520。
根据一些实施例，电路衬底520包括复合介电层522、布线层524、导电通孔结构526、和接合焊盘528。根据一些实施例，复合介电层522具有彼此堆叠的介电层。根据一些实施例，布线层524和导电通孔结构526嵌在复合介电层522中。
根据一些实施例，接合焊盘528形成在电路衬底520的两个相对表面521a和521b上方。根据一些实施例，导电通孔结构526电连接在布线层524之间或者将布线层524电连接至接合焊盘528。根据一些实施例，导电凸块530将芯片510连接至接合焊盘528。
根据一些实施例，底部填充物层550填充在芯片510与电路衬底520之间。根据一些实施例，底部填充物层550包括聚合物材料。根据一些实施例，导电凸块540将接合焊盘528连接至导电层340。如图3O所示，根据一些实施例，底部填充物层560填充在电路衬底520与保护层330之间。根据一些实施例，底部填充物层560包括聚合物材料。
如图3O所示，根据一些实施例，模塑料层570模制在芯片510和电路衬底520上方。根据一些实施例，模塑料层570配置为保护芯片510免受随后的工艺期间的损害和污染。根据一些实施例，模塑料层570包括聚合物材料。根据一些实施例，金属氧化物纤维没有形成在接合焊盘B上方。
图4是根据本发明的一些实施例的半导体器件结构600的截面图。根据一些实施例，除了半导体器件结构600还包括金属氧化物层610、620和630之外，半导体器件结构600与图3O的半导体器件结构300类似。
如图4所示，根据一些实施例，金属氧化物层610形成在导电层340的侧壁342上方。根据一些实施例，金属氧化物纤维372连接至金属氧化物层610。根据一些实施例，金属氧化物纤维372和金属氧化物层610由相同的材料制成。根据一些实施例，金属氧化物层620形成在导电通孔结构360的侧壁364上方。
根据一些实施例，金属氧化物纤维374连接至金属氧化物层620。根据一些实施例，金属氧化物纤维374和金属氧化物层620由相同的材料制成。根据一些实施例，金属氧化物层630形成在导电层470上方。根据一些实施例，金属氧化物纤维480连接至金属氧化物层630。根据一些实施例，金属氧化物纤维480和金属氧化物层630由相同的材料制成。
根据一些实施例，提供半导体器件结构及其形成方法。方法(用于形成半导体器件结构)在导电结构上方形成金属氧化物纤维以将导电结构连接至介电层，该介电层覆盖导电结构和金属氧化物纤维。因此，金属氧化物纤维防止导电结构与介电层之间的分层。结果，提高了半导体器件结构的产量和可靠性。
根据一些实施例，提供了一种半导体器件结构。半导体器件结构包括衬底。半导体器件结构包括位于衬底上方的导电结构。半导体器件结构包括位于导电结构上方的第一金属氧化物纤维。半导体器件结构包括位于衬底上方并且覆盖导电结构和第一金属氧化物纤维的介电层。介电层填充第一金属氧化物纤维之间的间隙。
在实施例中，所述导电结构包括金属材料，并且所述多个第一金属氧化物纤维由所述金属材料的氧化物制成。
在实施例中，所述多个第一金属氧化物纤维包括氧化铜。
在实施例中，所述多个第一金属氧化物纤维与所述导电结构和所述介电层直接接触。
在实施例中，所述介电层包括聚合物材料或氧化物材料。
在实施例中，所述导电结构包括至少一个布线层。
在实施例中，所述介电层具有暴露所述导电结构的一部分的贯通孔，并且所述半导体器件结构还包括：导电层，位于所述介电层上方并且延伸至所述贯通孔中以与所述导电结构电连接；以及多个第二金属氧化物纤维，位于所述导电层上方。
在实施例中，所述导电层与所述导电层下方的介电层之间没有金属氧化物纤维。
在实施例中，半导体器件结构还包括：接合焊盘，位于所述介电层上方并且电连接至所述导电结构；以及导电凸块，位于所述接合焊盘上方并且电连接至所述接合焊盘。
在实施例中，所述多个第一金属氧化物纤维中的每一个都具有连接至所述导电结构的端部。
根据一些实施例，提供了一种半导体器件结构。半导体器件结构包括衬底。半导体器件结构包括位于衬底上方的第一导电结构。半导体器件结构包括位于第一导电结构上方的金属氧化物层。半导体器件结构包括连接至金属氧化物层的第一金属氧化物纤维。第一金属氧化物纤维和金属氧化物层由相同的材料制成。半导体器件结构包括位于衬底上方并且覆盖第一导电结构、金属氧化物层和第一金属氧化物纤维的介电层。
在实施例中，所述第一导电结构具有顶面和侧壁，并且所述金属氧化物层和所述多个第一金属氧化物纤维位于所述顶面和所述侧壁上方。
在实施例中，半导体器件结构还包括：模塑料层，围绕所述衬底；第二导电结构，穿过所述模塑料层；以及多个第二金属氧化物纤维，位于所述第二导电结构的侧壁上方并且穿过所述模塑料层。
在实施例中，所述第一导电结构包括金属材料，并且所述多个第一金属氧化物纤维和所述金属氧化物层由所述金属材料的氧化物制成。
在实施例中，所述第一金属氧化物纤维的一个端部连接至所述金属氧化物层。
根据一些实施例，提供了一种用于形成半导体器件结构的方法。方法包括在衬底上方形成导电结构。方法包括在导电结构上方形成多个第一金属氧化物纤维。方法包括在衬底上方形成介电层以覆盖导电结构和第一金属氧化物纤维。介电层填充第一金属氧化物纤维之间的间隙。
在实施例中，所述多个第一金属氧化物纤维的形成包括：氧化所述导电结构的表面部分。
在实施例中，所述导电结构的表面部分的氧化包括：在所述导电结构的表面部分上执行热氧化工艺或化学氧化工艺。
在实施例中，用于形成半导体器件结构的方法，还包括：在所述导电结构上方形成金属氧化物层，其中，所述多个第一金属氧化物纤维位于所述金属氧化物层上方。
在实施例中，用于形成半导体器件结构的方法还包括：去除所述介电层的第一部分和所述第一部分下方的第一金属氧化物纤维，以形成暴露所述导电结构的第二部分的贯通孔；形成位于所述介电层上方并且延伸至所述介电层的贯通孔中的导电层；以及在所述导电层上方形成多个第二金属氧化物纤维。
以上论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本发明的各个实施例。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体器件结构，包括：
衬底；
导电结构，位于所述衬底上方；
多个第一金属氧化物纤维，位于所述导电结构上方；以及
介电层，位于所述衬底上方并且覆盖所述导电结构和所述多个第一金属氧化物纤维，其中，所述介电层填充所述多个第一金属氧化物纤维之间的间隙。
2.根据权利要求1所述的半导体器件结构，其中，所述导电结构包括金属材料，并且所述多个第一金属氧化物纤维由所述金属材料的氧化物制成。
3.根据权利要求1所述的半导体器件结构，其中，所述多个第一金属氧化物纤维包括氧化铜。
4.根据权利要求1所述的半导体器件结构，其中，所述多个第一金属氧化物纤维与所述导电结构和所述介电层直接接触。
5.根据权利要求1所述的半导体器件结构，其中，所述介电层包括聚合物材料或氧化物材料。
6.根据权利要求1所述的半导体器件结构，其中，所述导电结构包括至少一个布线层。
7.根据权利要求1所述的半导体器件结构，其中，所述介电层具有暴露所述导电结构的一部分的贯通孔，并且所述半导体器件结构还包括：
导电层，位于所述介电层上方并且延伸至所述贯通孔中以与所述导电结构电连接；以及
多个第二金属氧化物纤维，位于所述导电层上方。
8.根据权利要求7所述的半导体器件结构，其中，所述导电层与所述导电层下方的介电层之间没有金属氧化物纤维。
9.一种半导体器件结构，包括：
衬底；
第一导电结构，位于所述衬底上方；
金属氧化物层，位于所述第一导电结构上方；
多个第一金属氧化物纤维，连接至所述金属氧化物层，其中，所述多个第一金属氧化物纤维和所述金属氧化物层由相同的材料制成；以及
介电层，位于所述衬底上方并且覆盖所述第一导电结构、所述金属氧化物层和所述多个第一金属氧化物纤维。
10.一种用于形成半导体器件结构的方法，包括：
在衬底上方形成导电结构；
在所述导电结构上方形成多个第一金属氧化物纤维；以及
在所述衬底上方形成介电层以覆盖所述导电结构和所述多个第一金属氧化物纤维，其中，所述介电层填充所述所述第一金属氧化物纤维之间的间隙。
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9508664B1 (en) 2015-12-16 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same
US9997471B2 (en) * 2016-07-25 2018-06-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
WO2019004264A1 (ja) * 2017-06-30 2019-01-03 株式会社村田製作所 電子部品モジュール及びその製造方法
US10325854B2 (en) * 2017-07-18 2019-06-18 Advanced Semiconductor Engineering, Inc. Interposer and semiconductor package device
US10290611B2 (en) * 2017-07-27 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same
US10103107B1 (en) 2017-08-08 2018-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
KR102486561B1 (ko) * 2017-12-06 2023-01-10 삼성전자주식회사 재배선의 형성 방법 및 이를 이용하는 반도체 소자의 제조 방법
US10867919B2 (en) * 2018-09-19 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Electronic device and manufacturing method thereof
CN113196469B (zh) * 2018-12-21 2024-03-29 株式会社村田制作所 电子部件模块的制造方法及电子部件模块
FR3094138A1 (fr) * 2019-03-19 2020-09-25 Stmicroelectronics (Grenoble 2) Sas Circuits superposés interconnectés
DE202019002164U1 (de) * 2019-05-17 2019-06-21 Heraeus Nexensos Gmbh Verbesserter Hochtemperaturchip
US11984403B2 (en) * 2019-11-15 2024-05-14 Dyi-chung Hu Integrated substrate structure, redistribution structure, and manufacturing method thereof
KR20220026308A (ko) 2020-08-25 2022-03-04 삼성전자주식회사 반도체 패키지
KR20220047066A (ko) 2020-10-08 2022-04-15 삼성전자주식회사 반도체 패키지 장치

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076618A (ja) * 2000-08-23 2002-03-15 Ibiden Co Ltd 多層プリント配線板の製造方法
JP2005071965A (ja) * 2003-08-28 2005-03-17 Mitsubishi Electric Corp 電界放出型冷陰極構造、その製造方法、及び平板型画像表示装置
JP2006059676A (ja) * 2004-08-20 2006-03-02 Konica Minolta Holdings Inc 電子放出素子およびその製造方法
CN100475005C (zh) * 1998-02-26 2009-04-01 揖斐电株式会社 具有充填导电孔构造的多层印刷布线板
JP2010062175A (ja) * 2008-09-01 2010-03-18 Casio Comput Co Ltd 半導体装置の製造方法
CN102548248A (zh) * 2010-12-29 2012-07-04 三星电机株式会社 一种印制电路板及其制作方法

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4234458A (en) 1979-04-23 1980-11-18 Uop Inc. Acidic multimetallic catalytic composite
US4946518A (en) 1989-03-14 1990-08-07 Motorola, Inc. Method for improving the adhesion of a plastic encapsulant to copper containing leadframes
JPH11233545A (ja) 1997-11-10 1999-08-27 Citizen Watch Co Ltd 半導体装置とその製造方法
US20020000657A1 (en) 1999-05-06 2002-01-03 Cheng P. Wen Plated chrome solder dam for high power mmics
JP4582892B2 (ja) 1999-11-11 2010-11-17 イビデン株式会社 多層プリント配線板およびその製造方法
US6770971B2 (en) * 2002-06-14 2004-08-03 Casio Computer Co., Ltd. Semiconductor device and method of fabricating the same
JP2004022699A (ja) 2002-06-14 2004-01-22 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2004230690A (ja) 2003-01-30 2004-08-19 Takiron Co Ltd 制電性透明樹脂板
MXPA06013990A (es) * 2004-04-30 2007-08-14 Virtus Nutrition Llc Sintesis de sal de metal monovalente y divalente de acido graso polinsaturado.
US8394679B2 (en) * 2004-05-28 2013-03-12 Stellarray, Inc. Nano-structured gasket for cold weld hermetic MEMS package and method of manufacture
US20090151972A1 (en) 2004-05-28 2009-06-18 Stellar Microdevices, Inc. Cold weld hermetic mems package and method of manufacture
KR20060000106A (ko) 2004-06-28 2006-01-06 삼성전자주식회사 최외곽 수지층의 접착성을 향상시킨 인쇄 회로 기판과 그제조방법, 그 인쇄 회로 기판을 포함하는 반도체 패키지및 그 제조방법
US7365007B2 (en) 2004-06-30 2008-04-29 Intel Corporation Interconnects with direct metalization and conductive polymer
JP2006270031A (ja) 2005-02-25 2006-10-05 Casio Comput Co Ltd 半導体装置およびその製造方法
JP5100032B2 (ja) * 2005-06-27 2012-12-19 ラピスセミコンダクタ株式会社 基板の表面改質方法及び半導体装置の製造方法
EP2024283A2 (en) * 2006-05-19 2009-02-18 Massachusetts Institute of Technology Continuous process for the production of nanostructures including nanotubes
JP5502268B2 (ja) * 2006-09-14 2014-05-28 信越化学工業株式会社 システムインパッケージ型半導体装置用の樹脂組成物セット
CN101536199A (zh) * 2006-11-10 2009-09-16 皇家飞利浦电子股份有限公司 包括单片陶瓷发光转换器的照明系统
US8178964B2 (en) * 2007-03-30 2012-05-15 Advanced Chip Engineering Technology, Inc. Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same
US8012886B2 (en) * 2007-03-07 2011-09-06 Asm Assembly Materials Ltd Leadframe treatment for enhancing adhesion of encapsulant thereto
JP4498378B2 (ja) * 2007-03-30 2010-07-07 三洋電機株式会社 基板およびその製造方法、回路装置およびその製造方法
US7648799B2 (en) * 2007-03-30 2010-01-19 Eveready Battery Co., Inc. Multi-layer positive electrode structures having a silver-containing layer for miniature cells
JP5286893B2 (ja) * 2007-04-27 2013-09-11 日立化成株式会社 接続端子、接続端子を用いた半導体パッケージ及び半導体パッケージの製造方法
KR101383357B1 (ko) * 2007-08-27 2014-04-10 엘지이노텍 주식회사 발광 소자 패키지 및 그 제조방법
US7858266B2 (en) * 2008-07-10 2010-12-28 Gm Global Technology Operations, Inc. Structural reinforcement of membrane electrodes
JP2010212492A (ja) 2009-03-11 2010-09-24 Tokyo Electron Ltd 半導体装置の製造方法
JP5584991B2 (ja) 2009-04-02 2014-09-10 コニカミノルタ株式会社 透明電極、透明電極の製造方法、および有機エレクトロルミネッセンス素子
WO2010147187A1 (ja) * 2009-06-18 2010-12-23 ローム株式会社 半導体装置
US20120153444A1 (en) * 2009-06-18 2012-06-21 Rohm Co., Ltd Semiconductor device
CA2716144A1 (en) * 2009-10-02 2011-04-02 University Of Windsor Method of surface treatment of aluminum foil and its alloy and method of producing immobilized nanocatalyst of transition metal oxides and their alloys
JP2011114233A (ja) 2009-11-27 2011-06-09 Sony Corp 積層配線基板とその製造方法
US8455995B2 (en) * 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
JP2012216780A (ja) * 2011-03-31 2012-11-08 Ricoh Co Ltd ｐ型酸化物、ｐ型酸化物製造用組成物、ｐ型酸化物の製造方法、半導体素子、表示素子、画像表示装置、及びシステム
JP5200194B2 (ja) * 2011-06-24 2013-05-15 パナソニック株式会社 窒化ガリウム系半導体発光素子、光源および凹凸構造形成方法
EP2548841B1 (de) * 2011-07-19 2016-01-06 LITRONIK Batterietechnologie GmbH Aktivmaterial für eine Elektrode eines galvanischen Elements
JP5783094B2 (ja) * 2011-11-30 2015-09-24 株式会社リコー ｐ型酸化物、ｐ型酸化物製造用組成物、ｐ型酸化物の製造方法、半導体素子、表示素子、画像表示装置、及びシステム
JP5915370B2 (ja) * 2012-05-16 2016-05-11 ソニー株式会社 電気泳動素子、電気泳動表示装置、電子機器、及び、電気泳動素子の製造方法
US9273415B2 (en) * 2012-09-07 2016-03-01 International Business Machines Corporation Methods for preparing carbon hybrid materials
US9508674B2 (en) * 2012-11-14 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control of semiconductor die package
US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US9087832B2 (en) 2013-03-08 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage reduction and adhesion improvement of semiconductor die package
US8907479B2 (en) * 2013-03-11 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Treating copper surfaces for packaging
US8916972B2 (en) 2013-03-12 2014-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Adhesion between post-passivation interconnect structure and polymer
US8916981B2 (en) 2013-05-10 2014-12-23 Intel Corporation Epoxy-amine underfill materials for semiconductor packages
TWI533421B (zh) * 2013-06-14 2016-05-11 日月光半導體製造股份有限公司 半導體封裝結構及半導體製程
KR102154112B1 (ko) * 2013-08-01 2020-09-09 삼성전자주식회사 금속 배선들을 포함하는 반도체 장치 및 그 제조 방법
US8828100B1 (en) 2013-10-14 2014-09-09 John C. Warner Formulation and processes for hair coloring
US9252065B2 (en) * 2013-11-22 2016-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming package structure
US9331021B2 (en) 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9607959B2 (en) * 2014-08-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging device having plural microstructures disposed proximate to die mounting region
KR102285432B1 (ko) * 2014-11-18 2021-08-04 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 발광소자 패키지
US9583472B2 (en) * 2015-03-03 2017-02-28 Apple Inc. Fan out system in package and method for forming the same
KR102435855B1 (ko) * 2015-08-06 2022-08-25 삼성전자주식회사 하드 마스크 패턴의 형성 방법 및 이를 이용한 반도체 소자의 제조 방법
US9508664B1 (en) * 2015-12-16 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same
US9859222B1 (en) 2016-06-08 2018-01-02 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
DE102016117841A1 (de) * 2016-09-21 2018-03-22 HYUNDAI Motor Company 231 Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung
DE102016118784A1 (de) * 2016-10-04 2018-04-05 Infineon Technologies Ag Chipträger, konfiguriert zur delaminierungsfreien Kapselung und stabilen Sinterung

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100475005C (zh) * 1998-02-26 2009-04-01 揖斐电株式会社 具有充填导电孔构造的多层印刷布线板
JP2002076618A (ja) * 2000-08-23 2002-03-15 Ibiden Co Ltd 多層プリント配線板の製造方法
JP2005071965A (ja) * 2003-08-28 2005-03-17 Mitsubishi Electric Corp 電界放出型冷陰極構造、その製造方法、及び平板型画像表示装置
JP2006059676A (ja) * 2004-08-20 2006-03-02 Konica Minolta Holdings Inc 電子放出素子およびその製造方法
JP2010062175A (ja) * 2008-09-01 2010-03-18 Casio Comput Co Ltd 半導体装置の製造方法
CN102548248A (zh) * 2010-12-29 2012-07-04 三星电机株式会社 一种印制电路板及其制作方法

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