CN106887422A - 封装件结构及其形成方法 - Google Patents

封装件结构及其形成方法 Download PDF

Info

Publication number
CN106887422A
CN106887422A CN201610688826.0A CN201610688826A CN106887422A CN 106887422 A CN106887422 A CN 106887422A CN 201610688826 A CN201610688826 A CN 201610688826A CN 106887422 A CN106887422 A CN 106887422A
Authority
CN
China
Prior art keywords
insulating barrier
metal oxide
conductive structure
monovalent metal
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610688826.0A
Other languages
English (en)
Other versions
CN106887422B (zh
Inventor
余振华
林俊成
符策忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN106887422A publication Critical patent/CN106887422A/zh
Application granted granted Critical
Publication of CN106887422B publication Critical patent/CN106887422B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4864—Cleaning, e.g. removing of solder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0541—11th Group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明的实施例提供了封装件结构及其形成方法。封装件结构包括衬底和在衬底上方形成的半导体管芯。封装件结构还包括覆盖半导体管芯的封装件层和在封装件层中形成的导电结构。封装件结构包括在导电结构上形成的第一绝缘层，并且第一绝缘层包括一价金属氧化物。在第一绝缘层和封装件层之间形成第二绝缘层。第二绝缘层包括一价金属氧化物，并且第二绝缘层中的一价金属氧化物的重量比大于第一绝缘层中的一价金属氧化物的重量比。

Description

封装件结构及其形成方法
相关申请的交叉引用
本申请涉及下列于2015年12月16日提交的美国序列号第14/970,962号的共同待审通常指定的专利申请，其整体内容引入本文作为参考。
技术领域
本发明涉及半导体领域，更具体地，涉及封装件结构及其形成方法。
背景技术
半导体器件用于许多电子应用，作为实例诸如个人电脑、移动电话、数码相机以及其他电子设备。通常，通过在半导体衬底上依次沉积材料的绝缘或介电层、导电层以及半导体层，并且使用光刻图案化各个材料层以在所述材料层上形成电路部件和元件来制造半导体器件。通常，在单个半导体晶圆上制造许多集成电路，并且通过沿着划线在集成电路之间锯切将单个管芯分割。通常，例如，在多芯片模块或在其他类型的封装件中将单个管芯单独封装。
已经开始研发诸如堆叠式封装(PoP)的新封装技术，其中将具有器件管芯的顶部封装件接合至具有另一个器件管芯的底部封装件。通过采用新的封装技术，将具有不同或类似功能的各种封装件集成在一起。
通常，尽管现有封装件结构以及制造封装件结构的方法足够用于它们的预期目的，但它们并非在所有方面完全符合要求。
发明内容
根据本发明的实施例，提供了一种封装件结构，包括：衬底；在衬底上方形成的半导体管芯；邻近半导体管芯的封装件层；在封装件层中形成的导电结构；在导电结构上形成的第一绝缘层，其中，第一绝缘层包括一价金属氧化物；以及在第一绝缘层和封装件层之间形成的第二绝缘层，其中，第二绝缘层包括一价金属氧化物，并且其中，第二绝缘层中的一价金属氧化物的重量比大于第一绝缘层中的一价金属氧化物的重量比。
根据本发明的实施例，提供了一种封装件结构，包括：衬底；在衬底上方形成的半导体管芯；邻近半导体管芯的封装件层；在封装件层中形成的导电结构；以及在导电结构上形成的绝缘层，其中，绝缘层包括邻近绝缘层的外表面的第一位置处的一价金属氧化物，并且在第一位置处的一价金属氧化物多于邻近与导电结构接触的内表面的第二位置处的一价金属氧化物。
根据本发明的实施例，提供了一种形成封装件结构的方法，包括：在衬底上方形成导电结构；在衬底上方形成半导体管芯，其中，半导体管芯被导电结构包围；在导电结构上实施湿工艺或等离子体工艺以在导电结构上方形成绝缘层，其中，绝缘层包括在第一绝缘层上方的第二绝缘层，其中，第一绝缘层和第二绝缘层都包括一价金属氧化物，并且第二绝缘层中的一价金属氧化物的重量比大于第一绝缘层中的一价金属氧化物的重量比；以及在半导体管芯和第二绝缘层上方形成封装件层。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各种部件的数量和尺寸可以被任意增加或减少。
图1A至图1N示出根据本发明的一些实施例的形成封装件结构的各个阶段的截面视图。
图1H’示出根据本发明的一些实施例的在导电结构上实施的湿工艺的截面视图。
图2A示出根据本发明的一些实施例的在等离子体工艺或湿工艺之前的导电结构的顶视图。
图2B示出根据本发明的一些实施例的在等离子体工艺或湿工艺之后的导电结构的顶视图。
图3A示出根据本发明的一些实施例的在等离子体工艺或湿工艺之前的导电结构的顶视图。
图3B示出根据本发明的一些实施例的在等离子体工艺或湿工艺之后的导电结构的顶视图。
具体实施方式
以下公开的内容提供了多种不同实施例或实例，用于实现本发明的不同部件。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考符号和/或字符。这种重复用于简化和清楚，并且其本身不表示所述多个实施例和/或配置之间的关系。
描述了实施例的一些变型。在整个各个视图和示出的实施例中，相同的引用符号用于指定相同元件。应当理解，在方法之前、期间和之后可提供额外的操作，并且对于方法的其他实施例，可替换或消除所描述的一些操作。
提供了封装件结构及其形成方法的实施例。图1A至图1N示出根据本发明的一些实施例的形成封装件结构100的各个阶段的截面视图。封装件结构100适用于晶圆级封装件(WLP)。
如图1A所示，提供了衬底102。衬底102为临时支撑衬底。在一些实施例中，衬底102由半导体材料、陶瓷材料、聚合物材料、金属材料、任何适用的材料或其组合制成。在一些实施例中，衬底102为玻璃衬底。在一些实施例中，衬底102为诸如硅晶圆的半导体衬底。
在衬底102上形成粘合剂层104。在一些实施例中，粘合剂层由胶水或箔制成。在一些其他实施例中，粘合剂层104由通过光辐射从衬底102中容易分离的感光材料制成。在一些实施例中，粘合剂层104由热敏材料制成。
此后，在粘合剂层104上形成基底层106。在一些实施例中，基底层106由聚合物层或含聚合物的层制成。基底层106可为聚对苯撑苯并双噻唑(PBO)层、聚酰亚胺(PI)层、阻焊(SR)层、味之素堆积膜(ABF)、管芯附接膜(DAF)、另外的适用材料或其组合。在一些实施例中，在衬底102上方沉积或层压粘合剂层104和基底层106。
此后，根据本发明的一些实施例，如图1B所示，在基底层106上方形成晶种层108。在一些实施例中，晶种层108由诸如铜(Cu)、钛(Ti)、铜合金、钛合金或其组合的金属材料制成。在一些实施例中，通过诸如化学汽相沉积工艺(CVD)、物理汽相沉积工艺(PVD)、另一种适用的工艺或其组合的沉积工艺形成晶种层108。
根据本发明的一些实施例，如图1C所示，在基底层106上形成晶种层108之后，在晶种层108上形成掩模层110。在掩模层110中形成开口112。通过开口112暴露晶种层108。开口112用于限定导电结构(随后形成，在图1D中示出)的位置。在一些实施例中，掩模层110由光刻胶材料制成。通过图案化工艺形成开口112。图案化工艺包括光刻工艺和蚀刻工艺。光刻工艺的实例包括软烘烤、掩模对齐、曝光、曝光后烘烤、显影和光刻、冲洗和干燥(例如，硬烘烤)。蚀刻工艺可为干蚀刻或湿蚀刻工艺。
此后，根据本发明的一些实施例，如图1D所示，在掩模层110中形成导电结构114。将导电结构114填充至开口112中。导电结构114可由诸如铜(Cu)、铝(Al)、钨(W)、镍(Ni)、其合金或其组合的金属材料制成。导电结构114的顶视图形状可为矩形、正方形、圆形等。导电结构114的高度取决于掩模层110的厚度。在一些实施例中，通过电镀工艺形成导电结构114。
此后，根据本发明的一些实施例，如图1E所示，去除掩模层110，并且实施蚀刻工艺以去除晶种层108的部分。在蚀刻工艺期间，导电结构114用作掩模。因此，导电结构114和剩余的晶种层108结合在一起称为InFO通孔(TIV)116，还将其称为通孔116。在一些实施例中，导电结构114和晶种层108由相同材料制成，因此在导电结构114和晶种层108之间没有可区分的界面。
此后，根据本发明的一些实施例，如图1F所示，通过粘合剂层122在基底层106上方形成半导体管芯120。导电结构114的高度大于半导体管芯120的高度。导电结构114的顶面高于半导体管芯120的顶面。
在一些实施例中，粘合剂层122为管芯附接膜(DAF)。半导体管芯120包括半导体衬底124、介电层126、导电衬垫128、钝化层130和连接件132。在介电层126中形成导电衬垫128，并在钝化层130中形成连接件132。将连接件132电连接至导电衬垫128。
可在半导体管芯120中形成其他器件元件。器件元件包括晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高压晶体管、高频晶体管、p-沟道和/或n沟道场效应晶体管(PFET/NFET)等)、二极管和/或其他适用元件。实施诸如沉积、蚀刻、注入、光刻、退火和/或其他适用工艺的多种工艺以形成器件元件。
如图1G所示，在导电结构114上自然形成第一绝缘层136a。第一绝缘层136a包围导电结构114。换言之，导电结构114和晶种层108被第一绝缘层136a包围。
导电结构114包括金属材料，并且第一绝缘层136a包括与金属材料相同的金属元素。在一些实施例中，第一绝缘层136a为自然氧化物层。在一些实施例中，导电结构114包括铜(Cu)，并且第一绝缘层136a包括氧化铜和氧化亚铜(CuO和Cu2O)。
应该注意，在导电结构114和封装件层(随后形成，诸如图1I所示的封装件层140)之间形成第一绝缘层136a。然而，在诸如加热工艺的随后的工艺期间可能发生第一绝缘层136a和封装件层之间的分层。例如，在加热操作期间，加热可引起应力，并且加热可引起封装件层的分层。
在一些实施例中，根据本发明的一些实施例，在导电结构114上实施等离子体工艺11并将第一绝缘层的外部转化为第二绝缘层136b。例如，如图1H所示，在导电结构114上方形成第二绝缘层136b。与在实施等离子体工艺11之前的第一绝缘层136a的表面相比，在实施等离子体工艺11之后获得位于第二绝缘层136b上的粗糙表面。第一绝缘层136a’具有第一厚度T1，且第二绝缘层136b具有第二厚度T2。在一些实施例中，第一厚度T1与第二厚度T2的比例(T1/T2)为从约1/1至约1/0.2的范围。
在等离子体工艺11之后，绝缘层136包括第一绝缘层136a’和第二绝缘层136b。第一绝缘层136a’比第二绝缘层136b更接近导电结构114。换言之，形成与导电结构114直接接触的第一绝缘层136a’，并且形成与封装件层140(图1I所示)直接接触的第二绝缘层136b。如图1H所示，绝缘层136中的虚线用于示意性限定两层。换言之，绝缘层136包括比邻近与导电结构114接触的内表面的第二位置处的一价金属氧化物更多的邻近绝缘层136的外表面的第一位置处的一价金属氧化物。“邻近外表面”的描述在第二绝缘层136b的厚度范围内，且“邻近内表面”在第一绝缘层136a’中的厚度内。
在一些实施例中，两层136a’、136b中的一价金属氧化物和二价金属氧化物的组成不同。例如，第一绝缘层136a’和第二绝缘层136b中的一价金属氧化物和二价金属氧化物的重量比不同。可通过形成第二层136b改善粘合以避免分层问题。
导电结构114包括金属材料，并且第一绝缘层136a’和第二绝缘层136b包括与金属材料相同的金属元素。更具体地，第一绝缘层136a’和第二绝缘层136b都包括一价金属氧化物和二价金属氧化物，且第二绝缘层136b包括较高比例的一价金属氧化物。例如，导电结构114包括铜(Cu)，且第一绝缘层136a’和第二绝缘层136b包括氧化铜(CuO)和氧化亚铜(Cu2O)。
应该注意，第二绝缘层136b中的一价金属氧化物的重量比大于第一绝缘层136a’中的一价金属氧化物的重量比。在一些实施例中，导电结构114包括铜(Cu)，且第二绝缘层136b中的氧化亚铜(Cu2O)的重量比大于第一绝缘层136a’中的氧化亚铜(Cu2O)。在一些实施例中，第二绝缘层136b中的氧化亚铜(Cu2O)的重量比为从约30％至约60％的范围。在一些实施例中，第一绝缘层136a’中的氧化亚铜(Cu2O)的重量比为从约20％至约28％的范围。在一些实施例中，第二绝缘层136b中的氧化亚铜(Cu2O)的重量比为第一绝缘层136a’中的氧化亚铜(Cu2O)的重量比的约1.5至3倍。
在一些其他实施例中，第二绝缘层136b中的氧化亚铜(Cu2O)和氧化铜(CuO)的重量比从第二绝缘层136b的内表面向外表面逐渐增加。内表面为第一绝缘层136a’和第二绝缘层136b之间的界面。外表面为第二绝缘层136b和封装件层140之间的界面。在一些实施例中，第一绝缘层136a’中的氧化亚铜(Cu2O)和氧化铜(CuO)的重量比基本恒定。
此外，第二绝缘层136b的表面粗糙度大于第一绝缘层136a’的表面粗糙度。高粗糙度增加接触面积，因此提高粘合强度。通过处理导电结构114的表面提高导电结构114和封装件层140之间的粘合。
换言之，与二价金属氧化物相比，一价金属氧化物提供导电结构114和随后形成的封装件层140之间更好的接合特性。
在一些实施例中，等离子体工艺11包括实施预清洗工艺和主要等离子体工艺。预清洗工艺配置为清洗导电结构114的表面以及去除一些污染物。如果未去除污染物，它们可阻碍并降低导电结构114和封装件层140之间的粘合。主要等离子体工艺配置为改变第一绝缘层136a的成分。因此，获得在第一绝缘层136a’上方形成的第二绝缘层136b。
在一些实施例中，清洗工艺包括使用具有从约200sccm至约600sccm的范围的流速的氮气(N2)。在一些实施例中，在从约20Pa至约70Pa的范围的压力下实施清洗工艺。在一些实施例中，将清洗工艺实施从约10秒至约70秒的范围的时间。当将预清洗工艺实施上述范围内的时间时，完全去除污染物。
在一些实施例中，主要等离子体工艺包括使用具有从约100sccm至约300sccm的范围的流速的氧气(O2)。除了氧气(O2)之外，主要等离子体工艺还包括使用具有从约100sccm至约300sccm的范围的流速的氩气(Ar)。氩气(Ar)还用于增加表面粗糙度。在一些实施例中，在从约20Pa至约40Pa的范围的压力下实施主要等离子体工艺。在一些实施例中，将主要等离子体工艺实施从约5秒至约50秒的范围的时间。当将主要等离子体工艺实施上述范围内的时间时，增加了第二绝缘层136b中的一价金属氧化物的比例。
在一些其他实施例中，在导电结构114上实施湿工艺13并将绝缘层136a的外部转化为第二绝缘层136b。根据本发明的一些实施例，如图1H’所示，在导电结构114上方形成第二绝缘层136b。
在一些实施例中，湿工艺13包括将衬底102放入化学浴20中。化学浴20包括输入端202和输出端204。输入端202用于提供用于化学溶液的输入，并且输出端204用于提供用于化学溶液的输出。螺旋桨206用于搅拌和循环化学溶液，因此可使衬底102与化学溶液均匀反应。
在湿工艺13之后，获得包括第一绝缘层136a’和第二绝缘层136b的绝缘层136。第一绝缘层136a’包括一价金属氧化物和二价金属氧化物。第二绝缘层136b包括一价金属氧化物和二价金属氧化物。在一些实施例中，一价金属氧化物为氧化亚铜(Cu2O)，且二价金属氧化物为氧化铜(CuO)或氢氧化铜(Cu(OH)2)。
应该注意，第二绝缘层136b中的一价金属氧化物的重量比大于第一绝缘层136a’中的一价金属氧化物的重量比。在一些实施例中，第二绝缘层136b中的一价金属氧化物的比例为从约30wt％至约60wt％的范围。在一些实施例中，第一绝缘层136a’中的一价金属氧化物的比例为从约20wt％至约28wt％的范围。
在一些实施例中，化学溶液包括过氧化氢(H2O2)溶液。在一些实施例中，过氧化氢(H2O2)溶液具有从约20wt％至约60wt％的范围的浓度。在一些实施例中，在室温下实施化学浴20。在一些实施例中，在从约20度至约40度的范围的温度下实施化学浴20。
在湿工艺13之后，在绝缘层136上实施可选的清洗工艺。清洗工艺用于去除可能来自化学浴20的一些污染物。如果污染物剩余在绝缘层136上方，则污染物可阻止封装件层140的粘合。在一些实施例中，清洗工艺包括使用具有从约200sccm至约700sccm的范围的流速的氮气(N2)。
应该注意，过氧化氢(H2O2)溶液容易制备并且在室温下实施化学浴20而不加热化学浴20。因此，实施湿工艺13的成本相对低。湿工艺13可用于大量生产。
如上所述，通过实施等离子体工艺11或实施湿工艺13改进导电结构114和封装件层140之间的粘合。避免分层问题。因此，进一步改进封装件结构100的可靠性和性能。
此后，根据本发明的一些实施例，如图1I所示，在半导体管芯120和绝缘层136上方形成封装件层140。在一些实施例中，封装件层140完全封装和覆盖半导体管芯120。封装件层140的顶面高于导电结构114的顶面和半导体管芯120的顶面。
在一些实施例中，封装件层140由诸如液体环氧树脂、可变性凝胶、硅橡胶等的模塑料制成。在一些实施例中，在基底层106、半导体管芯120和绝缘层136上方分配模塑料，并且因此实施热工艺以硬化模塑料。
在形成封装件层140之后，根据本发明的一些实施例，如图1J所示，实施平坦化工艺以暴露半导体管芯120和InFO通孔(TIV)116。在平坦化工艺之后，半导体管芯120的顶面与导电结构114的顶面基本齐平。在一些实施例中，平坦化工艺包括研磨工艺、化学机械抛光(CMP)工艺、蚀刻工艺、其他适用工艺或其组合。
在平坦化工艺之后，根据本发明的一些实施例，如图1K所示，在封装件层140上方形成再分布结构146。再分布结构146包括在钝化层142中形成再分布线(RDL)144。将RDL144电连接至半导体管芯120和InFO通孔(TIV)116。
在一些实施例中，再分布线(RDL)144由诸如铜(Cu)、铜合金、铝(Al)、铝合金、钨(W)、钨合金、钛(Ti)、钛合金、钽(Ta)或钽合金的金属材料制成。在一些实施例中，通过电镀、无电镀电镀、溅射或化学汽相沉积(CVD)形成RDL 144。在一些实施例中，钝化层142由聚苯并噁唑(PBO)、苯并环丁烯(BCB)、硅酮、丙烯酸酯、硅氧烷或其组合制成。在一些其他实施例中，钝化层142由诸如氧化硅、无掺杂硅酸盐玻璃、氮氧化硅、阻焊(SR)层、氮化硅、HMDS(六甲基二硅氮烷)的非有机材料制成。
此后，在再分布结构146上方形成电连接件148。在一些实施例中，电连接件148包括焊球、金属柱、其他适用连接件。在一些实施例中，在电连接件148下方形成凸块下金属化(UBM)层(未示出)。
此后，根据本发明的一些实施例，如图1L所示，去除衬底102和粘合剂层104，并将图1K的结构翻转并且附接至载体152。因此，基底层106面朝上并且暴露。载体152包括感光或热敏的胶带并且容易从电连接件148中分离载体152。
此后，根据本发明的一些实施例，如图1M所示，去除基底层106的一部分以形成开口154。在一些实施例中，去除晶种层108的一部分，并将晶种层108暴露。在一些其他实施例中，不去除或完全去除晶种层108。在一些其他实施例中，通过激光钻孔工艺、蚀刻工艺或其他适用工艺形成开口154。
根据本发明的一些实施例，如图1N所示，在形成开口154之后，将电连接件158填充至开口154中。此后，将顶封装件160接合至电连接件158。顶封装件160包括封装件衬底162和半导体管芯164。在一些实施例中，半导体管芯164包括诸如静态随机存储存储器(SRAM)管芯、动态随机存储存储器(DRAM)管芯等的存储器管芯。
此后，半导体结构100可继续经历其他工艺以形成其他结构或器件。此后，实施切割工艺以将图1N所示的结构分离为芯片封装件。
图2A示出根据本发明的一些实施例，在等离子体工艺11或湿工艺13之前，导电结构114的顶视图。如图2A所示，第一绝缘层136a包围导电结构114，并且导电结构114的顶视图形状为圆形。
图2B示出根据本发明的一些实施例，在等离子体工艺11或湿工艺13之后，导电结构114的顶视图。在实施等离子体工艺11或湿工艺13之后，获得在第一绝缘层136a’上方形成的第二绝缘层136b。第二绝缘层136b将与封装件层140直接接触。将第二绝缘层136b的表面粗糙度增加以提高导电结构114和封装件层140之间的粘合力。
如上所述，绝缘层136包括多于邻近与导电结构114接触的内表面的第二位置处的一价金属氧化物的邻近绝缘层136的外表面的第一位置处的一价金属氧化物。“邻近外表面”的描述在第二绝缘层136b的厚度范围内，且“邻近内表面”在第一绝缘层136a’中的厚度内。
图3A示出根据本发明的一些实施例，导电结构114的顶视图。如图3A所示，第一绝缘层136a包围导电结构114，并且导电结构114的顶视图形状为矩形。
图3B示出根据本发明的一些实施例，在等离子体工艺11或湿工艺13之后，导电结构114的顶视图。第二绝缘层136b中的一价金属氧化物的重量比大于第一绝缘层136a’中的一价金属氧化物的重量比。通过改变第二绝缘层136b的比例提高接合强度。因此，进一步提高封装件结构100的可靠性和性能。
提供了用于形成封装件结构的实施例及其形成方法。在衬底上方形成半导体管芯，并且封装件层覆盖半导体管芯。在封装件层中形成导电结构，并在导电结构和封装件层之间形成绝缘层。在导电结构上实施等离子体工艺或湿工艺以形成包括第一绝缘层和第二绝缘层的绝缘层。第二绝缘层与封装件层直接接触并且具有较大的表面粗糙度以提高粘合性。当提高粘合性时，避免分层问题。因此，也提高封装件结构的性能。
在一些实施例中，提供了封装件结构。封装件结构包括衬底和在衬底上方形成的半导体管芯。封装件结构还包括覆盖半导体管芯的封装件层和在封装件层中形成的导电结构。封装件结构包括在导电结构上形成的第一绝缘层，并且第一绝缘层包括一价金属氧化物。封装件结构包括在第一绝缘层和封装件层之间形成的第二绝缘层。第二绝缘层包括一价金属氧化物，并且第二绝缘层中的一价金属氧化物的重量比大于第一绝缘层中的一价金属氧化物的重量比。
在一些实施例中，提供了封装件结构。封装件结构包括衬底和在衬底上方形成的半导体管芯。封装件结构还包括邻近半导体管芯的封装件层和在封装件层中形成的导电结构。封装件结构还包括在导电结构上形成的绝缘层。绝缘层包括邻近绝缘层的外表面的第一位置处的一价金属氧化物，并且其多于邻近与导电结构接触的内表面的第二位置处的一价金属氧化物。
在一些实施例中，提供了形成封装件结构的方法。方法包括在衬底上方形成导电结构并且在衬底上方形成半导体管芯。半导体管芯被导电结构包围。方法还包括在导电结构上实施湿工艺或等离子体工艺以在导电结构上方形成绝缘层。绝缘层包括在第一绝缘层上方的第二绝缘层，并且第一绝缘层和第二绝缘层都包括一价金属氧化物。第二绝缘层中的一价金属氧化物的重量比大于第一绝缘层中的一价金属氧化物的重量比。方法还包括在半导体管芯和第二绝缘层上方形成封装件层。
根据本发明的实施例，提供了一种封装件结构，包括：衬底；在衬底上方形成的半导体管芯；邻近半导体管芯的封装件层；在封装件层中形成的导电结构；在导电结构上形成的第一绝缘层，其中，第一绝缘层包括一价金属氧化物；以及在第一绝缘层和封装件层之间形成的第二绝缘层，其中，第二绝缘层包括一价金属氧化物，并且其中，第二绝缘层中的一价金属氧化物的重量比大于第一绝缘层中的一价金属氧化物的重量比。
根据本发明的实施例，导电结构包括金属材料，且一价金属氧化物包括与金属材料相同的金属元素。
根据本发明的实施例，第一绝缘层还包括二价金属氧化物，第二绝缘层还包括二价金属氧化物，且第二绝缘层中的二价金属氧化物的重量比小于第一绝缘层中的二价金属氧化物的重量比。
根据本发明的实施例，一价金属氧化物为氧化亚铜(Cu2O)，且二价金属氧化物为氧化铜(CuO)。
根据本发明的实施例，第二绝缘层中的一价金属氧化物的重量比在从约30wt％至约60wt％的范围内。
根据本发明的实施例，第二绝缘层的表面粗糙度大于第一绝缘层的表面粗糙度。
根据本发明的实施例，第二绝缘层与封装件层接触。
根据本发明的实施例，还包括：在封装件层上方形成的再分布层，其中，再分布层电连接至半导体管芯。
根据本发明的实施例，第一绝缘层为自然氧化物层。
根据本发明的实施例，提供了一种封装件结构，包括：衬底；在衬底上方形成的半导体管芯；邻近半导体管芯的封装件层；在封装件层中形成的导电结构；以及在导电结构上形成的绝缘层，其中，绝缘层包括邻近绝缘层的外表面的第一位置处的一价金属氧化物，并且在第一位置处的一价金属氧化物多于邻近与导电结构接触的内表面的第二位置处的一价金属氧化物。
根据本发明的实施例，导电结构包括金属材料，并且一价金属氧化物包括与金属材料相同的金属元素。
根据本发明的实施例，邻近绝缘层的外表面的一价金属氧化物的重量比为邻近绝缘层的内表面的一价金属氧化物的重量比的约1.5至约3倍。
根据本发明的实施例，还包括：在封装件层上方形成的再分布层，其中，再分布层电连接至半导体管芯。
根据本发明的实施例，提供了一种形成封装件结构的方法，包括：在衬底上方形成导电结构；在衬底上方形成半导体管芯，其中，半导体管芯被导电结构包围；在导电结构上实施湿工艺或等离子体工艺以在导电结构上方形成绝缘层，其中，绝缘层包括在第一绝缘层上方的第二绝缘层，其中，第一绝缘层和第二绝缘层都包括一价金属氧化物，并且第二绝缘层中的一价金属氧化物的重量比大于第一绝缘层中的一价金属氧化物的重量比；以及在半导体管芯和第二绝缘层上方形成封装件层。
根据本发明的实施例，在导电结构上实施湿工艺包括：将衬底放入化学浴中，其中，化学浴包括过氧化氢(H2O2)溶液。
根据本发明的实施例，过氧化氢(H2O2)溶液具有在约20wt％至约60wt％的范围内的浓度。
根据本发明的实施例，在导电结构上实施湿工艺之后，还包括：在导电结构上实施清洗工艺，其中，清洗工艺包括使用氮气(N2)。
根据本发明的实施例，还包括：形成在封装件层上方形成的再分布层，其中，将再分布层电连接至半导体管芯。
根据本发明的实施例，实施等离子体工艺包括：在导电结构上实施清洗工艺；以及在导电结构上实施主要等离子体工艺。
根据本发明的实施例，清洗工艺包括使用氮气(N2)，并且主要等离子体工艺包括使用氧气(O2)。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种封装件结构，包括：
衬底；
在所述衬底上方形成的半导体管芯；
邻近所述半导体管芯的封装件层；
在所述封装件层中形成的导电结构；
在所述导电结构上形成的第一绝缘层，其中，所述第一绝缘层包括一价金属氧化物；以及
在所述第一绝缘层和所述封装件层之间形成的第二绝缘层，其中，所述第二绝缘层包括一价金属氧化物，并且其中，所述第二绝缘层中的一价金属氧化物的重量比大于所述第一绝缘层中的一价金属氧化物的重量比。
2.根据权利要求1所述的封装件结构，其中，所述导电结构包括金属材料，且所述一价金属氧化物包括与所述金属材料相同的金属元素。
3.根据权利要求1所述的封装件结构，其中，所述第一绝缘层还包括二价金属氧化物，所述第二绝缘层还包括二价金属氧化物，且所述第二绝缘层中的二价金属氧化物的重量比小于所述第一绝缘层中的二价金属氧化物的重量比。
4.根据权利要求3所述的封装件结构，其中，所述一价金属氧化物为氧化亚铜(Cu2O)，且所述二价金属氧化物为氧化铜(CuO)。
5.根据权利要求1所述的封装件结构，其中，所述第二绝缘层中的一价金属氧化物的重量比在从约30wt％至约60wt％的范围内。
6.根据权利要求1所述的封装件结构，其中，所述第二绝缘层的表面粗糙度大于所述第一绝缘层的表面粗糙度。
7.根据权利要求1所述的封装件结构，其中，所述第二绝缘层与所述封装件层接触。
8.根据权利要求1所述的封装件结构，还包括：
在所述封装件层上方形成的再分布层，其中，所述再分布层电连接至所述半导体管芯。
9.一种封装件结构，包括：
衬底；
在所述衬底上方形成的半导体管芯；
邻近所述半导体管芯的封装件层；
在所述封装件层中形成的导电结构；以及
在所述导电结构上形成的绝缘层，其中，所述绝缘层包括邻近所述绝缘层的外表面的第一位置处的一价金属氧化物，并且在所述第一位置处的一价金属氧化物多于邻近与所述导电结构接触的内表面的第二位置处的一价金属氧化物。
10.一种形成封装件结构的方法，包括：
在衬底上方形成导电结构；
在所述衬底上方形成半导体管芯，其中，所述半导体管芯被所述导电结构包围；
在所述导电结构上实施湿工艺或等离子体工艺以在所述导电结构上方形成绝缘层，其中，所述绝缘层包括在第一绝缘层上方的第二绝缘层，其中，所述第一绝缘层和所述第二绝缘层都包括一价金属氧化物，并且所述第二绝缘层中的一价金属氧化物的重量比大于所述第一绝缘层中的一价金属氧化物的重量比；以及
在所述半导体管芯和所述第二绝缘层上方形成封装件层。
CN201610688826.0A 2015-12-16 2016-08-19 封装件结构及其形成方法 Active CN106887422B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/971,132 2015-12-16
US14/971,132 US9633924B1 (en) 2015-12-16 2015-12-16 Package structure and method for forming the same

Publications (2)

Publication Number Publication Date
CN106887422A true CN106887422A (zh) 2017-06-23
CN106887422B CN106887422B (zh) 2019-04-23

Family

ID=57352035

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201610688826.0A Active CN106887422B (zh) 2015-12-16 2016-08-19 封装件结构及其形成方法
CN201611074839.5A Active CN107039381B (zh) 2015-12-16 2016-11-29 半导体器件结构及其形成方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201611074839.5A Active CN107039381B (zh) 2015-12-16 2016-11-29 半导体器件结构及其形成方法

Country Status (5)

Country Link
US (6) US9633924B1 (zh)
KR (4) KR20170072104A (zh)
CN (2) CN106887422B (zh)
DE (2) DE102016100109B4 (zh)
TW (2) TWI607495B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113518905A (zh) * 2019-05-17 2021-10-19 贺利氏先进传感器技术有限公司 改进的高温芯片

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9633924B1 (en) 2015-12-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming the same
US9997471B2 (en) * 2016-07-25 2018-06-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
WO2019004264A1 (ja) 2017-06-30 2019-01-03 株式会社村田製作所 電子部品モジュール及びその製造方法
US10325854B2 (en) * 2017-07-18 2019-06-18 Advanced Semiconductor Engineering, Inc. Interposer and semiconductor package device
US10290611B2 (en) * 2017-07-27 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same
US10103107B1 (en) 2017-08-08 2018-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
KR102486561B1 (ko) * 2017-12-06 2023-01-10 삼성전자주식회사 재배선의 형성 방법 및 이를 이용하는 반도체 소자의 제조 방법
US10867919B2 (en) * 2018-09-19 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Electronic device and manufacturing method thereof
CN113196469B (zh) * 2018-12-21 2024-03-29 株式会社村田制作所 电子部件模块的制造方法及电子部件模块
US11984403B2 (en) * 2019-11-15 2024-05-14 Dyi-chung Hu Integrated substrate structure, redistribution structure, and manufacturing method thereof
KR20220026308A (ko) 2020-08-25 2022-03-04 삼성전자주식회사 반도체 패키지
KR20220047066A (ko) 2020-10-08 2022-04-15 삼성전자주식회사 반도체 패키지 장치

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1471161A (zh) * 2002-06-14 2004-01-28 ����ŷ�������ʽ���� 半导体器件及其制造方法
US20050285230A1 (en) * 2004-06-28 2005-12-29 Hyeong-Seob Kim Semiconductor package including a semiconductor device, and method of manufacturing the same
US20070020946A1 (en) * 2005-06-27 2007-01-25 Yasuo Tanaka Method for modifying surface of substrate and method for manufacturing semiconductor device
JP2010062175A (ja) * 2008-09-01 2010-03-18 Casio Comput Co Ltd 半導体装置の製造方法
CN102548248A (zh) * 2010-12-29 2012-07-04 三星电机株式会社 一种印制电路板及其制作方法
TW201419485A (zh) * 2012-11-14 2014-05-16 Taiwan Semiconductor Mfg 半導體晶粒封裝與其形成方法
CN103972191A (zh) * 2013-01-31 2014-08-06 台湾积体电路制造股份有限公司 具有环绕封装通孔端部的开口的管芯封装件及层叠封装件
US20140252647A1 (en) * 2013-03-08 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage Reduction and Adhesion Improvement of Semiconductor Die Package
CN104051378A (zh) * 2013-03-11 2014-09-17 台湾积体电路制造股份有限公司 用于封装的铜表面处理
US20140264853A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Adhesion between Post-Passivation Interconnect Structure and Polymer
CN104658989A (zh) * 2013-11-22 2015-05-27 台湾积体电路制造股份有限公司 形成封装件衬底的机制

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4234458A (en) 1979-04-23 1980-11-18 Uop Inc. Acidic multimetallic catalytic composite
US4946518A (en) 1989-03-14 1990-08-07 Motorola, Inc. Method for improving the adhesion of a plastic encapsulant to copper containing leadframes
JPH11233545A (ja) 1997-11-10 1999-08-27 Citizen Watch Co Ltd 半導体装置とその製造方法
KR100633678B1 (ko) 1998-02-26 2006-10-11 이비덴 가부시키가이샤 필드 바이어 구조를 갖는 다층프린트 배선판
US20020000657A1 (en) 1999-05-06 2002-01-03 Cheng P. Wen Plated chrome solder dam for high power mmics
JP4582892B2 (ja) 1999-11-11 2010-11-17 イビデン株式会社 多層プリント配線板およびその製造方法
JP4508380B2 (ja) 2000-08-23 2010-07-21 イビデン株式会社 多層プリント配線板の製造方法
JP2004022699A (ja) 2002-06-14 2004-01-22 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2004230690A (ja) * 2003-01-30 2004-08-19 Takiron Co Ltd 制電性透明樹脂板
JP2005071965A (ja) * 2003-08-28 2005-03-17 Mitsubishi Electric Corp 電界放出型冷陰極構造、その製造方法、及び平板型画像表示装置
EP1765964A4 (en) * 2004-04-30 2007-11-07 SYNTHESIS OF METALLIC SALTS OF MONOVALENT AND DIVALENT POLYUNSATURATED FATTY ACIDS
US8394679B2 (en) * 2004-05-28 2013-03-12 Stellarray, Inc. Nano-structured gasket for cold weld hermetic MEMS package and method of manufacture
US20090151972A1 (en) 2004-05-28 2009-06-18 Stellar Microdevices, Inc. Cold weld hermetic mems package and method of manufacture
US7365007B2 (en) 2004-06-30 2008-04-29 Intel Corporation Interconnects with direct metalization and conductive polymer
JP2006059676A (ja) * 2004-08-20 2006-03-02 Konica Minolta Holdings Inc 電子放出素子およびその製造方法
JP2006270031A (ja) 2005-02-25 2006-10-05 Casio Comput Co Ltd 半導体装置およびその製造方法
WO2008054541A2 (en) * 2006-05-19 2008-05-08 Massachusetts Institute Of Technology Nanostructure-reinforced composite articles and methods
JP5502268B2 (ja) * 2006-09-14 2014-05-28 信越化学工業株式会社 システムインパッケージ型半導体装置用の樹脂組成物セット
KR20090089384A (ko) * 2006-11-10 2009-08-21 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 모놀리식 세라믹 발광 변환기를 포함하는 조명 시스템, 복합 모놀리식 세라믹 발광 변환기 및 복합 모놀리식 세라믹 발광 변환기 제조 방법
US8178964B2 (en) * 2007-03-30 2012-05-15 Advanced Chip Engineering Technology, Inc. Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same
US8012886B2 (en) * 2007-03-07 2011-09-06 Asm Assembly Materials Ltd Leadframe treatment for enhancing adhesion of encapsulant thereto
US7648799B2 (en) * 2007-03-30 2010-01-19 Eveready Battery Co., Inc. Multi-layer positive electrode structures having a silver-containing layer for miniature cells
JP4498378B2 (ja) * 2007-03-30 2010-07-07 三洋電機株式会社 基板およびその製造方法、回路装置およびその製造方法
JP5286893B2 (ja) * 2007-04-27 2013-09-11 日立化成株式会社 接続端子、接続端子を用いた半導体パッケージ及び半導体パッケージの製造方法
KR101383357B1 (ko) * 2007-08-27 2014-04-10 엘지이노텍 주식회사 발광 소자 패키지 및 그 제조방법
US7858266B2 (en) * 2008-07-10 2010-12-28 Gm Global Technology Operations, Inc. Structural reinforcement of membrane electrodes
JP2010212492A (ja) 2009-03-11 2010-09-24 Tokyo Electron Ltd 半導体装置の製造方法
JP5584991B2 (ja) * 2009-04-02 2014-09-10 コニカミノルタ株式会社 透明電極、透明電極の製造方法、および有機エレクトロルミネッセンス素子
US20120153444A1 (en) * 2009-06-18 2012-06-21 Rohm Co., Ltd Semiconductor device
WO2010147187A1 (ja) * 2009-06-18 2010-12-23 ローム株式会社 半導体装置
CA2716144A1 (en) * 2009-10-02 2011-04-02 University Of Windsor Method of surface treatment of aluminum foil and its alloy and method of producing immobilized nanocatalyst of transition metal oxides and their alloys
JP2011114233A (ja) 2009-11-27 2011-06-09 Sony Corp 積層配線基板とその製造方法
US8455995B2 (en) * 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
JP2012216780A (ja) * 2011-03-31 2012-11-08 Ricoh Co Ltd ｐ型酸化物、ｐ型酸化物製造用組成物、ｐ型酸化物の製造方法、半導体素子、表示素子、画像表示装置、及びシステム
JP5200194B2 (ja) * 2011-06-24 2013-05-15 パナソニック株式会社 窒化ガリウム系半導体発光素子、光源および凹凸構造形成方法
EP2548841B1 (de) * 2011-07-19 2016-01-06 LITRONIK Batterietechnologie GmbH Aktivmaterial für eine Elektrode eines galvanischen Elements
JP5783094B2 (ja) * 2011-11-30 2015-09-24 株式会社リコー ｐ型酸化物、ｐ型酸化物製造用組成物、ｐ型酸化物の製造方法、半導体素子、表示素子、画像表示装置、及びシステム
JP5915370B2 (ja) * 2012-05-16 2016-05-11 ソニー株式会社 電気泳動素子、電気泳動表示装置、電子機器、及び、電気泳動素子の製造方法
US9273415B2 (en) * 2012-09-07 2016-03-01 International Business Machines Corporation Methods for preparing carbon hybrid materials
US8916981B2 (en) 2013-05-10 2014-12-23 Intel Corporation Epoxy-amine underfill materials for semiconductor packages
TWI533421B (zh) * 2013-06-14 2016-05-11 日月光半導體製造股份有限公司 半導體封裝結構及半導體製程
KR102154112B1 (ko) * 2013-08-01 2020-09-09 삼성전자주식회사 금속 배선들을 포함하는 반도체 장치 및 그 제조 방법
US8828100B1 (en) 2013-10-14 2014-09-09 John C. Warner Formulation and processes for hair coloring
US9331021B2 (en) 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9607959B2 (en) * 2014-08-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging device having plural microstructures disposed proximate to die mounting region
KR102285432B1 (ko) * 2014-11-18 2021-08-04 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 발광소자 패키지
US9583472B2 (en) * 2015-03-03 2017-02-28 Apple Inc. Fan out system in package and method for forming the same
KR102435855B1 (ko) * 2015-08-06 2022-08-25 삼성전자주식회사 하드 마스크 패턴의 형성 방법 및 이를 이용한 반도체 소자의 제조 방법
US9633924B1 (en) * 2015-12-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming the same
US9859222B1 (en) 2016-06-08 2018-01-02 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
DE102016117841A1 (de) * 2016-09-21 2018-03-22 HYUNDAI Motor Company 231 Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung
DE102016118784A1 (de) * 2016-10-04 2018-04-05 Infineon Technologies Ag Chipträger, konfiguriert zur delaminierungsfreien Kapselung und stabilen Sinterung

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1471161A (zh) * 2002-06-14 2004-01-28 ����ŷ�������ʽ���� 半导体器件及其制造方法
US20050285230A1 (en) * 2004-06-28 2005-12-29 Hyeong-Seob Kim Semiconductor package including a semiconductor device, and method of manufacturing the same
US20070020946A1 (en) * 2005-06-27 2007-01-25 Yasuo Tanaka Method for modifying surface of substrate and method for manufacturing semiconductor device
JP2010062175A (ja) * 2008-09-01 2010-03-18 Casio Comput Co Ltd 半導体装置の製造方法
CN102548248A (zh) * 2010-12-29 2012-07-04 三星电机株式会社 一种印制电路板及其制作方法
TW201419485A (zh) * 2012-11-14 2014-05-16 Taiwan Semiconductor Mfg 半導體晶粒封裝與其形成方法
CN103972191A (zh) * 2013-01-31 2014-08-06 台湾积体电路制造股份有限公司 具有环绕封装通孔端部的开口的管芯封装件及层叠封装件
US20140252647A1 (en) * 2013-03-08 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage Reduction and Adhesion Improvement of Semiconductor Die Package
CN104051378A (zh) * 2013-03-11 2014-09-17 台湾积体电路制造股份有限公司 用于封装的铜表面处理
US20140264853A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Adhesion between Post-Passivation Interconnect Structure and Polymer
CN104658989A (zh) * 2013-11-22 2015-05-27 台湾积体电路制造股份有限公司 形成封装件衬底的机制

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113518905A (zh) * 2019-05-17 2021-10-19 贺利氏先进传感器技术有限公司 改进的高温芯片

Also Published As

Publication number Publication date
US10163817B2 (en) 2018-12-25
KR101939531B1 (ko) 2019-01-16
US20190109098A1 (en) 2019-04-11
KR20170072105A (ko) 2017-06-26
CN107039381A (zh) 2017-08-11
TW201732902A (zh) 2017-09-16
US20180301424A1 (en) 2018-10-18
DE102016101287A1 (de) 2017-06-22
TWI607495B (zh) 2017-12-01
US9633924B1 (en) 2017-04-25
US10636748B2 (en) 2020-04-28
TWI618129B (zh) 2018-03-11
KR20180089332A (ko) 2018-08-08
TW201732903A (zh) 2017-09-16
KR20180021034A (ko) 2018-02-28
DE102016101287B4 (de) 2022-01-27
US10224293B2 (en) 2019-03-05
KR102026568B1 (ko) 2019-09-27
DE102016100109B4 (de) 2021-07-01
US20170179054A1 (en) 2017-06-22
US20170229404A1 (en) 2017-08-10
CN107039381B (zh) 2019-11-08
CN106887422B (zh) 2019-04-23
US9508664B1 (en) 2016-11-29
US10943873B2 (en) 2021-03-09
DE102016100109A1 (de) 2017-06-22
KR20170072104A (ko) 2017-06-26

Similar Documents

Publication Publication Date Title
CN106887422B (zh) 封装件结构及其形成方法
CN103681606B (zh) 三维(3d)扇出封装机制
US10269778B2 (en) Package on package (PoP) bonding structures
CN103972191B (zh) 具有环绕封装通孔端部的开口的管芯封装件及层叠封装件
CN103515305B (zh) 3d ic堆叠器件及制造方法
CN104979334B (zh) 半导体器件及方法
US10553458B2 (en) Chip packaging method
TWI553749B (zh) 封裝結構及其形成方法
CN110137151A (zh) 半导体器件和制造方法
CN105895616B (zh) 金属氧化物层状结构及其形成方法
CN107393865A (zh) 半导体器件
CN108122878A (zh) 芯片封装结构
CN109216219A (zh) 具有双侧金属布线的半导体封装件
US20110221054A1 (en) Semiconductor Device and Method of Forming Conductive Vias Through Interconnect Structures and Encapsulant of WLCSP
CN106356340A (zh) 半导体器件及其制造方法
CN104658989A (zh) 形成封装件衬底的机制
TW201203412A (en) Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation
SG178695A1 (en) Semiconductor device and method of formingbase leads from base substrate as standoff for stacking semiconductor die
US11069625B2 (en) Method for forming package structure
CN106571346A (zh) 用于芯片封装件的结构和形成方法
CN108122788A (zh) 半导体封装结构的制造方法
CN107342232A (zh) 晶片封装体的形成方法
TWI721184B (zh) 晶片封裝及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant