CN103515305B - 3d ic堆叠器件及制造方法 - Google Patents

3d ic堆叠器件及制造方法 Download PDF

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Publication number
CN103515305B
CN103515305B CN201210558608.7A CN201210558608A CN103515305B CN 103515305 B CN103515305 B CN 103515305B CN 201210558608 A CN201210558608 A CN 201210558608A CN 103515305 B CN103515305 B CN 103515305B
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semiconductor element
substrate
sealant
semiconductor
vias
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CN103515305A (zh
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林俊成
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了3D IC堆叠半导体器件及制造方法。在实施例中，两个或多个半导体管芯连接至载体并被封装。露出两个或更多半导体管芯的连接件，并且减薄两个或更多半导体管芯以在相对侧上形成连接件。然后，可以以偏离或悬突位置放置附加半导体管芯。

Description

3D IC堆叠器件及制造方法
本申请要求于2012年6月27日提交的标题为“3D IC Stacking Device andMethod of Manufacture”的美国临时专利申请第61/665,123号的优先权，其内容结合于此作为参考。
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及3D IC堆叠器件及制造方法。
背景技术
自从发明了集成电路(IC)，半导体行业就由于各种电子元件(即，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进而经历了快速发展。在很大程度上，集成密度的这种改进源于最小部件尺寸的反复减小，这允许将更多的元件集成到给定面积中。
实际上，这些集成改进基本上是二维(2D)的，因为集成元件所占的体积主要在半导体晶圆的表面上。虽然光刻的巨大改进在2D IC形成中引起相当大的改进，但能够二维实现的密度存在物理限制。一个这样的限制是制造这些元件所需的最小尺寸。而且，当将更多的器件置于一个芯片中时，需要更复杂的设计。
在进一步增加电路密度的努力中，研究出了三维(3D)IC。在3D IC的典型形成工艺中，两个管芯接合到一起并且在每个管芯和衬底上的接触焊盘之间形成电连接。例如，一种尝试涉及将两个管芯接合到对方的顶部。然后，堆叠的管芯被接合至载体衬底并且导线将每个管芯上的接触焊盘电连接至载体衬底上的接触焊盘。
发明内容
根据本发明的一个方面，提供了一种形成器件的方法，包括：在第一载体晶圆上放置一个或多个底部管芯；在一个或多个底部管芯之间形成第一模塑料，以露出一个或多个底部管芯上的电接触件；将一个或多个底部管芯和第一模塑料连接至第二载体晶圆；减薄一个或多个底部管芯以露出穿过一个或多个底部管芯形成的通孔；沿着一个或多个底部管芯的背面形成针对通孔的电接触件；以及将一个或多个顶部管芯连接至一个或多个底部管芯。
优选地，第一模塑料覆盖一个或多个底部管芯的底面。
优选地，形成第一模塑料包括减薄第一模塑料露出一个或多个底部管芯上的电接触件。
优选地，该方法还包括在一个或多个底部管芯上方形成再分布层。
优选地，再分布层在第一模塑料之上延伸。
优选地，该方法还包括形成在一个或多个底部管芯上方的第二模塑料。
根据本发明的另一方面，提供了一种制造半导体器件的方法，包括：第一半导体管芯连接至载体，第一半导体管芯包括第一外部接触件；将第二半导体管芯连接至载体，第二半导体管芯包括第二外部接触件；用密封剂封装第一半导体管芯和第二半导体管芯；去除部分密封剂以露出第一外部接触件和第二外部接触件；减薄第一半导体管芯和第二半导体管芯以在第一半导体管芯中形成第一衬底通孔以及在第二半导体管芯中形成第二衬底通孔；将第三半导体管芯电连接至第一衬底通孔并将第四半导体管芯电连接至第二衬底通孔。
优选地，该方法还包括封装第三半导体管芯和第四半导体管芯。
优选地，该方法还包括：在封装第三半导体管芯和第四半导体管芯之后，在第一外部接触件上形成第三外部接触件。
优选地，该方法还包括形成与第一外部接触件电连接的再分布层。
优选地，在减薄第一半导体管芯和第二半导体管芯之前形成再分布层。
优选地，该方法还包括：在将第三半导体管芯电连接至第一衬底通孔之后，形成与再分布层电连接的第三外部接触件。
优选地，将第三半导体管芯电连接至第一衬底通孔还包括使第三半导体管芯偏离第一半导体管芯。
优选地，在将第三半导体管芯电连接至第一衬底通孔之后，第三半导体管芯悬突于第一半导体管芯上方。
根据本发明的又一方面，提供了一种半导体器件，包括：第一半导体管芯，被第一密封剂封装；至少一个衬底通孔，延伸穿过第一半导体管芯的至少一部分并且在第一半导体管芯的第一侧上露出；第一外部连接件，位于第一半导体管芯的第二侧上；以及第三半导体管芯，与至少一个衬底通孔电连接，第三半导体管芯在密封剂上方延伸。
优选地，该半导体器件还包括：第二半导体管芯，被第一密封剂封装；以及第四半导体管芯，与第二半导体管芯电连接，第四半导体管芯在第一密封剂上方延伸。
优选地，通过第二密封剂封装第三半导体管芯与第四半导体管芯。
优选地，该半导体器件还包括与第一外部连接件电连接的第一再分布层，第一再分布层在第一密封剂上方延伸。
优选地，该半导体器件还包括与至少一个衬底通孔电连接的第二再分布层，第二再分布层在第一密封剂之上延伸。
优选地，第三半导体管芯偏离第一半导体管芯。
附图说明
为了更加完整地理解本发明及其优点，现在结合附图作为参考进行以下描述，其中：
图1至图10D示出了根据实施例的连接半导体器件的制造工艺；以及
图11至图13D示出了根据实施例的连接半导体器件的制造工艺的可选实施例；
除非另有说明，否则不同图中的对应数字和符号通常代表对应的部件。各附图清楚地示出实施例的相关方面并且不一定按比例绘制。
具体实施方式
下面详细描述本发明实施例的制造和使用。然而，应该理解，实施例提供许多可在各种具体环境中具体化的可应用的发明概念。所讨论的具体实施例仅仅是实施例的制造和使用具体方式的说明，但不限制本发明的范围。
在详细描述说明性实施例之前，大概描述实施例的各方面及其有利特征。如以下所示，本文公开的实施例提供了改进与顶部管芯外突(overhang，悬突)问题相关问题的方法和结构。例如，(衬底上芯片)上芯片(Co(CoS))会存在低产量和相对较高的成本的问题。衬底上(晶圆上芯片)((CoW)oS)技术对于外突顶部管芯是不实用的。衬底上(芯片上芯片)((CoC)oS)比((CoW)oS)的成本更高且比((CoW)oS)的产量更低。
概括来说，所示实施例提供了CoW工艺，其使得顶部管芯悬突或者顶部管芯大于底部管芯(w/TV管芯)。实施例还可以为CoWoS工艺提供解决方案并且可能跳过(skip)衬底以获得较低的组装成本。实施例可可以通过利用BGA技术进一步表现出较低的形状因数。
现在参照图1至图10B，提供第一个实施例。图1示出了具有涂覆在其上的第一粘合剂103的第一载体晶圆101。例如，第一载体晶圆101可包括玻璃、氧化硅、氧化铝等，并且可具有大于约12mil的厚度。可选地，第一载体晶圆101可包括合适的载带(carrier tape)。如果利用载带，则载带可以是公知的蓝带。
第一粘合剂103可用于将第一载体晶圆101粘合至其它器件，诸如第一半导体管芯201和第二半导体管芯203(图1未示出，但以下参照图2示出并讨论)。在实施例中，粘合剂可以是热剥离薄膜。可选地，第一粘合剂103可以是紫外线(UV)胶，当紫外线胶暴露于UV光时失去粘性。可以利用任何合适的粘合剂，并且所有这些粘合剂都完全包括在实施例的范围内。
图2示出了第一半导体管芯201(或第一底部管芯)和第二半导体管芯203(或第二底部管芯)利用第一粘合剂接合至第一载体晶圆101。第一半导体管芯201和第二半导体管芯203均可包括衬底205、衬底通孔(TSV) 开口207、有源器件209、金属化层211、接触焊盘213、第一钝化层215和第一外部连接件217。然而，虽然示出第一半导体管芯201和第二半导体管芯203具有类似的部件，但这只是说明性的而不用于限制实施例，因为第一半导体管芯201和第二半导体管芯203可具有类似的结构或不同结构以满足第一半导体管芯201和第二半导体管芯203所需的功能性能。
此外，虽然图2示出单个第一半导体管芯201和单个第二半导体管芯203，但这只是说明性的而不用于限制实施例。更确切地，单个第一半导体管芯201可代表一个或多个第一半导体管芯201，它们具有最终形成在其中的衬底通孔(TSV；以下参照图7进一步讨论)并且堆叠到一起。类似地，单个第二半导体管芯203可代表一个或多个第二半导体管芯203，它们具有最终形成在其中的TSV并且堆叠在一起。可以可选地利用任何合适数量的第一半导体管芯201和第二半导体管芯203，并且所有这种组合都完全包括在实施例的范围内。
衬底205可包括掺杂或非掺杂体硅或者绝缘体上硅(SOI)衬底的有源层并且可具有第一侧202和第二侧204。通常，SOI衬底包括半导体材料层，诸如硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。可使用的其它衬底包括多层衬底、梯度衬底或复合取向衬底。
衬底通孔(TSV)开口207可形成在衬底205的第一侧202中。可以通过施加并显影合适的光刻胶(未示出)并去除露出期望深度的衬底205来形成TSV开口207。可形成TSV开口207以至少比在衬底205内和/或衬底205上形成的有源器件209更深地延伸到衬底205中，并且可延伸至比衬底205的最终期望高度更大的深度。因此，虽然该深度取决于第一半导体管芯201和第二半导体管芯203的整体设计，但是从衬底205上的有源器件209开始该深度可在约20μm和约200μm之间，诸如从衬底205上的有源器件209开始约100μm的深度。
一旦在衬底205内形成TSV开口207，就可以用衬垫(在图2中没有单独示出)来对TSV开口207加衬。例如，衬垫可以是例如由正硅酸乙酯(TEOS)或氮化硅形成的氧化物，虽然可以可选地使用任何合适的介电材料。可以使用等离子体增强化学汽相沉积(PECVD)工艺形成衬垫，虽然 可以可选地使用其它任何合适的工艺，诸如物理汽相沉积或热工艺。此外，衬垫可以形成为大约0.1μm和大约5μm之间的厚度，诸如约1μm。
一旦沿TSV开口207的侧壁和底部形成衬垫，就可以形成势垒层(也没有单独示出)，并且TSV开口207的剩余部分可填充有第一导电材料219。第一导电材料219可包括铜，虽然可以可选地使用其它任何合适的材料，诸如铝、合金、掺杂多晶硅、它们的组合等。可通过将铜电镀到种子层(未示出)上，填充并过填充TSV开口207来形成第一导电材料219。一旦TSV开口207被填充，就可通过平坦化工艺(诸如化学机械抛光(CMP))去除TSV开口207外的过量衬垫、势垒层、种子层和第一导电材料219，尽管可以使用任何合适的去除工艺。
有源器件209在图2中表示为每个衬底205上的单个晶体管。然而，本领域技术人员应该理解，诸如电容器、电阻器、电感器等的各种有源器件和无源器件可用于为第一半导体管芯201和第二半导体管芯203产生设计的期望结构和功能需求。可使用任何合适的方法在衬底205的第一侧202内或第一侧202上形成有源器件209。
金属化层211形成在衬底205的第一侧202和有源器件209上方并被设计成连接各个有源器件209以形成功能电路。虽然图2示为电介质和互连件的单层，但是金属化层211还可以由交替的介电层和导电材料层形成，并且可通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在实施例中，可以存在通过至少一个层间介电层(ILD)与衬底205隔开的四个金属化层，但金属化层211的精确数量取决于第一半导体管芯201和第二半导体管芯203的设计。
接触焊盘213可形成在金属化层211上方并与其电接触。接触焊盘213可包括铝，但是可以可选择地使用其它材料，诸如铜。可通过以下方式形成接触焊盘213：使用诸如溅射的沉积工艺形成材料层(未示出)，然后通过合适的工艺(诸如光刻掩模和蚀刻)去除部分材料层来形成接触焊盘213。然而，任何其它合适的工艺可用于形成接触焊盘213。接触焊盘213可形成为具有约0.5μm和约4μm之间的厚度，诸如约1.45μm。
第一钝化层215可在金属化层211和接触垫片213之上形成在衬底205 上。第一钝化层215可由一种或多种合适的介电材料制成，诸如氧化硅、氮化硅、低k电介质(诸如掺碳氧化物)、极低k电介质(诸如多孔掺碳二氧化硅)、它们的组合等。可通过诸如化学汽相沉积(CVD)的工艺形成第一钝化层215，尽管还可以利用任何合适的工艺，并且第一钝化层215可具有约0.5μm和约5μm之间的厚度，诸如约
第二钝化层1002(为了清楚在图2中没有单独示出，但以下参照图10B以特写示图示出)可形成在第一钝化层215上方以提供进一步的保护。在实施例中，第二钝化层1002可由诸如聚酰亚胺的聚合物形成或者可以可选地由与第一钝化层215类似的材料形成(例如，氧化硅、氮化硅、低k电介质、极低k电介质、它们的组合等)。第二钝化层1002可形成为具有约2μm和约15μm之间的厚度，诸如约5μm。
可形成第一外部连接件217来为接触焊盘213和诸如印刷电路板或其它半导体管芯中外部器件(图2中未示出，例如具有倒装芯片配置)之间的接触提供导电区。第一外部连接件217还可用作诸如化学机械抛光(CMP)的平坦化工艺中的缓冲区。在实施例中，第一外部连接件217可以是导电柱，并且可以通过在第一钝化层215和第二钝化层1002上方最初形成光刻胶(未示出)而形成为约5μm至约20μm之间的厚度，诸如约10μm。可图案化光刻胶以露出第一钝化层215和第二钝化层1002的部分，导电柱将通过露出部分延伸。一旦被图案化，光刻胶就可以用作掩模以去除第一钝化层215和第二钝化层1002的期望部分，从而露出下面的接触焊盘213中将与导电柱接触的那些部分。
一旦露出接触焊盘213，第一UBM层1003(图2中没有单独示出，但以下参照图10B以特写图示出)可以形成为与接触焊盘213电接触。第一UBM层1003可包括导电材料层，诸如钛层或镍层。第一UBM层1003可包括多个子层(未示出)。本领域技术人员应理解，存在许多适合于形成第一UBM层1003的材料和层的适当配置，诸如铬/铬铜合金/铜/金的配置、钛/钛钨/铜的配置或铜/镍/金的配置。可用于第一UBM层1003的任何合适的材料或材料层完全包括在本实施例的范围内。根据期望的材料，可使用诸如溅射、蒸发或PECVD工艺的工艺制造第一UBM层1003。第一 UBM层1003可形成为具有约0.7μm和约10μm之间的厚度，诸如约5μm。
在形成第一UBM层1003之后，导电柱可形成在第一钝化层215、第二钝化层1002和光刻胶的开口内。导电柱可由诸如铜的导电材料形成，虽然也可使用其它导电材料，诸如镍、金或金属合金、它们的组合等。此外，可使用诸如电镀的工艺形成导电柱，其中，电流流经接触焊盘213期望形成导电柱的导电部分，并且接触焊盘213被浸入溶液。溶液和电流例如将铜沉积在开口内以填充和/或过填充光刻胶、第一钝化层215和第二钝化层1002的开口，从而形成导电柱。然后，可利用例如化学机械抛光(CMP)去除开口外过量的导电材料。
在形成导电柱之后，可通过诸如灰化的工艺去除光刻胶，增加光刻胶的温度直到光刻胶分解并且可被去除。在去除光刻胶之后，导电柱远离第一钝化层215和第二钝化层1002延伸约5μm至约50μm之间的距离，诸如40μm。可选地，可通过例如化学镀在导电柱之上形成势垒层(未示出)，其中，势垒层可由镍、钒(V)、铬(Cr)和它们的组合形成。
然而，本领域技术人员应理解，上述形成导电柱的工艺仅仅是示例性的，并不用于将实施例限制为该确切的工艺。相反，所描述的工艺仅仅是说明性的，可以可选地利用用于形成第一外部连接件217的任何合适的工艺。例如，并且还可以使用将第一钝化层215和第二钝化层1002形成为厚度大于它们最终的厚度，在第一钝化层215和第二钝化层1002的开口中形成导电柱，然后去除第一钝化层215和第二钝化层1002的顶部以使导电柱远离第一钝化层215和第二钝化层1002延伸。所有合适的工艺完全包括在本实施例的范围之内。
可选地，可在第一外部连接件217之上形成保护层221以保护第一外部连接件217。在实施例中，保护层221可以是诸如聚合物层的保护层，虽然还可以可选地利用任何合适的材料。保护层221可形成为具有约5μm和15μm之间的厚度，诸如约8μm。
图3示出了第一模制工艺以封装第一半导体管芯201和第二半导体管芯203，同时第一半导体管芯201和第二半导体管芯203保持固定至第一载体晶圆101。在实施例中，可利用例如模制器件(未示出)封装第一半 导体管芯201和第二半导体管芯203。例如，第一半导体管芯201、第二半导体管芯203和第一载体晶圆101可置于模制设备的腔内，并且可以密封腔。密封剂301可在腔被密封之前放置在腔内或可以通过注射口注入腔中。在实施例中，密封剂301可以是模塑料树脂，诸如聚酰亚胺、PPS、PEEK、PES、耐热水晶树脂、它们的组合等。
一旦密封剂301被放置到腔中使得密封剂301封装第一半导体管芯201和第二半导体管芯203，可固化密封剂301以硬化密封剂301用于最佳保护。虽然精确的固化工艺至少部分取决于密封剂301选择的特定材料，但在模塑料被选为密封剂301的实施例中，可通过将密封剂301加热到约100℃和约130℃之间(诸如约125℃)持续约60sec到约3000sec(诸如约600sec)的工艺进行固化。此外，引发剂和/或催化剂可包括在密封剂301内以更好地控制固化工艺。
然而，本领域技术人员应理解，上述固化工艺仅仅是示例性工艺并且不用于限制本实施例。可以可选地使用其它固化工艺，诸如照射或者甚至允许密封剂301在室温下变硬。可使用其它合适的固化工艺，并且所有这种工艺完全包括在本文讨论的实施例的范围内。
图4示出了去除密封剂301以露出第一外部连接件217。在实施例中，可使用例如化学机械抛光(CMP)工艺执行去除密封剂301，其中向密封剂301施加研磨剂和蚀刻剂并进行抛光以与密封剂301反应并且研磨掉密封剂301直到露出第一外部连接件217。可选地，可以利用一个或多个蚀刻工艺以去除密封剂301并利用第一外部连接件217平坦化密封剂301。
图5示出了从第一半导体管芯201和第二半导体管芯203去除第一载体晶圆101。虽然去除第一载体晶圆101至少部分地取决于所使用的第一粘合剂103的类型，但在第一粘合剂103是热剥离膜的实施例中，第一粘合剂103可被加热到大于约200℃的温度以从第一半导体管芯201和第二半导体管芯203剥离第一载体晶圆101。可以可选地利用去除第一载体晶圆101的任何其它合适的方法，诸如当第一粘合剂103是UV胶时利用UV光照射第一粘合剂103。
图6示出了利用第二粘合剂603将第二载体晶圆601连接至密封剂301 和第一外部连接件217。在实施例中，第二载体晶圆601和第二粘合剂603可以分别与第一载体晶圆101和第一粘合剂103类似，诸如可以是玻璃载体晶圆和热剥离膜。然而，第二载体晶圆601和第二粘合剂603可以可选地与第一载体晶圆101和第一粘合剂103不同。
图7示出了去除密封剂301和衬底205的第二侧204的部分以露出TSV开口207并形成TSV 701。在实施例中，可以使用例如CMP和研磨工艺去除密封剂301和衬底205的第二侧204，以去除密封剂301和衬底205的第二侧204的部分并且还平坦化密封剂301和衬底205的第二侧204。可选地，一种或多种蚀刻工艺或其它去除工艺还可用于去除密封剂301并露出TSV开口207以形成TSV 701。
图8示出了在衬底205的第二侧204上形成第一再分布层(RDL)801和第二外部连接件803。第一RDL 801可包括由诸如铝、铜、钨、钛和它们的组合的金属形成的两个导电层。可通过化学汽相沉积沉积金属层、然后蚀刻不需要的部分留下第一RDL 801来形成第一RDL801。第一RDL 801可以在约2μm和约30μm之间，诸如约5μm。然而，其它材料和工艺(诸如公知的镶嵌工艺)可以可选地用于形成第一RDL 801。
可选地，在实施例中，第一RDL 801不仅可以形成在第一半导体管芯201和第二半导体管芯203上方，而且还可以形成在密封剂301上方。通过在密封剂301之上形成第一RDL801，第一半导体管芯201和第二半导体管芯203的扇出区可延伸到第一半导体管芯201和第二半导体管芯203的边界之外，这还允许增加输入/输出(I/O)数。
第二外部连接件803可以是接触凸块(诸如微型凸块或可控坍塌芯片连接(C4)凸块)，并且可包括诸如锡的材料或诸如银或铜的其它合适的材料。在第二外部连接件803是锡焊料凸块的实施例中，第二外部连接件803可通过诸如蒸发、电镀、印刷、焊料转换、焊球放置等任何合适的方法最初形成锡层而形成为约100μm的优选厚度。一旦在结构上形成锡层，就进行回流以使材料成形为期望的凸块形状。
图9A示出了将第三半导体管芯901(或第三顶部管芯)和第四半导体管芯903(或第四顶部管芯)分别连接至第二半导体管芯203和第一半导 体管芯201。在实施例中，第三半导体管芯901和第四半导体管芯903可包含与第一半导体管芯201和第二半导体管芯203类似的有源器件、金属化层和接触焊盘(为了清楚均没有示出这些器件)，尽管它们还可以包含不同结构并且可以执行与它们所连接的半导体管芯不同或互补的功能。
在实施例中，第三半导体管芯901可大于下面的第二半导体管芯203。例如，在第二半导体管芯203可具有约3mm和约14mm之间(诸如约8mm)的第一长度l1的实施例中，第三半导体管芯901可具有约1mm和约20mm之间(诸如约10mm)的第二长度l2。通过具有大于第二半导体管芯203的尺寸，第三半导体管芯901可突出到第二半导体管芯203外。然而，密封剂301和RDL 801可用于为第二半导体管芯203和第三半导体管芯901提供支持和连接。
然而，本领域技术人员应该理解，如图9A所示第二长度l2大于第一长度l1是一个实施例，该描述仅仅是说明性的而不用于限制实施例。在其它实施例中，第二长度l2可大于、小于第一长度或等于第一长度l1。第一长度l1和第二长度l2的所有规格和尺寸完全包括在实施例的范围内。
在实施例中，第三半导体管芯901和第四半导体管芯903可通过首先使第三半导体管芯901与第二半导体管芯203对齐并且使第四半导体管芯903与第一半导体管芯201对齐来接合至第二半导体管芯203和第一半导体管芯201。一旦对齐，就可执行回流焊以回流第二外部连接件803的材料并将管芯接合到一起。然而，诸如铜铜接合的任何合适的接合方法可以可选地用于接合第一半导体管芯201、第二半导体管芯203、第三半导体管芯901和第四半导体管芯903。
可选地，图9A还示出了封装第三半导体管芯901和第四半导体管芯903。在实施例中，第二模制工艺可用于封装第三半导体管芯901和第四半导体管芯903，并且第二模制工艺可与用于封装第一半导体管芯201和第二半导体管芯203的第一模制工艺类似。例如，如上面参照图3描述的，密封剂301可与第一半导体管芯201、第二半导体管芯203、第三半导体管芯901和第四半导体管芯903一同被放置到模制室中。然而，虽然第二模制工艺可以与第一模制工艺类似，但是它可以可选地使用不同的材料和不 同的工艺并且依然在实施例的范围之内。
通过封装第三半导体管芯901和第四半导体管芯903，第一RDL 801可位于两组密封剂301之间。这样的位置有助于为不直接位于第一半导体管芯201、第二半导体管芯203、第三半导体管芯901和第四半导体管芯903之间的第一RDL 801的部分提供支持。通过提供更好的保护，可以减少或消除第一RDL 801将来的退化。
此外，可选地，用于封装第三半导体管芯901和第四半导体管芯903的密封剂301可以利用第三半导体管芯901和第四半导体管芯903进行平坦化以露出第三半导体管芯901和第四半导体管芯903。在实施例中，可使用例如CMP工艺来平坦化和去除密封剂301，以与密封剂301反应并研磨掉密封剂301直到露出第三半导体管芯901和第四半导体管芯903。
此外，虽然图9A仅示出了单个第三半导体管芯901和单个第四半导体管芯903，但这仅仅用于说明而不用于限制实施例。在可选实施例中，图9A所示单个第三半导体管芯901可表示期望电连接至第二半导体管芯203的多个半导体管芯。类似地，图9A所示单个第四半导体管芯903可表示期望电连接至第一半导体管芯201的多个半导体管芯。可以可选地使用第三半导体管芯901和第四半导体管芯903的任意数量的组合，并且所有这种组合完全包括在实施例范围之内。
图9B示出了第三半导体管芯901和第四半导体管芯903的可选放置。在这个实施例中，第三半导体管芯901和第四半导体管芯903不是简单地悬于第一半导体管芯201和第二半导体管芯203之上，而是与它们对应的管芯偏离放置。在实施例中，第三半导体管芯901和第四半导体管芯903可偏离约100um和约3mm之间的第一距离d1，诸如约1.5mm。
可选地，可在第一半导体管芯201、第二半导体管芯203、第三半导体管芯901和第四半导体管芯903之间的空间中注入或以其他方式形成底部填充材料905。例如，底部填充材料905可包括分散在第一半导体管芯201、第二半导体管芯203、第三半导体管芯901和第四半导体管芯903之间的液体环氧树脂，然后其被固化变硬。底部填充材料905可用于防止在第二外部连接件803中形成裂纹，其中通常由热应力产生裂纹。
可选地，为了帮助防止在第二外部连接件803内发生裂纹，可在第一半导体管芯201、第二半导体管芯203、第三半导体管芯901和第四半导体管芯903之间形成可变形凝胶或硅橡胶。可通过在第一半导体管芯201、第二半导体管芯203、第三半导体管芯901和第四半导体管芯903之间注入或以其他方式放置凝胶或硅橡胶来形成这种凝胶或硅橡胶。可变形凝胶或硅橡胶还可在后续工艺期间提供应力缓解。
图10A示出了去除第二载体晶圆601和第二粘合剂603，以及形成针对第一外部连接件217的第三外部连接件1001。在第二粘合剂603是热剥离膜的实施例中，可通过将第二粘合剂603的温度增加至大于约200℃来去除第二粘合剂603和第二载体晶圆601，使得可容易地去除第二载体晶圆601。可选地，在第二粘合剂603是UV胶的实施例中，可用UV光照射第二粘合剂603以去除第二载体晶圆601和第二粘合剂603。
一旦去除了第二载体晶圆601和第二粘合剂603，就可以形成第三外部连接件1001来与第一外部连接件217接触。在实施例中，第三外部连接件1001可以是诸如可控坍塌芯片连接(C4)凸块或微凸块的接触凸块，并且可包括诸如锡的材料或诸如银或铜的其它合适的材料。在第三外部连接件1001是锡焊料凸块的实施例中，第三外部连接件1001可通过诸如蒸发、电镀、印刷、焊料转换、焊球放置等任何合适的方法最初形成锡层而形成为约100μm的优选厚度。一旦在结构上形成锡层，就进行回流以使材料成形为期望的凸块形状。
图10A还示出了将第一半导体管芯201和第二半导体管芯203连接至第二衬底1022。第二衬底1022可用于支持并保护第一半导体管芯201和第二半导体管芯203，同时还用于提供第一半导体管芯201和第二半导体管芯203上的第三外部连接件1001与外部器件(未示出)之间的连接。在实施例中，第二衬底1022可以是印刷电路板或者可以是形成为诸如双马来亚酰胺(BT)、FR-4等的聚合物材料的多个薄层的叠层(或层压结构)的层压衬底。然而，可以可选地利用诸如有机衬底、陶瓷衬底等任何合适的衬底，并且为第一半导体管芯201和第二半导体管芯203提供支持和连接的所有这些衬底都完全包括在实施例的范围之内。
图10B示出了图10A中被虚线1020包围的部分的特写和更详细的视图。可以看出，第一外部连接件217穿过密封剂301远离第一UBM层1003延伸。如此，密封剂301可为第一外部连接件217提供附加支持和保护，同时还为第一半导体管芯201的剩余部分提供附加支持和保护。
图10C和10D示出了可选保护层221可用于保护第一外部连接件217的实施例。图10C示出了保护层221可使用例如平坦化工艺(诸如CMP工艺)形成为与第一外部连接件217的顶面平齐的实施例。图10D示出了保护层221保护第一外部连接件217的一部分但是不延伸到第一外部连接件217的顶面的可选实施例。
通过利用本文描述的实施例，晶圆上芯片工艺或衬底上晶圆上芯片工艺允许顶部管芯(例如，第三半导体管芯901或第四半导体管芯903)悬突于底部管芯(例如，第一半导体管芯201或第二半导体管芯203)之上或具有大于底部管芯的尺寸。这些实施例还允许通过使用球栅阵列连接第一半导体管芯201、第二半导体管芯203、第三半导体管芯901和第四半导体管芯903来减小形状因数并允许较大的处理灵活性，因为第一半导体管芯201和第二半导体管芯203可在连接至另一衬底(诸如印刷电路板)之前连接至第三半导体管芯901和第四半导体管芯903。这种灵活性意味着可消除或重新排列印刷电路板的连接，从而潜在地降低组装成本。
图11示出了在第一半导体管芯201和第二半导体管芯203的第一侧202之上形成第二RDL 1101的又一实施例。在实施例中，可以在去除密封剂301以露出第一外部连接件217之后以及在去除第一载体101之前形成第二RDL 1101。可以与参照图8描述的第一RDL 801类似的方式并使用类似的材料形成第二RDL 1101。例如，第二RDL 1101可包括由金属(诸如铝、铜、钨、钛和它们的组合)形成的两个导电层，并且可使用化学汽相沉积和图案化工艺形成。然而，可以可选地使用与第一RDL 801不同的材料和不同的工艺形成第二RDL 1101。
图12示出了在去除第一载体101并且第二载体晶圆601例如利用第二粘合剂603附接至第二RDL 1101、第一半导体管芯201和第二半导体管芯203变薄以形成TSV 701、第一RDL 801和第二外部连接件803形成在第 一半导体管芯201和第二半导体管芯203的第二侧204之上以及第三半导体管芯901和第四半导体管芯903接合至第一半导体管芯201和第二半导体管芯203之后得到的结构。
图13A和图13B示出了从第二RDL 1101去除第二载体晶圆601和第二粘合剂603以及形成与第二RDL 1101连接的第五外部连接件1307，图13B示出了图13A中被虚线框1320包围的部分的特写和更详细的视图。在第二粘合剂603是热剥离膜的实施例中，可通过增加第二粘合剂603的温度直到可以去除第二载体晶圆601来去除第二晶圆601。
一旦去除了第二载体晶圆601，就可在第二RDL 1101之上形成第三钝化层1301以为第二RDL 1101提供保护。第三钝化层1301可由一种或多种合适的介电材料制成，诸如氧化硅、氮化硅、低k电介质(诸如掺碳氧化物)、极低K介质(诸如多孔掺碳二氧化硅)、它们的组合等。可通过诸如化学汽相沉积(CVD)的工艺形成第三钝化层1301，虽然可利用任何合适的工艺，并且其可具有约0.5μm和约5μm之间的厚度，诸如约
第四钝化层1303可形成在第三钝化层1301之上以提供进一步的保护。在实施中，第四钝化层1303可以由诸如聚酰亚胺的聚合物形成，或者可以可选地由与第三钝化层1301类似的材料(例如，氧化硅、氮化硅、低k介质、极低k介质、它们的组合等)形成。第四钝化层1303可形成为具有约2μm和约15μm之间的厚度，诸如约5μm。
在形成第四钝化层1303之后，可使用例如光刻掩模和蚀刻工艺图案化第三钝化层1301和第四钝化层1303以露出第二RDL 1101的部分。一旦露出第二RDL 1101，第二UBM层1305就可形成为与第二RDL 1101电接触。第二UBM层1305可包括导电材料层，诸如钛层或镍层。第二UBM层1305可包括多个子层(未示出)。本领域技术人员应理解，存在许多适合形成第二UBM层1305的合适的材料和层的配置，诸如铬/铬-铜合金/铜/金的配置、钛/钛钨/铜的配置或铜/镍/金的配置。可用于第二UBM层1305的任何合适的材料或材料层完全旨在包括在本实施例的范围内。可根据期望的材料使用诸如溅射、蒸发或PECVD工艺的工艺制造第二UBM层1305。 第二UBM层1305可形成为具有约0.7μm和约10μm的厚度，诸如约5μm。
一旦形成第二UBM层1305，第五外部连接件1307就可形成为与第二RDL 1101电连接。第五外部连接件1307可以是诸如微凸块或可控坍塌芯片连接(C4)凸块的接触凸块并且可包括诸如锡的材料或诸如银或铜的其它合适的材料。在第五外部连接件1307是锡焊料凸块的实施例中，第五外部连接件1307可以通过任何合适的方法(诸如蒸发、电镀、印刷、焊料转换、焊球放置等)最初形成锡层而形成为具有约100μm的优选厚度。一旦在结构上形成锡层，就进行回流以使材料成形为期望的凸块形状。
图13C和图13D示出了可选保护层221可用于保护第一外部连接件217的实施例。图13C示出了保护层221可使用平坦化工艺(诸如CMP工艺)形成为与第一外部连接件217的顶面平齐的实施例。图13D示出了保护层221保护第一外部连接件217的一部分但并不一直延伸至第一外部连接件217的顶面的可选实施例。
可选地，虽然在图13A和图13B中没有示出，但第三半导体管芯901和第四半导体管芯903在该实施例中也可以被封装。在实施例中，可以与封装第一半导体管芯201和第二半导体管芯203(以上参照图3讨论)类似的方式封装第三半导体管芯901和第四半导体管芯903。然而，可选的密封剂或不同的方法可用于封装第三半导体管芯901和第四半导体管芯903。
通过使用以上参照图11-图13B描述的实施例，再分布层(例如，第一RDL 801和第二RDL 1101)可形成在第一半导体管芯201和第二半导体管芯203的两侧上。这允许根据需要实现连接件的控制和放置更大的扇出和更大的灵活性，因此，允许更大效率的放置和空间。
可选地，在以上参照图1至图13D讨论的每个实施例之后，实施例可进一步包括分割工艺(未单独示出)，其中包含例如第一半导体管芯201和第四半导体管芯903的第一封装件可与包含例如第二半导体管芯203和第三半导体管芯901的第二封装件分离。可通过使用例如金刚石涂层锯片切割第一封装件和第二封装件之间的划线区来执行切割工艺，虽然可以可选地使用任何合适的可选分离方法，诸如一系列的一种或多种蚀刻来分离 第一封装与第二封装。
根据实施例，提供一种形成器件的方法，该方法包括在第一载体晶圆上放置一个或多个底部管芯并在一个或多个底部管芯之间形成第一模塑料，使得露出一个或多个底部管芯上的电接触件。一个或多个底部管芯和第一模塑料连接至第二载体晶圆，并且减薄一个或多个底部管芯以露出穿过一个或多个底部管芯形成的通孔。沿着一个或多个底部管芯的背面形成针对通孔的电接触件，并且一个或多个顶部管芯连接至一个或多个底部管芯。
根据另一个实施例，提供了一种制造半导体器件的方法，包括：将第一半导体管芯连接至载体，第一半导体管芯包括第一外部接触件；并且将第二半导体管芯连接至载体，第二半导体管芯包括第二外部接触件。利用密封剂封装第一半导体管芯和第二半导体管芯，并且去除部分密封剂以露出第一外部接触件和第二外部接触件。减薄第一半导体管芯和第二半导体管芯以在第一半导体管芯中形成第一衬底通孔并且在第二半导体管芯中形成第二衬底通孔。第三半导体管芯电连接至第一衬底通孔，并且第四半导体管芯电连接至第二衬底通孔。
根据又一实施例，提供了一种半导体器件，包括通过第一密封剂封装的第一半导体管芯。至少一个衬底通孔延伸穿过第一半导体管芯的至少一部分并且在第一半导体管芯的第一侧上露出，第一外部连接件位于第一半导体管芯的第二侧上。第三半导体管芯与至少一个衬底通孔电连接，第三半导体管在密封剂之上延伸。
尽管已经详细描述了本发明及其优点，但应该理解，本文可以进行各种改变、替换和更改而不背离所附权利要求限定的实施例的精神和范围。此外，本申请的范围不旨在限于说明书中描述的工艺、机械装置、制造、物质组成、工具、方法和步骤的特定实施例。本领域技术人员很容易理解，根据本发明可以利用与本文描述的对应实施例执行基本相同功能或实现基本相同结果的目前现有或即将开发的工艺、机械装置、制造、物质组成、工具、方法或步骤。因此，所附权利要求旨在包括在这种工艺、机械装置、制造、物质组成、工具、方法、或步骤的范围内。

Claims (20)

1.一种形成器件的方法，包括：
在第一载体晶圆上放置一个或多个底部管芯；
在所述一个或多个底部管芯之间形成第一模塑料，以露出所述一个或多个底部管芯上的电接触件；
利用粘合剂将所述一个或多个底部管芯和所述第一模塑料连接至第二载体晶圆，其中，所述粘合剂与所述电接触件直接接触；
减薄所述一个或多个底部管芯以露出穿过所述一个或多个底部管芯形成的通孔；
沿着所述一个或多个底部管芯的背面形成针对所述通孔的电接触件；以及
将一个或多个顶部管芯连接至所述一个或多个底部管芯。
2.根据权利要求1所述的形成器件的方法，其中，所述第一模塑料覆盖所述一个或多个底部管芯的底面。
3.根据权利要求1所述的形成器件的方法，其中，形成所述第一模塑料包括减薄所述第一模塑料露出所述一个或多个底部管芯上的所述电接触件。
4.根据权利要求1所述的形成器件的方法，还包括在所述一个或多个底部管芯上方形成再分布层。
5.根据权利要求4所述的形成器件的方法，其中，所述再分布层在所述第一模塑料之上延伸。
6.根据权利要求1所述的形成器件的方法，还包括形成在所述一个或多个底部管芯上方的第二模塑料。
7.一种制造半导体器件的方法，所述方法包括：
将第一半导体管芯连接至载体，所述第一半导体管芯包括第一外部接触件；
将第二半导体管芯连接至所述载体，所述第二半导体管芯包括第二外部接触件；
用密封剂封装所述第一半导体管芯和所述第二半导体管芯；
去除部分所述密封剂以露出所述第一外部接触件和所述第二外部接触件；
利用粘合剂将所述第一半导体管芯和所述第二半导体管芯以及所述密封剂连接至载体晶圆，其中，所述粘合剂与所述第一外部接触件以及所述第二外部接触件直接接触；
减薄所述第一半导体管芯和所述第二半导体管芯以露出所述第一半导体管芯中的第一衬底通孔以及所述第二半导体管芯中的第二衬底通孔；
将第三半导体管芯电连接至所述第一衬底通孔并将第四半导体管芯电连接至所述第二衬底通孔。
8.根据权利要求7所述的制造半导体器件的方法，还包括封装所述第三半导体管芯和所述第四半导体管芯。
9.根据权利要求7所述的制造半导体器件的方法，还包括：在封装所述第三半导体管芯和所述第四半导体管芯之后，在所述第一外部接触件上形成第三外部接触件。
10.根据权利要求7所述的制造半导体器件的方法，还包括形成与所述第一外部接触件电连接的再分布层。
11.根据权利要求10所述的制造半导体器件的方法，其中，在减薄所述第一半导体管芯和所述第二半导体管芯之前形成所述再分布层。
12.根据权利要求10所述的制造半导体器件的方法，还包括：在将所述第三半导体管芯电连接至所述第一衬底通孔之后，形成与所述再分布层电连接的第三外部接触件。
13.根据权利要求7所述的制造半导体器件的方法，其中，将所述第三半导体管芯电连接至所述第一衬底通孔还包括使所述第三半导体管芯偏离所述第一半导体管芯。
14.根据权利要求7所述的制造半导体器件的方法，其中，在将所述第三半导体管芯电连接至所述第一衬底通孔之后，所述第三半导体管芯悬突于所述第一半导体管芯上方。
15.一种半导体器件，包括：
第一半导体管芯，被第一密封剂封装；
至少一个衬底通孔，延伸穿过所述第一半导体管芯的至少一部分并且在所述第一半导体管芯的第一侧上露出；
第一外部连接件，位于所述第一半导体管芯的第二侧上；以及
第三半导体管芯，通过位于所述第一半导体管芯的第二侧上的载体晶圆作为临时载体与所述至少一个衬底通孔电连接，所述第三半导体管芯在所述密封剂上方延伸；
其中，所述载体晶圆与所述第一半导体管芯中间设置有粘合剂，并且所述粘合剂与所述第一外部连接件直接接触。
16.根据权利要求15所述的半导体器件，还包括：
第二半导体管芯，被所述第一密封剂封装；以及
第四半导体管芯，与所述第二半导体管芯电连接，所述第四半导体管芯在所述第一密封剂上方延伸。
17.根据权利要求16所述的半导体器件，其中，通过第二密封剂封装所述第三半导体管芯与所述第四半导体管芯。
18.根据权利要求15所述的半导体器件，还包括与所述第一外部连接件电连接的第一再分布层，所述第一再分布层在所述第一密封剂上方延伸。
19.根据权利要求18所述的半导体器件，还包括与所述至少一个衬底通孔电连接的第二再分布层，所述第二再分布层在所述第一密封剂之上延伸。
20.根据权利要求15所述的半导体器件，其中，所述第三半导体管芯偏离所述第一半导体管芯。
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US10109613B2 (en) 2018-10-23
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