JP2007036104A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2007036104A JP2007036104A JP2005220652A JP2005220652A JP2007036104A JP 2007036104 A JP2007036104 A JP 2007036104A JP 2005220652 A JP2005220652 A JP 2005220652A JP 2005220652 A JP2005220652 A JP 2005220652A JP 2007036104 A JP2007036104 A JP 2007036104A
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Abstract
【解決手段】 配線チップ3と、第1の貫通電極5を有し配線チップ3の裏面に搭載された第1のLSIチップ2と、配線チップ3の表面にフリップチップ接続された第2のLSIチップとを備え、全体が一体的に樹脂封止されている。第1のLSIチップ2と第2のLSIチップ4は、配線チップ3に施された配線15を介して通信が行われる。第1のLSIチップ2と配線チップ3とは四辺が概ね揃うように積層される。第2のLSIチップ4は配線チップ3よりも四辺の寸法が小さく、配線チップ3の四辺よりも内側の領域に搭載されている。
【選択図】 図1
Description
2 第1のLSIチップ
3 配線チップ
4 第2のLSIチップ
5 第1の貫通電極
6 第2の貫通電極
10 モールド樹脂
13 接続端子
14 配線端子
15 配線
Claims (11)
- 配線が施された配線チップと、第1の貫通電極を有し前記配線チップの裏面に搭載された第1のLSIチップと、前記配線チップの表面にフリップチップ接続で搭載された第2のLSIチップと、を備え、
前記第1および第2のLSIチップは前記配線チップに施された前記配線を介して通信が行われ、
前記第1のLSIチップと前記配線チップとは四辺が概ね揃うように積層され、
前記第2のLSIチップは前記配線チップよりも四辺の寸法が小さく、前記配線チップの四辺よりも内側の領域に搭載されており、
前記第1のLSIチップおよび前記配線チップの側面と、第2のLSIチップの前記配線チップ側とは反対側の面とが一体的に樹脂封止されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記配線チップは第2の貫通電極を有し、前記第1のLSIチップの前記第1の貫通電極とフリップチップ接続されていることを特徴とする半導体装置。 - 請求項1または2に記載の半導体装置において、
外部端子を有する外部基板上に、前記第1のLSIチップ、前記配線チップおよび前記第2のLSIチップがこの順に積層され、前記複数の外部端子と前記第1の貫通電極とが電気的に接続され、外部基板、前記第1のLSIチップ、前記配線チップおよび前記第2のLSIチップが一体的に樹脂封止されていることを特徴とする半導体装置。 - 請求項1乃至3のいずれかに記載の半導体装置において、
前記第1のLSIチップはメモリLSIチップであり、前記第2のLSIチップはロジックLSIチップであることを特徴とする半導体装置。 - 請求項1乃至4のいずれかに記載の半導体装置において、
前記第1のLSIチップと同一形状の他の第1のLSIチップをさらに1つ以上有し、複数の前記第1のLSIチップ、前記配線チップおよび前記第2のLSIチップがこの順に積層されるとともに、前記複数の第1のLSIチップ同士は、上下に重なる位置の前記複数の第1の貫通電極同士が電気的に接続されていることを特徴とする半導体装置。 - 請求項2乃至5に記載の半導体装置において、
前記第1および第2の貫通電極は、前記第1のLSIチップおよび前記配線チップの中央領域と周辺領域とに集中的に配置されていることを特徴とする半導体装置。 - 配線が施された配線チップを準備する工程と、
第1の貫通電極を有する第1のLSIチップを準備する工程と、
前記配線チップよりも四辺の寸法が小さい第2のLSIチップを準備する工程と、を備え、
前記第1のLSIチップの上に前記配線チップを四辺が概ね揃うように積層し、
前記配線チップの四辺よりも内側の領域に前記第2のLSIチップを積層した後、
前記第1のLSIチップおよび前記配線チップの側面と、第2のLSIチップの前記配線チップ側とは反対側の面とを一体的に樹脂封止することを特徴とする半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
外部端子を有する外部基板を準備する工程をさらに有し、
前記外部基板の上に、前記第1のLSIチップ、前記配線チップおよび前記第2のLSIチップをこの順に積層した後、前記外部基板、前記第1のLSIチップ、前記配線チップおよび前記第2のLSIチップを一体的に樹脂封止することを特徴とする半導体装置の製造方法。 - 請求項7または8に記載の半導体装置の製造方法において、
前記第1のLSIチップが複数形成された第1の半導体ウエハを準備する工程と、
前記配線チップが複数形成された配線ウエハを準備する工程と、
前記第2のLSIチップを準備する工程と、を有し、
前記第1の半導体ウエハ上に前記配線ウエハを積層して前記第1の貫通電極と前記配線とを電気的に接続し、
前記配線ウエハ上に前記第2のLSIチップを積層して前記配線と前記第2のLSIチップを電気的に接続し、
その後、前記第1の半導体ウエハおよび前記配線ウエハを一括分割して、前記第1のLSIチップ、前記配線チップおよび前記第2のLSIチップがこの順に積層された状態とし、
その後前記第1のLSIチップ、前記配線チップおよび前記第2のLSIチップを樹脂封止することを特徴とする半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、
前記第1の半導体ウエハを複数準備し、
一の前記第1の半導体ウエハ上に他の前記第1の半導体ウエハを積層し、上下に重なる位置の前記第1の貫通電極同士を電気的に接続する工程を繰り返すことによって、前記複数の第1の半導体ウエハを積層する工程をさらに含むことを特徴とする半導体装置の製造方法。 - 請求項9または10に記載の半導体装置の製造方法において、
前記配線ウエハを準備する工程は、第2の貫通電極を形成する工程をさらに有し、
前記第1の貫通電極と前記配線との電気的接続が、前記第1の貫通電極と前記第2の貫通電極とをフリップチップ接続することによりなされることを特徴とする半導体装置の製造方法。
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