JP2005340389A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2005340389A JP2005340389A JP2004155143A JP2004155143A JP2005340389A JP 2005340389 A JP2005340389 A JP 2005340389A JP 2004155143 A JP2004155143 A JP 2004155143A JP 2004155143 A JP2004155143 A JP 2004155143A JP 2005340389 A JP2005340389 A JP 2005340389A
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- electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 281
- 238000004519 manufacturing process Methods 0.000 title claims description 47
- 238000000034 method Methods 0.000 claims abstract description 75
- 230000008569 process Effects 0.000 claims abstract description 37
- 238000007747 plating Methods 0.000 claims abstract description 26
- 239000004033 plastic Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 54
- 230000015654 memory Effects 0.000 claims description 18
- 230000006870 function Effects 0.000 claims description 3
- 238000000227 grinding Methods 0.000 abstract description 6
- 238000001312 dry etching Methods 0.000 abstract description 5
- 239000002344 surface layer Substances 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 1
- 230000035515 penetration Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 55
- 235000012431 wafers Nutrition 0.000 description 48
- 239000010410 layer Substances 0.000 description 31
- 229910052751 metal Inorganic materials 0.000 description 24
- 239000002184 metal Substances 0.000 description 24
- 239000000853 adhesive Substances 0.000 description 20
- 230000001070 adhesive effect Effects 0.000 description 20
- 239000010949 copper Substances 0.000 description 13
- 239000010931 gold Substances 0.000 description 13
- 229920005989 resin Polymers 0.000 description 13
- 239000011347 resin Substances 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000010409 thin film Substances 0.000 description 9
- 238000009713 electroplating Methods 0.000 description 8
- 238000003466 welding Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000009471 action Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005429 filling process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000012945 sealing adhesive Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229920002614 Polyether block amide Polymers 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
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- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract
【解決手段】
半導体チップ裏面を所定の厚さまでバックグラインド等によって薄型化し、デバイス側外部電極部に相当する裏面位置に、ドライエッチングにより表層電極に達するまでの孔を形成し、孔の側壁及び裏面側周囲に金属製のメッキ膜を施し、前記金属製のメッキ膜が施された貫通孔内部に、上段側に積層される別の半導体チップの金属製バンプ(突起状電極)を圧接によって変形注入させ、LSIチップ内に形成された貫通孔内部に前記金属製バンプを幾何学的にかしめて電気的に接続させる。
【効果】 非常に低コスト・短TATなプロセスで、かつ金属バンプの塑性流動変形を利用したかしめ作用により高い信頼性をもった独自の接続構造を実現することが可能であり、実用性の高い三次元のチップ間接続構造を提供。
【選択図】 図1
Description
(1)孔内部を電解メッキ等で充填するのではなく、薄膜の金属メッキを側壁含めた裏面側電極部に形成するだけなので、長時間を要するメッキ充填工程やその後のCMP(Chemical Mechanical Polishing)工程が不要となり、短TATかつ低コストなプロセスで製造できる、
(2)圧接時の塑性流動により貫通電極孔内への注入された金属バンプは、そのスプリングバック作用により、貫通電極孔内のメッキ電極部と安定した接合状態で維持される。また、金属バンプはSiに比べて線膨張係数が大きいため、リフロー加熱時にも熱膨張差によるかしめ状態が形成され、高温時においても安定した接続状態が維持される、
(3)チップ間の接続プロセスは従来の金のスタッドバンプを用いた圧接工法と同様な方法で対応できる、等がある。
(1)貫通孔内部を電解メッキ等でメッキ充填するのではなく、薄膜の金属メッキを側壁含めた裏面側電極部に形成するだけなので、長時間を要するメッキ充填工程やその後のCMP(Chemical Mechanical Polishing)工程が不要となり、短TATかつ低コストなプロセスで製造できる、
(2)圧接時の塑性流動により貫通電極孔内への注入された金属バンプは、そのスプリングバック作用により、貫通電極孔内のメッキ電極部と安定した接続状態維持される。さらに、金属バンプはSiに比べて線膨張係数が大きいため、リフロー加熱時にも熱膨張差によるかしめ状態が形成され、安定した接続状態が維持される、
(3)チップ間の接続プロセスは従来の金のスタッドバンプを用いた圧接工法と同様な方法で対応できる、等がある。すなわち、公知例で開示されている貫通電極を用いた接続方法に対比して、非常に低コスト・短TATなプロセスで、かつ金属バンプの塑性流動変形を利用したかしめ作用により高い信頼性をもった独自の接続構造を実現することが可能であり、実用性の高い三次元のチップ間接続構造を提供している。
図1乃至図14は、本発明の実施形態1である半導体装置に係わる図であり、
図1は、半導体装置の概略構成を示す模式的断面図、
図2は、図1の一部を拡大した模式的断面図、
図3は、図1の半導体チップの概略構成を示す模式的断面図、
図4は、図3の一部を拡大した模式的断面図、
図5乃至図10は、半導体装置の製造において、半導体チップの製造を説明するための図((a)は模式的平面図,(b)は模式的断面図)、
図11乃至図14は、半導体装置の製造において、組み立てプロセスを説明するための模式的断面図である。
半導体チップ1は、詳細に図示していないが、厚さ方向と交差する平面形状が方形状になっており、本実施形態1では例えば長方形になっている。
各々の半導体チップ1間は、アンダーフィル等の封止用接着材14によって封止され、機械的な強度を保持すると同時に外部環境から保護されている。
まず、半導体ウエハ20を準備する(図5参照)。半導体ウエハ20としては、例えば単結晶シリコンからなる半導体ウエハを用いる。
まず、図11(a)に示すように、配線基板10の主面のチップ搭載領域に、接着材13として例えばACFを貼り付ける(以下、ACF(13)と言うこともある)。
この後、半導体チップ1間に封止用樹脂14を充填し、その後、配線基板10の電極パッドに半田バンプ15を形成することにより、図1に示す半導体装置がほぼ完成する。
(1)貫通孔内部を電解メッキ等でメッキ充填するのではなく、薄膜の金属メッキを側壁含めた裏面側電極部に形成するだけなので、長時間を要するメッキ充填工程やその後のCMP(Chemical Mechanical Polishing)工程が不要となり、短TATかつ低コストなプロセスで製造できる。
(2)圧接時の塑性流動により貫通電極孔内への注入されたスタッドバンプは、そのスプリングバック作用により、貫通電極孔内のメッキ電極部と安定した接続状態維持される。さらに、金属バンプはSiに比べて線膨張係数が大きいため、リフロー加熱時にも熱膨張差によるかしめ状態が形成され、安定した接続状態が維持される。
(3)チップ間の接続プロセスは従来の金のスタッドバンプを用いた圧接工法と同様な方法で対応できる。
図15に示すように、貫通孔5の側壁面が鉛直方法の線に対して、外側に0度から5度程度傾いた形状に加工されるのは図4と同様であるが、奥行き方向の途中から、鉛直方向の線に対して内側に30度から60度程度傾いた形状に加工される。すなわち、孔の奥行き方向に対して、途中までは内径が同等もしくは増加する形状で加工され、奥行き方向の途中から、逆に内径が狭くなる形状で、複数の孔が加工される。これによって、電極パッド(デバイス側外部電極部)4とのコンタクト領域が小さくなるため、電極パッド(デバイス側外部電極部)4の強度を維持すると同時に電極(貫通電極部)6の熱応力による影響を小さくすることができる。
図16及び図17は、本発明の実施形態2である半導体装置の製造において、半導体チップの製造を説明するための模式的断面図である。
貫通孔5の内壁面を絶縁膜24で覆う方法として、前述の実施形態1では、貫通孔5の内壁面に沿う薄膜の絶縁膜24を形成することにより、貫通孔5の内壁面を絶縁膜24で覆う例について説明したが、本実施形態2では、貫通孔5の内部を絶縁膜5で一旦埋め込んで、貫通孔5の内壁面を絶縁膜24で覆う例につして説明する。
このように、本実施形態2においても、前述の実施形態1と同様に、半導体ウエハ20(半導体基板2)から電極6を絶縁分離させることができる。
図18は、本発明の実施形態3である半導体装置の製造において、組み立てプロセスを説明するための模式的断面図である。
前述の実施形態1では、配線基板10の主面に接着材13を介在して最下段の半導体チップ1(1a)を実装し、その後、最下段の半導体チップ(1a)上に順次3つの半導体チップ(1b,1c,1d)を積層してチップ積層体30を形成する例について説明したが、本実施形態3では、図18に示すように、先にチップ積層体30を形成し、その後、配線基板10の主面にチップ積層体30を実装する。チップ積層体30の実装は、最下段の半導体チップ1(1a)と配線基板10との間に接着材13を介在した状態で配線基板10にチップ積層体30を圧着して行う。
本実施形態3においても、前述の実施形態1と同様の効果が得られる。
図19は、本発明の実施形態4である半導体装置の概略構成を示す模式的断面図である。
前述の実施形態1では、最上段の半導体チップ1(1d)の電極6が露出する構造になっているが、本実施形態4の半導体装置は、図19に示すように、最上段の半導体チップ1(1d)の電極6が封止用接着剤14で覆われた構造になっている。このような構造にすることにより、半導体装置の信頼性を高めることができる。
図20は、本発明の実施形態5である半導体装置の概略構成を示す模式的断面図である。
本実施形態5の半導体装置は、図20に示すように、最上段に位置する半導体チップ1(1d)が他の半導体チップ1(1a,1b,1c)と異なる構造になっている。即ち、半導体チップ1(1a,1b,1c)には、貫通孔5及び電極6が設けられているが、最上段の半導体チップ1(1d)には、貫通孔5及び電極6が設けられていない。このような構造にすることにより、本実施形態5においても、半導体装置の信頼性を高めることができる。
図21は、本発明の実施形態6である半導体装置の概略構成を示す模式的断面図である。
実施形態6では、前述の実施形態1と基本構造及びその適用用途は同様であるが、貫通電極7を有する半導体チップ1の厚さが実施形態1に比べて厚い場合の実施形態を示す。電極(貫通電極部)6の孔内(凹部内)に圧接注入されるスタッドバンプ8が、裏面側電極部及び孔内の側壁電極部のみと機械的に接触または接合され、貫通孔内のデバイス側電極部(底辺部)、即ち電極パッド4とは直接接続されない。この場合、スタッドバンプ8の圧接注入時にバンプ先端が貫通孔内の底辺部まで達しないため、前記底辺部で金属バンプが再塑性流動変形して周辺方向に広がる効果が期待できない。したがって、ドライエッチングにより形成された孔は、図4、図15に示した孔形状とは異なり、孔径が深さ方向に対して同等か或いは若干狭くなるように形成され、鉛直方向の線に対して内側に数度傾いた孔形状に形成されるのが望ましい。これにより、スタッドバンプ8の圧接注入時に、貫通孔内の側壁部と安定した接触状態を実現することが可能となる。或いは、孔内部に形成される電解メッキ膜を底辺部(デバイス側外部電極とのコンタクト領域)のみ成長させることで、孔深さを実施形態1と同等レベルにした場合は、図4、図15で示した孔形状に加工されることでよい。
図22は、本発明の実施形態7である半導体装置の概略構成を示す模式的断面図である。
本実施形態7は異種の半導体チップを実施形態1に基づいて三次元積層された実施形態を示している。裏面1y側に電極(貫通電極部)6が形成された最下段の半導体チップ1は、電極バッド(デバイス側外部電極)4上にスタッドバンプ8が形成され、配線基板(搭載基板,パッケージ基板)10にスタッドバンプ8を介して電気的に接続される。最下段の半導体チップ1と異種の最上段の半導体チップ31間の電気的な接続は、その中間に再配線用のSiからなるインターポーザ基板32を積層することで実現される。インターポーザ基板32には、最下段の半導体チップ1の電極6に対応する位置にスタッドバンプ8が形成され、最上段の半導体チップ31のスタッドバンプ8に対応する位置に、実施形態1及び2と同様な電極(貫通電極部)6が形成される。両者間はインターポーザ基板32に形成された配線を介して電気的に接続され、最下段の半導体チップ1と最上段の異種の半導体チップ31は最短の配線長をもって電気的に三次元接続される。インターポーザ基板32には単に再配線のための配線パターンを形成するだけでなく、キャパシタの形成によって特性インピーダンスを整合させる配線設計等、高速信号伝送を考慮した配線パターンを構成できることは言うまでもない。例えば、最下段の半導体チップ1はギガヘルツ帯の周波数性能を持つ高性能マイコン(MPU)であり、最上段の半導体チップ31が高速メモリ(DRAM:Dynamic Random Access Memory))である場合、MPUとDRAM間の高速バス伝送設計を中間のSiインターポーザ32上で高密度・最短配線長で形成することができ、大容量メモリを混載したSOC(System On Chip)プロセスからなるシステムLSI代替の高性能システムを構築することが可能となる。通常、ボード実装のような長距離のチップ間接続を前提としているため、各チップの入出力回路の高速・低電力性を犠牲にしても、信号の駆動能力を高めているが、上記のような最短配線長のチップ間接続を実現することで、入出力回路の駆動能力をSOC並に低く設定することが可能となり、デバイスの高速伝送、低消費電力化を加速することができる。また、SRAM等のメモリを混載する場合、メモリの耐熱温度が一般のデバイスに比べて低いため、前記Siインターポーザ基板に、高性能マイコン(MPU)の発熱をメモリ側に伝達させにくい機能を持たせることも可能である。例えば、前記マイコンとSiインターポーザ基板との隙間を封止する樹脂に、通常のエポキシ系樹脂に比べて熱伝導率の低い材料を用いる、或いはSiインターポーザの表面に熱伝導率の低い材料をコーティングする等の手段がある。
図23は、本発明の実施形態8である半導体装置の概略構成を示す模式的断面図である。
本実施形態8は、実施形態7において、Siからなるインターポーザ基板32上に、2種類の異種半導体チップを混載積層した実施形態を示している。例えば、実施形態7と同様に最下段のチップ1はギガヘルツ帯の周波数性能を持つ高性能マイコン(MPU)であり、最上段のチップ31には高速メモリ(DRAM)とフラッシュメモリ(Flash)が混載されたシステムで、前記MPUとDRAM、Flash間は貫通電極7を介して最短配線長で電気的にそれぞれ接続される。実施形態7も同様であるが、最上層のDRAM及びFlashには電極(貫通電極7)6を形成する必要がなく、特に厚さの制約もないため、外部からチップを購入してシステムを構築することも容易である。
図24は、本発明の実施形態9である半導体装置の概略構成を示す模式的断面図である。
本実施形態9は、実施形態7において、Siからなるインターポーザ基板32を介して、前記上段側の半導体チップ31を実施形態1と同様に多数個積層した場合を示している。例えば、上段側の半導体チップ31をDRAMとした場合、本実施形態9によって、SOCでは実現困難な高速かつ大容量なメモリ混載のマイクロコントローラ(MPU)システムを実現することが可能となる。また、旧世代プロセスのメモリを多段積層することで、大容量化を図りながらも低コストかつ高歩留りなシステムを構築することも可能である。
図25は、本発明の実施形態10である半導体装置の製造を示す模式的断面図である。
本実施形態10では、最下段の半導体チップ33においては、デバイス側外部電極に対応する位置に実施形態1から9と同様、電極(貫通電極7)6が形成されている。デバイス側については実施形態1から9と異なり、配線基板(搭載基板,パッケージ基板)にスタッドバンプ8を介して電気的に接続されるのではなく、ウエハプロセス上で前記外部電極部からの再配線、絶縁膜(ポリイミド膜)形成及び外部電極(はんだバンプ)形成が実施される。すなわち、最下段の半導体チップ33は、一般にWPP(Wafer Process Package)と呼ばれるパッケージング技術を適用し、ウエハ状態のままパッケージングされたものである。最下段の半導体チップ33は、個片にダイシングされる前のウエハ状態のままで、前記裏面側に形成された電極6の孔内(凹部)に、上段側に積層される半導体チップ31の電極パッド(外部電極)4上に形成されたスタッドバンプ8が変形、注入され、電気的に接続される。複数枚の半導体チップ31が前記方式でウエハレベルで積層実装され、最後に各チップ積層エリアをアンダーフィル等の接着材14を用いて封止されるか、或いはウエハ状態のまま全体をトランスファーモールドレジンを用いて一括封止されてもよい。最後に個片ごとにダイシングされてパッケージングプロセスは完了する。本実施形態10においては、例えば実施形態7と同様に、WPPで構成された最下段の半導体チップ33はギガヘルツ帯の周波数性能を持つ高性能マイコン(MPU)であり、最上段の半導体チップ31が高速メモリ(DRAM)で、MPUとDRAM間の高速バス伝送を中間のSiインターポーザ32上で高密度・最短配線長で形成することができる。ただし、ウエハレベルでの積層実装であるため、最下段の半導体チップが上段側の半導体チップより個々のチップサイズが小さい場合には、上段側半導体チップが搭載不可となるため、その際には、最もチップサイズの大きい半導体チップか、或いはSiのインターポーザ基板32を最下段のWPPで構成することによって、ウエハレベルでの積層実装を可能とする。
図26は、本発明の実施形態11である半導体装置の製造において、上下の半導体チップ間の接続方法を示す模式的断面図である。
図4、図15において示した製造プロセスによって、電極6が形成された後、前記電極(裏面貫通電極)6が形成された側に、ウエハ状態のままシート状の接着材13が一面に貼り付けられ、前記接着材13を貼り付けた状態で個々の半導体チップ1にダイシングされる。各半導体チップ1はその裏面に接着材13が貼り付けられた状態でチップトレイ等に格納される。前記接着材13はデバイス回路面側にウエハ状態のまま貼り付けられた場合でもよい。ただし、搭載時の位置合わせ用アライメントマークの認識を困難する場合があるため、特に透明度の高い接着材である場合に限られる。各半導体チップ1を搭載する配線基板10は、例えば複数の半導体チップ1がエリアアレイ上に搭載できる構成で製造されており、各チップ搭載エリアには事前に同様な接着材13が貼り付けられ、図示のように、裏面に接着材が貼り付けられた各半導体チップ1は、下段側の半導体チップに形成された電極(裏面電極部)6の位置と、上段側の半導体チップに形成されたスタッドバンプ8との位置合わせを実施した状態で多段に積層され、最上段の半導体チップ1を積層する際にその位置合わせと同時に、圧接荷重またはそれと同時に超音波を印加することで、全チップ一括でチップ間接続が実施される。実施形態6においては、電極6の孔内部が実施形態1に比べて深いため、前記接着材13の一部がこの電極6に充填され、圧接注入されたスタッドバンプ8との隙間を埋める効果も期待される。実施形態6においては、アンダーフィル等の接着材を用いた例を示したが、この方法によれば、チップ間接続完了後の封止プロセスが不要となるため、プロセスの簡略化が可能となる。ただし、特に耐湿性を要する場合等、必要に応じてチップ搭載エリア全体をトランスファーモールドレジンによって再度封止されてもよい。
図27は、下段の半導体チップと上段の半導体チップ間のバンプ接続構造の例を示す。
本発明による基本的なチップ間接続構造は、上段に示した接続構造1であり、下段側チップ裏面に形成された電極6の孔内部に上段側半導体チップ上に形成されたスタッドバンプ8が圧接により注入充填され、幾何学的なかしめ状態が形成された接合構造である。しかしながら、設計上の制約から必ずしも下段側半導体チップの裏面電極位置と上段側半導体チップのスタッドバンプ位置とを一致させることが難しい場合も想定され、その場合には中段の図の接合構造2に示したように、裏面電極側に再配線エリアを形成し、それによって上下間のずれを補正して上下半導体チップ間を接続させてもよい。また、同様に設計上の制約から、裏面電極の孔径を十分に確保できない場合には、下段の接合構造3に示すように、金属バンプサイズに対して小さい貫通電極部の孔内部に前記金属バンプを圧接注入させてチップ間を接続させることも可能である。
図28は、本発明の実施形態13である半導体装置の製造において、半導体チップの製造工程を示す模式的断面図である。
(1)ウエハ状態のままデバイス側外部電極部またはそれに隣接した位置に、ドライエッチング(Deep-RIE)によりウエハ内部に複数の孔が形成され、プラズマCVD(Chemical Vapor Deposition)等によって、孔内部側壁に酸化絶縁膜が形成される。
(2)スタッドバンピング法により、Auのスタッドバンプが形成される。一度目のバンピングによるバンプは孔内部に充填され、二度目にバンピングされたバンプが外部電極として形成される。
(3)シリコンウエハが、前記孔内に充填されたバンプ位置までバックグラインド(BG)によって研削される。研削時に金属バンプ成分がウエハ面内に分布した場合には、簡単なエッチング及び洗浄処理が実施される。
(4)上段側半導体チップのスタッドバンプ(金属バンプ)が、圧縮荷重(及び超音波)を外部から印加されることによって、下段側半導体チップ裏面側の貫通バンプ領域を下部方向に変形させながら、前記金属バンプが孔内に変形、注入され上下チップ間が電気的に接続される。本実施形態では、メッキプロセスを不要とするため、プロセスの低コスト化が可能となる。
Claims (12)
- 第1の半導体チップと、前記第1の半導体チップ上に積層された第2の半導体チップとを有し、
前記第1の半導体チップは、互いに反対側に位置する主面及び裏面と、前記主面に配置された第1の電極と、前記裏面から前記第1の電極に達する貫通孔と、前記貫通孔の内壁面に沿って形成され、前記第1の電極と電気的に接続された第2の電極とを有し、
前記第2の半導体チップは、互いに反対側に位置する主面及び裏面と、前記主面に配置された第1の電極と、前記第1の電極上に配置され、前記主面から突出する突起状電極とを有し、
前記第2の半導体チップの突起状電極は、その一部が前記第1の半導体チップの第2の電極を介在して前記貫通孔の中に挿入され、前記第1の半導体チップの第1の電極と電気的に接続されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第2の電極は、メッキ膜からなることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第2の半導体チップの突起状電極は、その一部が塑性流動を伴う変形によって圧接注入されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記貫通孔の内径は、少なくともその一部が奥行き方向に対して広くなるように形成され、
前記突起状電極の一部は、その一部が塑性流動を伴う変形によって圧接注入され、幾何学的なかしめ状態になっていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記突起状電極は、Auスタッドバンプ、或いはAuメッキバンプであり、
前記第2の電極は、Cuメッキ膜及びAuメッキ膜からなることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第2の半導体チップは、更に、前記第2の半導体チップの裏面から前記第2の半導体チップの第1の電極に達する貫通孔と、前記貫通孔の内壁面に沿って形成され、前記第1の電極と電気的に接続された第2の電極とを有することを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1の半導体チップは、突起状電極を介在して配線基板に実装されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1及び第2の半導体チップは、同一機能の記憶回路が搭載されていることを特徴とする半導体装置。 - 第1の半導体チップと、前記第1の半導体チップ上にインターポーザ基板を介在して積層された第2の半導体チップとを有し、
前記第1の半導体チップは、互いに反対側に位置する主面及び裏面と、前記主面に配置された第1の電極と、前記裏面から前記第1の電極に達する貫通孔と、前記貫通孔の内壁面に沿って形成され、前記第1の電極と電気的に接続された第2の電極とを有し、
前記第2の半導体チップは、互いに反対側に位置する主面及び裏面と、前記主面に配置された第1の電極と、前記第1の電極上に配置され、前記主面から突出する突起状電極とを有し、
前記インターポーザ基板は、互いに反対側に位置する主面及び裏面と、前記主面に配置された第1の電極と、前記第1の電極上に配置され、前記主面から突出する突起状電極と、前記裏面から前記主面に向かって延びる貫通孔と、前記貫通孔の内壁面に沿って形成され、前記第1の電極と電気的に接続された第2の電極とを有し、
前記インターポーザ基板の突起状電極は、その一部が前記第1の半導体チップの第2の電極を介在して前記第1の半導体チップの貫通孔の中に、塑性流動を伴う変形によって圧接注入され、前記第1の半導体チップの第1の電極と電気的に接続されており、
前記第2の半導体チップの突起状電極は、その一部が前記インターポーザ基板の第2の電極を介在して前記インターポーザ基板の貫通孔の中に、塑性流動を伴う変形によって圧接注入され、前記インターポーザの第2の電極と電気的に接続されていることを特徴とする半導体装置。 - 請求項9に記載の半導体装置において、
前記第1の半導体チップは、マイクロコンピュータ或いはロジック回路が搭載され、
前記第2の半導体チップは、記憶回路が搭載されていることを特徴とする半導体装置。 - 主面に配置された第1の電極と、前記主面とは反対側の裏面から前記第1の電極に達する貫通孔と、前記貫通孔の内壁面に沿って形成され、前記第1の電極と電気的に接続された第2の電極とを有する第1の半導体チップと、
主面に配置された第1の電極と、前記第1の電極上に配置され、前記主面から突出する突起状電極とを有する第2の半導体チップとを準備する工程と、
前記第1の半導体チップの第2の電極を介在して前記第1の半導体チップの貫通孔の中に、前記第2の半導体チップの突起状電極の一部を塑性流動に伴う変形によって圧接注入する工程と、を有することを特徴とする半導体装置の製造方法。 - 主面に配置された第1の電極と、前記主面とは反対側の裏面から前記第1の電極に到達する貫通孔と、前記貫通孔の内壁面に沿って形成され、前記第1の電極と電気的に接続された第2の電極とを有する第1の半導体チップと、
主面に配置された第1の電極と、前記第1の電極上に配置され、前記主面から突出する突起状電極とを有する第2の半導体チップと、
主面に配置された第1の電極と、前記第1の電極上に配置され、前記主面から突出する突起状電極と、前記主面とは反対側の裏面から前記主面に向かって延びる貫通孔と、前記貫通孔の内壁面に沿って形成され、前記第1の電極と電気的に接続された第2の電極とを有するインターポーザ基板とを準備する工程と、
前記第1の半導体チップの第2の電極を介在して前記第1の半導体チップの貫通孔の中に、前記インターポーザ基板の突起状電極の一部を塑性流動に伴う変形によって圧接注入する工程と、
前記インターポーザ基板の第2の電極を介在して前記インターポーザ基板の貫通孔の中に、前記第2の半導体チップの突起状電極の一部を塑性流動に伴う変形によって圧接注入する工程と、を有することを特徴とする半導体装置の製造方法。
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