TWI469231B - 晶片封裝結構之製造方法 - Google Patents

晶片封裝結構之製造方法 Download PDF

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Publication number
TWI469231B
TWI469231B TW100132667A TW100132667A TWI469231B TW I469231 B TWI469231 B TW I469231B TW 100132667 A TW100132667 A TW 100132667A TW 100132667 A TW100132667 A TW 100132667A TW I469231 B TWI469231 B TW I469231B
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Taiwan
Prior art keywords
layer
package structure
chip package
wafer
conductive
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TW100132667A
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English (en)
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TW201312668A (zh
Inventor
Diann Fang Lin
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Dawning Leading Technology Inc
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Priority to TW100132667A priority Critical patent/TWI469231B/zh
Priority to CN201110359998.0A priority patent/CN103000541B/zh
Priority to US13/327,491 priority patent/US8962390B2/en
Publication of TW201312668A publication Critical patent/TW201312668A/zh
Application granted granted Critical
Publication of TWI469231B publication Critical patent/TWI469231B/zh

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Description

晶片封裝結構之製造方法
本發明是有關一種封裝結構之製造方法，特別關於一種晶片封裝結構之製造方法。
晶片封裝結構有許多種，而其中一種大致包括：一晶片及一基板，該晶片放置於基板上，且晶片的連接墊(pad)與基板的電路相互電性連接，而晶片及基板可選擇地再被一封裝膠體包覆住。中華民國專利證書號I343100所揭露者，即為上述的晶片封裝結構。
上述的晶片封裝結構已發展多年，故其技術較成熟，良率也較高。然而，因為該晶片封裝結構的基板是由多層材料堆疊而成，基板的厚度會較大，造成晶片封裝結構之整體厚度難以縮減到預期值。在電子產品薄型化的趨勢下，此種厚度較大的晶片封裝結構的應用將會受限。
有鑑於此，提供一種可改善至少一種上述缺失的晶片封裝結構之製造方法，乃為此業界亟待解決的嚴肅問題。
本發明之目的在於提供一種晶片封裝結構及其製造方法，所製造出的晶片封裝結構的基板可具有明顯更薄之厚度，以使得晶片封裝結構之厚度也減少。
為達上述目的，本發明的晶片封裝結構包含：一導電線路層；一黏著層，設置於該導電線路層上；以及一晶片，黏於該黏著層上，並電性連接該導電線路層。
為達上述目的，本發明的晶片封裝結構之製造方法包含：提供一保護層；形成一導電線路層於該保護層上；形成一黏著層於該導電線路層上；放置一晶片於該黏著層上；以及電性連接該晶片與該導電線路層。
為讓上述目的、技術特徵及優點能更明顯易懂，下文係以較佳之實施例配合所附圖式進行詳細說明。
請參閱第1圖所示，為本發明的晶片封裝結構的第一較佳實施例的一側視圖。第一較佳實施例的晶片封裝結構1包括：一保護層11、一導電線路層12、一黏著層13及一晶片14，各元件將依序說明如下。
保護層(protection layer)11為晶片封裝結構1的基層，可用以承載晶片封裝結構1的其它元件。保護層11由不會導通電能的材料所製成，例如樹脂、陶瓷等。
導電線路層(conductive trace layer)12設置於保護層11上，換言之，保護層11設置於導電線路層12下。導電線路層12非佈滿整個保護層11之上表面121，而是構成一特定之線路圖案。導電線路層12的製造材料可由包含銅等導電率良好的金屬材料所構成，且導電線路層12可藉由印刷、貼附或半導體製程(沈積、蝕刻等)等方式設置於保護層11上。
黏著層(adhesion layer)13設置於導電線路層12上，而本實施例中，黏著層13為直接地設置於導電線路層12上，因此黏著層13可接觸、覆蓋導電線路層12，並且還可接觸未被導電線路 層12覆蓋的部分之保護層11。此外，黏著層13可為黏性膠帶、可固化的黏膠等具有黏性且不會導通電能的物體，以使被黏著層13覆蓋的導電線路層12不會有短路之問題。
黏著層13中另定義有至少一貫穿孔131(本實施例為二個貫穿孔)，以使得導電線路層12的一上表面121可部分地暴露於貫穿孔131中；如此，其它物體(例如後述的金屬引線或金屬凸塊)可通過貫穿孔131，而接觸到導電線路層12的上表面121。
晶片14貼附於黏著層13上，使得製程中晶片14不易相對於黏著層13或導電線路層12造成移動。晶片14並進一步電性連接導電線路層12，使得晶片14可與導電線路層12相互電性傳遞(訊號或資料)。
本實施例中，晶片14與導電線路層12的電性連接是透過打線(wire bonding)方式來達成。詳言之，晶片封裝結構1另包含多個金屬引線16，金屬引線16的一端會焊接於晶片14的其中一個連接墊141上，而金屬引線16的另一端則會焊接於暴露於貫穿孔131中的導電線路層12之上表面121上，藉此導通連接墊141與導電線路層12。
本實施例之晶片封裝結構1與習知的相較，可具有較少的層數(例如導電線路層12與晶片14之間只有黏著層13)，故晶片封裝結構1的整體厚度也可較小，以適於應用於薄型化的電子產品。
以上為第一較佳實施例的晶片封裝結構1之說明，接著說明 本發明的晶片封裝結構的其它較佳實施例。為了簡潔說明之目的，其他較佳實施例與第一較佳實施例相似之處，以及其他較佳實施例之間的相似之處，皆將不再敘述之。
請參閱第2圖所示，其為本發明的晶片封裝結構之第二較佳實施例的一側視圖。第二較佳實施例的晶片封裝結構2與前述晶片封裝結構1之差異在於：晶片封裝結構2的黏著層13A中並不需定義貫穿孔。
詳言之，黏著層13A設置於部分的導電線路層12上，可僅分佈在晶片14之下方(無須滿板覆蓋於導電線路層12上)。如此，沒有被黏著層13A所覆蓋的導電線路層12便可直接進行後續製程。且由於不需額外再增加一形成貫穿孔的製程，故其製程時間及成本也可降低。
請參閱第3圖所示，其為本發明的晶片封裝結構之第三較佳實施例的一側視圖。第三較佳實施例的晶片封裝結構3與前述該等晶片封裝結構1、2之差異在於：晶片封裝結構3更包括一轉接元件(transfer element)15。
轉接元件15設置於晶片14上，且可透過打線方式來電性連接晶片14或導電線路層12。轉接元件15與晶片14之間也可設置另一黏著層(圖未示)，以使製程中轉接元件15不會相對於晶片14造成移動。轉接元件15可為電路板(軟性電路板、陶瓷電路板等)、晶片等可傳遞電能的元件，且轉接元件15之中或其上可形成或包含天線、電容器、電感器等電子元件裝置，以增加轉接元件15的功能。
請參閱第4圖所示，其為本發明的晶片封裝結構之第三較佳實施例的另一側視圖。轉接元件15可供另一晶片17設置於其上。由於轉接元件15可傳遞電能至晶片14或導電線路層12，晶片17的電能可透過轉接元件15傳遞至晶片14或導電線路層2。換言之，晶片17與導電線路層12之間可不需金屬引線來電性連接，因此第4圖所示的金屬引線16A實際上是可省略的。當金屬引線16A省略後，晶片封裝結構1的整體高度可大幅降低。可知，轉接元件15對於晶片封裝結構1而言，有降低整體封裝高度之功效。
請參閱第5圖所示，其為本發明的晶片封裝結構之第四較佳實施例的一側視圖。第四較佳實施例的晶片封裝結構4與前述該等晶片封裝結構1至3之差異在於：晶片封裝結構4更包括一絕緣層(isolation layer)18。
詳言之，絕緣層18設置於導電線路層12與黏著層13之間，使得黏著層13為間接地設置於導電線路層12上。絕緣層18可覆蓋整個導電線路層12，並同樣定義有貫穿孔181，使得導電線路層12的部分上表面121可暴露出。
請參閱第6圖所示，其為本發明的晶片封裝結構之第五較佳實施例的一側視圖。第五較佳實施例的晶片封裝結構5與前述晶片封裝結構1至4之差異在於：晶片14與導電線路層12的電性連接是透過覆晶(flip chip)方式來達成。
詳言之，晶片封裝結構5可包含多個金屬凸塊(metal bump)19，設置於黏著層13的貫穿孔131中及導電線路層12的 上表面121上，而晶片14的連接墊141則朝向、面對導電線路層12的上表面121。如此，金屬凸塊19可同時接觸晶片14的連接墊141與導電線路層12的上表面121，以導通連接墊141與導電線路層12。
請參閱第7圖所示，其為本發明的晶片封裝結構之第六較佳實施例的一側視圖。第六較佳實施例的晶片封裝結構6與前述晶片封裝結構1至5之差異在於：更包括一封裝膠體(encapsulation)20。該封裝膠體20至少可包覆晶片14、黏著層13及導電線路層12；若晶片封裝結構5包含轉接元件15、晶片17、金屬引線16或金屬凸塊19時，封裝膠體20也可一併將該等元件包覆住。被封裝膠體20包覆住的物體較不會受到外界環境的影響。
請參閱第8圖及9圖所示，分別為本發明的晶片封裝結構的第七較佳實施例的一側視圖。第七較佳實施例的晶片封裝結構7與前述晶片封裝結構1至6之差異在於：晶片封裝結構7的保護層11中定義有至少一貫穿孔111，使得導電線路層12的一下表面122部分地暴露於貫穿孔111中。
此外，晶片封裝結構7更包含至少一導電材料21A(如第8圖所示)或金屬凸塊21B(如第9圖所示)，設置於保護層11的貫穿孔111中，並接觸導電線路層12的下表面122。如此，導電材料21A(或金屬凸塊21B)可作為晶片封裝結構7與外部電子元件或電路板(圖未示)連接用的媒介。需說明的是，導電材料21A可略高於保護層11。
請參閱第10圖所示，其為本發明的晶片封裝結構之第八較佳實施例的一側視圖。第八較佳實施例的晶片封裝結構8與前述晶片封裝結構1至6之差異在於：晶片封裝結構8無包含保護層11，使得導電線路層12的下表面122可以皆露出。如此，導電線路層12之下表面122即可直接作為晶片封裝結構8與外部電子元件或電路板(圖未示)連接用的媒介。此外，因為沒有了保護層11，晶片封裝結構8的厚度可進一步地縮減。
以上為本發明的晶片封裝結構的各實施例之說明。接著說明本發明的晶片封裝結構之製造方法，該製造方法至少可製作出上述該等晶片封裝結構1至8。然而需說明的是，本發明的晶片封裝結構並不侷限由本發明的晶片封裝結構之製造方法來製作出。
請參閱第11圖所示，為本發明的晶片封裝結構之製造方法的第一較佳實施例的一流程圖。並請參閱第12A圖至12D圖所示，分別為第11圖的其中一個步驟的示意圖。本實施例的晶片封裝結構之製造方法可從步驟S101開始，也就是先提供一個保護層11(如第12A圖所示)。
接著形成一金屬層12A於保護層11上(步驟S103)，然後藉由蝕刻等方式移除部分之金屬層12A(步驟S105，如第12B圖所示)。沒有被移除之金屬層12A可構成一特定之線路圖案，也就是導電線路層12。除了步驟S103及S105外，仍有其它方式可形成導電線路層12於保護層11上，例如藉由印刷方式等。
導電線路層12形成後，接著可形成一黏著層13於導電線路 層12上(步驟S107，如第12C圖所示)。黏著層13可直接地形成在導電線路層12，以接觸導電線路層12及部分未被導電線路層12覆蓋的保護層11。
或者，在導電線路層12形成後，也可先形成一絕緣層18於導電線路層12上(步驟S109，如第12D圖所示)，再形成一黏著層13於絕緣層18上(步驟S111，如第12D圖所示)，使得黏著層13為間接地形成於導電線路層12上。
黏著層13直接或間接形成於導電線路層12上後，可藉由蝕刻等方式，移除部分的黏著層13，以在黏著層13中形成至少一貫穿孔131(步驟S113，如第1圖所示)。如此，導電線路層12的上表面121可部分地暴露於貫穿孔131中，以便於後續導電線路層12與晶片14的電性連接。若黏著層13僅形成於部分的導電線路層12上時(如第2圖所示)，則黏著層13可不用額外地被移除部分，換言之，步驟S113可視情況而省略。
下一步，放置一晶片14於黏著層13上，以使晶片14被黏著層13黏固，然後藉由打線或覆晶等方式，電性連接晶片14與導電線路層12(步驟S115，如第1圖或第6圖所示)。
晶片14與導電線路層12耦接後，接著可放置一轉接元件15於晶片14上，並且藉由打線或覆晶等方式，電性連接晶片14與轉接元件15(步驟S117，如第3圖所示)。之後，可放置另一晶片17於轉接元件15上(步驟S119，如第4圖所示)，並使晶片17與轉接元件15、晶片14及/或導電線路層12電性連接。
在步驟S115、S117或S119後，可將現階段完成的晶片封裝結構放入一模具(圖未示)中，然後注入一封裝膠體20。待封裝膠體20固化後，封裝膠體20可至少包覆晶片14、黏著層13及導電線路層12(步驟S121，如第7圖所示)。若晶片17或轉接元件15存在時，封裝膠體20也可一併將晶片17或轉接元件15包覆。
需說明的是，若欲製造的晶片封裝結構無封裝膠體20的需求，則步驟S121可省略。
在封裝膠體20固化後，可移除部分的保護層11，以在保護層11中形成至少一貫穿孔111(步驟S123，如第8圖或第9圖所示)。如此，導電線路層12的下表面122可部分地暴露於貫穿孔111中。接著，可設置至少一導電材料21A或金屬凸塊21B於貫穿孔111中，並使得導電材料21A或金屬凸塊21B接觸導電線路層12(步驟S125，如第8圖或第9圖所示)。
或者，在封裝膠體20固化後，可移除全部的保護層11，使得導電線路層12的下表面122皆暴露出(步驟S127，如第10圖所示)。
藉由上述晶片封裝結構之製造方法，各種晶片封裝結構可被製造出。
綜合上述，本發明的晶片封裝結構及晶片封裝結構之製造方法可至少具有以下特點：
1、因為晶片與導電金屬層之間可僅設有黏著層，故晶片封 裝結構之整體厚度可較少，以利應用於厚度較薄的電子產品中。
2、晶片封裝結構可包含轉接元件，以減少晶片的打線距離及打線高度。且轉接元件可包含天線、電容器、電感器等元件，以擴充晶片封裝結構的功能。
3、晶片封裝結構可不包含保護層，以進一步減少晶片封裝結構的厚度。
4、晶片封裝結構之製造方法可輕易地實施。
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。
1-8‧‧‧晶片封裝結構
11‧‧‧保護層
111‧‧‧貫穿孔
12‧‧‧導電線路層
121‧‧‧上表面
122‧‧‧下表面
12A‧‧‧金屬層
13‧‧‧黏著層
131‧‧‧貫穿孔
13A‧‧‧黏著層
14‧‧‧晶片
141‧‧‧連接墊
15‧‧‧轉接元件
16‧‧‧金屬引線
16A‧‧‧金屬引線
17‧‧‧晶片
18‧‧‧絕緣層
181‧‧‧貫穿孔
19‧‧‧金屬凸塊
20‧‧‧封裝膠體
21A‧‧‧導電材料
21B‧‧‧金屬凸塊
第1圖為本發明的晶片封裝結構之第一較佳實施例的一側視圖；第2圖為本發明的晶片封裝結構之第二較佳實施例的一側視圖；第3圖為本發明的晶片封裝結構之第三較佳實施例的一側視圖；第4圖為本發明的晶片封裝結構之第三較佳實施例的另一側視圖；第5圖為本發明的晶片封裝結構之第四較佳實施例的一側視圖；第6圖為本發明的晶片封裝結構之第五較佳實施例的一側視圖；第7圖為本發明的晶片封裝結構之第六較佳實施例的一側視圖； 第8圖為本發明的晶片封裝結構之第七較佳實施例的一側視圖；第9圖為本發明的晶片封裝結構之第七較佳實施例的另一側視圖；第10圖為本發明的晶片封裝結構之第八較佳實施例的一側視圖；第11圖為本發明的晶片封裝結構之製造方法之第一較佳實施例的一流程圖；第12A圖為第11圖的步驟S101的示意圖；第12B圖為第11圖的步驟S105的示意圖；第12C圖為第11圖的步驟S107的示意圖；及第12D圖為第11圖的步驟S111的示意圖。
1‧‧‧晶片封裝結構
11‧‧‧保護層
12‧‧‧導電線路層
121‧‧‧上表面
122‧‧‧下表面
13‧‧‧黏著層
131‧‧‧貫穿孔
14‧‧‧晶片
141‧‧‧連接墊
16‧‧‧金屬引線

Claims (8)

  1. 一種晶片封裝結構之製造方法，包含：提供一保護層，該保護層為非導電材料；形成一導電線路層於該保護層上；形成一黏著層於該導電線路層上；放置一晶片於該黏著層上；電性連接該晶片與該導電線路層；放置一轉接元件於該晶片上，並電性連結該晶片與該轉接元件，該轉接元件係為一電路板；以及移除全部的該保護層。
  2. 如請求項1所述的晶片封裝結構之製造方法，其中該黏著層直接地形成於該導電線路層上，以接觸該導電線路層。
  3. 如請求項1所述的晶片封裝結構之製造方法，更包含：形成一絕緣層於該導電線路層上；以及形成該黏著層於該絕緣層上。
  4. 如請求項1所述的晶片封裝結構之製造方法，其中該黏著層形成於部分的該導電線路層上。
  5. 如請求項1所述的晶片封裝結構之製造方法，更包含：移除部分的該黏著層，以形成至少一貫穿孔於該黏著層中，使得該導電線路層的一上表面部分地暴露於該貫穿孔中。
  6. 如請求項1所述的晶片封裝結構之製造方法，其中於「形成一導電線路層於該保護層上」的該步驟中，更包含：形成一金屬層於該保護層上；以及移除部分的該金屬層，以形成該導電線路層。
  7. 如請求項1所述的晶片封裝結構之製造方法，其中該晶片與該導電線路層以打線方式或覆晶方式，來達成電性連接。
  8. 如請求項1所述的晶片封裝結構之製造方法，更包含：使用一封裝膠體來包覆該晶片、該黏著層及該導電線路層。
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