US20130075894A1 - Integrated circuit and method of making - Google Patents
Integrated circuit and method of making Download PDFInfo
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- US20130075894A1 US20130075894A1 US13/563,345 US201213563345A US2013075894A1 US 20130075894 A1 US20130075894 A1 US 20130075894A1 US 201213563345 A US201213563345 A US 201213563345A US 2013075894 A1 US2013075894 A1 US 2013075894A1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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Abstract
Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends from the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. A conductive adhesive connects the conductive stud to the first side of the conductive layer.
Description
- This patent application claims priority to U.S. provisional patent application 61/538,365 filed on Aug. 23, 2011 for PERMANENT CARRIER AND PACKAGE INTERCONNECT METHOD USING MOLD AND DISTRIBUTE APPROACH and U.S. provisional patent application 61/596,617 for INTEGRATED CIRCUIT AND METHOD OF MAKING filed on Feb. 8, 2012, which are both incorporated by reference for all that is disclosed therein. This patent application is also a continuation-in-part of U.S. patent application Ser. No. 13/443,401 filed on Apr. 10, 2012 for INTEGRATED CIRCUIT AND METHOD OF MAKING and a continuation-in-part of U.S. patent application Ser. No. 13/481,275 filed on May 25, 2012 for INTEGRATED CIRCUIT AND METHOD OF MAKING, which are both incorporated by reference for all that is disclosed therein.
- Conventional integrated circuits have a die, which is a small circuit, electrically and/or mechanically connected to a lead frame or other connection mechanism. The electrical connection between the die and the lead frame typically consists of wire bonds connected between conductive pads on the die and conductors on the lead frame. The wire bonds are very small and delicate such that a small force applied to a wire bond can damage it. Therefore, extreme care must be taken when handling a circuit having wire bonds connected thereto. In addition to being very delicate, the wire bonds take time to connect, so they add to the cost and manufacturing time of the integrated circuit.
- Many high speed and high frequency circuit applications require short leads connecting a die to a lead frame. Short leads reduce the chance of the die encountering electromagnetic interference and they affect the parasitic inductance and capacitance associated with the leads. Wire bonds are relatively long and add to the parasitic capacitance and inductance of the connection between the die and the lead frame of an integrated circuit. Wire bonds are also susceptible to electromagnetic interference.
- After a conventional die is connected to a lead frame, the integrated circuit is encapsulated with an encapsulant. The encapsulation process is typically the final or near the final stage of fabrication of the integrated circuit. The encapsulant prevents contaminants from interfering with the integrated circuit. For example, the encapsulant prevents moisture from contaminating the die. The encapsulant also prevents the wire bonds from being damaged. Until the integrated circuit is encapsulated, the die, wire bonds, and other components are subject to failure by contact with contaminants. It follows that great care must be taken during the fabrication process in order to prevent the integrated circuits from being damaged prior to encapsulation.
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FIG. 1 is a side, cutaway view of an embodiment of an integrated circuit. -
FIG. 2 is an enlarged view of a portion of the printed wiring board of the circuit ofFIG. 1 attached to the die. -
FIG. 3 is an embodiment of a conductive stud used in the printed wiring board ofFIG. 2 . -
FIG. 4 is a flow chart describing an embodiment of a method of fabricating the circuit ofFIG. 1 . -
FIG. 5 is a side elevation view of the circuit ofFIG. 1 in the process of being fabricated wherein the die therein has been encapsulated. -
FIG. 6 is a bottom plan view of the circuit ofFIG. 5 . -
FIG. 7 is a flow chart describing an embodiment of a method of affixing the first dielectric layer to the circuit ofFIG. 1 . -
FIG. 7 is a side elevation view of a first dielectric layer adhered to a conductive layer. -
FIG. 8 is a side elevation view of the dielectric layer and the conductive layer ofFIG. 7 affixed to the circuit ofFIG. 5 wherein conductive studs on the die pierce the dielectric layer. -
FIG. 9 is a side elevation view of the circuit ofFIG. 8 with the conductive studs adhered to the conductive layer. -
FIG. 10 is a side elevation view of the circuit ofFIG. 9 with the conductive layer etched. -
FIG. 11 is a side elevation view of the circuit ofFIG. 10 with the addition of a second dielectric layer. -
FIG. 12 is a side elevation view of the circuit ofFIG. 11 with vias formed through the second dielectric layer. -
FIG. 13 is a flow chart describing another embodiment of fabricating the die ofFIG. 1 . - Circuits and methods of making circuits are disclosed herein. An embodiment of a circuit includes a die having a side. A conductive stud having a first end and an opposite second end is attached to the die, wherein the first end is connected to the side of the die and wherein the conductive stud extends from the side. A dielectric layer having a first side and a second side is attached to the side of the die, wherein the first side of the first dielectric layer is located proximate the side of the die so that the conductive stud extends into the dielectric layer from the first side. A conductive layer is located adjacent the second side of the dielectric layer and proximate the second end of the conductive stud. A conductive adhesive is adhered to the second side of the conductive stud and the conductive layer.
- Integrated circuits (sometimes referred to herein simply as “circuits”) and methods of making circuits are disclosed herein.
FIG. 1 is a side, cutaway view of acircuit 100. Thecircuit 100 includes anencapsulant 106, a die 108, a printedwiring board 110, and aconnection mechanism 112. Embodiments of methods for fabricating thecircuit 100 are described in greater detail further below. - The
encapsulant 106 may be a conventional encapsulant commonly used to encapsulate integrated circuits or electronic devices. In some embodiments, theencapsulant 106 is applied by a transfer mold process. Theencapsulant 106 has afirst side 120 and asecond side 122 located opposite thefirst side 120. Avoid 124 that is sized to receive thedie 108, as described in greater detail below, is located in thefirst side 120. In many embodiments, theencapsulant 106 is molded around the die 108, so thevoid 124 is a recessed portion of theencapsulant 106 that is formed at the location of thedie 108 during the encapsulation process. - The die 108 may be a conventional die that is commonly used in integrated circuits. The die 108 has a
first side 126 and an oppositesecond side 128. Thefirst side 126 of thedie 108 forms a substantially continuous flat surface with thefirst side 120 of theencapsulant 106. Circuits and/or electronic devices (not shown) may be located in or on thedie 108 in a conventional manner. For example, electronic devices may be fabricated on thesecond side 128. A plurality ofconductive pads 130 may be located on thefirst side 126. Theconductive pads 130 serve to electrically connect the die 108 to external devices or conductors. In some embodiments, theconductive pads 130 are contact points or the like that electrically and mechanically connect objects to thedie 108. Theconductive pads 130 may be very thin relative to other components of thecircuit 100, however, for illustration purposes, they are shown as being substantially thick. -
Conductive studs 132 are electrically and/or mechanically connected to theconductive pads 130. An enlarged view of a portion of thecircuit 100 is shown inFIG. 2 . The die 108 has aconductive stud 132 connected thereto, which is an example of all theconductive studs 132 ofFIG. 1 . Theconductive stud 132 may be substantially similar to a copper pillar or a copper bump and may be fabricated by a copper bump process. Theconductive stud 132 has afirst end 133 that is closest to the die 108 and asecond end 135 that is located opposite thefirst end 133. Theconductive stud 132 has aheight 137 measured from thefirst end 133 to thesecond end 135. - A second and similar embodiment of the attachment of the
stud 132 to the die 108 is shown inFIG. 3 . In the embodiment ofFIG. 3 , there is noconductive pad 130 located on thedie 108. Rather, theconductive stud 132 in this embodiment is affixed directly to thedie 108. For example, an under bump metal (not shown) may be applied to the die 108 to connect thestud 132 to thedie 108. Alternatively, theconductive stud 132 may be a copper pillar similar or identical to those used in die and integrated circuit cooling. In the embodiment ofFIG. 3 , thestud 132 extends a distance 139 from thesurface 126 of thedie 108. - The
second end 135 of theconductive stud 132 has aconductive adhesive 141 adhered thereto. Theconductive adhesive 141 may be a solder ball similar to those commonly used in integrated circuit, including flip chip, fabrication. In the embodiments where theconductive adhesive 141 is solder, the solder may be in a solid state except during periods when the solder is heated to attached it to other components as described below. - The printed
wiring board 110 is adhered to or fabricated to thefirst side 126 of thedie 108 and may also be adhered to or fabricated to thefirst side 120 of theencapsulant 106. The printedwiring board 110 may contain several layers. In the embodiment ofFIGS. 1-3 , the printedwiring board 110 has three layers, a firstdielectric layer 134, aconductive layer 136, and asecond dielectric layer 138. The printedwiring board 110 may be fabricated separate from thecircuit 100 and applied to the die 108 and theencapsulant 106 as a completed assembly. In other embodiments, the printedwiring board 110 is fabricated onto thedie 108 and theencapsulant 106. Both fabrication methods are described below. - Referring to
FIGS. 2 and 3 , thefirst dielectric layer 134 has afirst side 140 and asecond side 142. Thefirst side 140 is attached to or adhered to thefirst side 126 of thedie 108,FIG. 1 , and may also be attached to or adhered to thefirst side 120 of theencapsulant 106. Theconductive layer 136 may be substantially similar to a redistribution layer in a die. Theconductive layer 136 has afirst side 148 and asecond side 150, wherein thefirst side 148 is attached to or adhered to thesecond side 142 of thefirst dielectric layer 134. Theconductive layer 136 includesconductive material 144, such as copper, that serves as traces andnonconductive material 146 that is located between the conductive traces. Theconductive material 144 may be metal, such as a copper foil similar or identical to copper foil used in subtractive processing, or plated in semi-additive or full additive form. An example of a copper foil includes a one half to two ounce copper foil. In other embodiments, theconductive material 144 may be a foil having several layers, such as a copper/aluminum/copper foil. Thenonconductive material 146 may be portions of either the first dielectric layer or thesecond dielectric layer 138. - The first side of the 148 of the
conductive material 144 is adhered to theconductive adhesive 141. Accordingly, thefirst side 148 of theconductive material 144 and theconductive adhesive 141 are two materials that can bond or adhere to each other. Alternatively, thefirst side 148 of theconductive material 144 and thesecond side 135 of theconductive stud 132 are materials than can accept acommon adhesive 141 or bonding material. In some embodiments, thefirst side 148 of theconductive material 144 is a copper material and theconductive adhesive 141 is solder. When solder is used as theconductive adhesive 141 and copper is used on thefirst side 148 of theconductive material 144, the solder is heated to a liquid state and flows into the copper of theconductive material 144 forming an electrical and mechanical connection. - The
second dielectric layer 138 has afirst side 152 and asecond side 154, wherein thefirst side 152 is attached to or adhered to thesecond side 150 of theconductive layer 136. Both thefirst dielectric layer 134 and thesecond dielectric layer 138 may be insulating materials that are commonly used in circuits. - The printed
wiring board 110 serves to electrically and/or mechanically connect thedie 108 to theconnection mechanism 112. In order to achieve the electrical connections, a plurality of traces and vias may be located within the printedwiring board 110 to electrically connect thedie 108 to theconnection mechanism 112. - As shown in
FIGS. 1-3 , the use of theconductive studs 132 and theconductive adhesive 141 enables electrical connections through thefirst dielectric layer 134 without the use of vias. Rather, electrical connections are completed between the die 108 and theconductive layer 136 by way of theconductive studs 132. Theconductive adhesive 141 connects theconductive studs 132 directly to theconductive layer 136 without the use of vias. Accordingly, the fabrication of the connection between the die 108 and theconductive layer 136 is completed without using mechanical drilling, chemicals, or other processes to form via holes in or through thefirst dielectric layer 134, which could damage thedie 108 or thefirst dielectric layer 134. In addition, plating and/or the like to form vias in the holes is not required. - The
conductive layer 136 provides electrical conducting points at specific locations for theconnection mechanism 112 by way of theconductive material 144. In the embodiment ofFIGS. 1-3 , vias 158 extend through thesecond dielectric layer 138 between theconductive layer 136 and thesecond side 154 of thesecond dielectric layer 138. It is noted that theconnection mechanism 112 is electrically connected to thevias 158. Therefore, theconnection mechanism 112 is electrically connected to thedie 108. - The
connection mechanism 112 may include a plurality ofsolder balls 160 that are electrically and mechanically connected to a plurality ofconductors 162. Theconductors 162 may be substantially similar to under bump metal layers used in semiconductor fabrication. Theconductors 162 are electrically connected to thevias 158. It follows that electrical connections extend between thesolder balls 160 and theconductive pads 130 on thedie 108. It is noted that thesolder balls 160 andconductors 162 are examples of devices for connecting thevias 158 to external devices and that other devices, such as pins or wire bonds, may be used to electrically connect thevias 158 to external devices. - Having described the structure of the
circuit 100, methods of fabricating thecircuit 100 will now be described. The fabrication of thecircuit 100 commences with encapsulating thedie 108 as described atstep 302 of theflow chart 300. Thedie 108 is a conventional circuit that is fabricated onto a wafer or substrate and may be similar to the type commonly used in integrated circuits. Thedie 108 may be a complete circuit meaning that no further circuit fabrication is required. However, thedie 108 does need to be electrically connected to theconnection mechanism 112 in order to power thedie 108 and to send and receive signals as described below. - As described above, the
die 108 has or is connected toconductive studs 132 that serve to electrically connect thedie 108 to theconductive layer 136. Theconductive adhesive 141 is applied to thesecond end 135 of theconductive studs 132. In some embodiments, theconductive adhesive 141 is solder balls commonly used in the fabrication of flip chip devices and integrated circuit packages. - As previously mentioned, the
conductive studs 132 may be substantially similar to copper bumps or copper pillars of the type that are conventionally used for cooling dies and integrated circuits. In other embodiments, theconductive studs 132 may be affixed to or fabricated onto theconductive pads 130 or other electrical contact points on thedie 108 so as to be electrically and/or mechanically connected to thedie 108. Theconductive studs 132 may extend a distance 139,FIG. 3 , from thesurface 126 of thedie 108. The length of theconductive stud 132 with theconductive adhesive 141 is sized so that theconductive adhesive 141 is able to adhere to theconductive layer 136 and theconductive layer 136 is able to bond or contact thefirst dielectric layer 134. In some embodiments, the distance 139 is equal to or slightly less than thethickness 143 of thefirst dielectric layer 134. In some embodiments, thefirst dielectric layer 134 has athickness 143 of between ten and fifty microns. In such embodiments, theconductive studs 132 may extend a distance 139 of eight to forty-five microns from thesurface 126 of thedie 108. - The encapsulated die 108 is shown in
FIG. 5 , which is a side, cutaway, elevation view of thedie 108 and theencapsulant 106. A bottom plan view of the encapsulatedcircuit 100 ofFIG. 5 is shown inFIG. 6 . Theencapsulant 106 may be a conventional encapsulant used in the fabrication of integrated circuits. In some embodiments, a transfer mold technique is used to encapsulate thedie 108. Encapsulating thedie 108 at this stage of fabrication is unique. In conventional circuits, dies are not encapsulated until they are electrically connected to a connector or other connection device. For example, in flip-chip fabrication, the encapsulation process does not occur until a printed wiring board has been attached to the die. By encapsulating thedie 108 at this stage of fabrication of thecircuit 100, thedie 108 may be handled or otherwise maneuvered with a lower probability of being damaged. The encapsulated die 108 is also less likely to become damaged by contaminants. - In the embodiments described herein, the
entire die 108 except for thefirst side 126 is encapsulated. By encapsulating thedie 108, except for thefirst side 126, at this point during fabrication, thedie 108 is protected and theconductive studs 132 are accessible in order to connect theconductive layer 136 to thedie 108. As shown inFIGS. 5 and 6 , theencapsulant 106 may extend laterally beyond theedges die 108, which enables the completedcircuit 100 to fit snugly into larger packages. Afirst edge 172 of the encapsulant and afirst edge 125 of thedie 108 are spaced apart adistance 170. Asecond edge 176 of theencapsulant 106 and asecond edge 127 of thedie 108 are separated by adistance 174 as shown inFIG. 6 . Thedistances first side 120 of theencapsulant 106, which may be substantially planar. Thedie 108 may be located in theencapsulant 106 in such a manner that thefirst side 126 of thedie 108 and thefirst side 120 of theencapsulant 106 form a substantially planar and continuous surface. - The
encapsulant 106 may be applied to the die 108 by different methods. For example, a liquid encapsulant may be molded over thedie 108 and cured in a conventional manner. In other embodiments, a solid encapsulant may be formed with the void 124 located therein. Thedie 108 may be secured within the void 124 so that thedie 108 is effectively encapsulated by theencapsulant 106. In yet other embodiments, theencapsulant 106 is cured simultaneously with the curing of the printedwiring board 110 or components in the printedwiring board 110. In such embodiments, theencapsulant 106 may be cured to a stage-B or jell state at this stage of fabrication. After the printedwiring board 110 is attached to the die 108 and theencapsulant 106, theencapsulant 106 and components in the printedwiring board 110 may then be cured simultaneously. The simultaneous curing may enhance the bond between the printedwiring board 110 and theencapsulant 106. For example, theencapsulant 106 and thefirst dielectric layer 134 are able to flow together in their jell state and then fully cure together. In yet another embodiment, thesolder balls 141 are heated during the curing of the encapsulant so that they flow into theconductive layer 136. This embodiment accomplishes the curing of the encapsulant and the connection of theconductive studs 132 to theconductive layer 136 in a single step. - Several different embodiments of applying the printed
wiring board 110 to the die 108 will be described below. It is noted that the printedwiring board 110 replaces conventional wire bonds. Therefore, none of the embodiments of thecircuit 100 described herein require wire bonds or the like between the die 108 and theconnection mechanism 112. Accordingly, all the embodiments of the printedwiring board 110 enable very short distances between the die 108 and theconnection mechanism 112, which reduces the parasitic capacitance and inductance associated with the electrical connection between the die 108 and theconnection mechanism 112. - A first embodiment of applying the printed
wiring board 110 to thecircuit 100 commences with applying thefirst dielectric layer 134 to thefirst side 148 of theconductive layer 136 as described instep 304 of the flow chart and as shown inFIG. 7 . More specifically, thefirst dielectric layer 134 is adhered to thefirst side 148 of theconductive layer 136. Thefirst dielectric layer 134 may be laminated to theconductive layer 136 by a conventional low temperature vacuum lamination process. Thefirst dielectric layer 134 may be a non-fibrous dielectric material, such as an Ajinomoto build-up film (ABF), produced by Ajinomoto Fine-Techno Co, Inc of Japan and Ajinomoto North America, Inc. of Fort Lee, N.J., USA. Thefirst dielectric layer 134 may have athickness 143 of between ten and fifty microns. The material used in thefirst dielectric layer 134 may have a low viscosity prior to being cured. In order to keep thefirst dielectric layer 134 from sliding off theconductive layer 136 when it is in a state having a low viscosity, thefirst dielectric layer 134 may be cured to a B-stage wherein thefirst dielectric layer 134 has the viscosity of a jell. Such a curing enables thefirst dielectric layer 134 to be transported by way of the conductive layer and be adhered to the encapsulant 105 and die 108 as described below. - The
conductive layer 136 may be a metal, such as a copper foil. In some embodiments, theconductive layer 136 is a one half to two ounce copper foil. In other embodiments, theconductive layer 136 may be a foil having several layers, such as a copper/aluminum/copper foil. Theconductive layer 136 is used to apply thefirst dielectric layer 134 to theencapsulant 106 and thedie 108 by forming a rigid carrier to support thefirst dielectric layer 134 so that it can be pressed against theencapsulant 106 and thedie 108. - At this stage of fabrication, the
first dielectric layer 134 is adhered to theconductive layer 136. Thefirst dielectric layer 134 may then be transported or handled by using theconductive layer 136, which reduces the likelihood of damage to thefirst dielectric layer 134 during handling. The jell state of thefirst dielectric layer 134 enables it to be applied to thecircuit 100 as described atstep 306 of theflow chart 300, which yields thecircuit 100 as shown inFIG. 8 . Application of thefirst dielectric layer 134 to the die 108 may be accomplished by pressing thefirst dielectric layer 134 with the attachedconductive layer 136 onto thedie 108. It is noted that in some embodiments, a large sheet of a first dielectric layer is adhered to a plurality of dies, which are singulated during a later stage of fabrication. As thefirst dielectric layer 134 and theconductive layer 136 are pressed onto thedie 108, theconductive studs 132 pierce thefirst dielectric layer 134. In some embodiments, theconductive studs 132 pierce thefirst dielectric layer 134 to a distance that is proximate or contacting thefirst side 148conductive layer 136. - The
circuit 100 may be heated to cause theconductive adhesive 141 to flow or bond to thefirst side 148 of theconductive layer 136 as described instep 308 of theflow chart 300 and as shown inFIG. 9 . For example, if theconductive adhesive 141 is solder, thecircuit 100 may be heated, or theconductive layer 136 may be heated, to a temperature that causes the solder to flow into thefirst side 148 of theconductive layer 136. - The
first dielectric layer 134 and theencapsulant 106 may be cured simultaneously as described atstep 310 of theflow chart 300. The partially cured jell state of thefirst dielectric layer 134 enables it to be easily bonded to or located adjacent thedie 108 and theencapsulant 106 and reduces or eliminates the potential for voids between the surfaces. More specifically, if theencapsulant 106 is in a jell state, firstdielectric layer 134 and theencapsulant 106 may flow together for better bonding. The bonding may be accomplished by applying heat to thecircuit 100. In some embodiments, thecircuit 100 is heated to cause theconductive adhesive 141 to bond to theconductive layer 136 while simultaneously curing thefirst dielectric layer 136 and theencapsulant 106. - The
circuit 100 at this point in the fabrication process has thefirst dielectric layer 134 and theencapsulant 108 cured. Thefirst dielectric layer 134 is adhered to the die 108 and/or theencapsulant 108. The process of fabricating thecircuit 100 proceeds to step 312 of theflow chart 300 where theconductive layer 136 is etched to form traces similar or identical to a redistribution layer. The etching may be performed by a conventional etching process. The resultingcircuit 100 is shown inFIG. 10 . - As shown in
FIG. 10 , no vias are required to be formed between the die 108 and theconductive layer 136. Rather, theconductive studs 132 that are connected between the die 108 and theconductive layer 136 serve as vias, but they do not require holes to be formed through thefirst dielectric layer 134. It has been found that the process of forming holes in a layer in close proximity to the die 108 may damage thedie 108. - In some embodiments, the
circuit 100 as shown inFIG. 10 is complete. Thecircuit 100 is functional and may be connected to other devices by way of the printedwiring board 110. For example conductors may be connected to thesecond side 150 of theconductive layer 136 in order to electrically connect thecircuit 100 to other components. - In other embodiments of the
circuit 100, thesecond dielectric layer 138 is affixed to theconductive layer 136 as described instep 314 of theflow chart 300 and as shown inFIG. 11 . As described above, thesecond dielectric layer 138 has afirst side 152 and asecond side 154, wherein thefirst side 152 is adhered to or attached to theconductive layer 136. Thesecond dielectric layer 138 may be substantially the same material as thefirst dielectric layer 134. Thesecond dielectric layer 138 serves to protect theconductive layer 136 from damage during handling and from debris or other matter that may short or otherwise damage theconductive layer 134. In addition, thesecond dielectric layer 138 serves to support theconnection mechanism 112. - The
vias 158 are formed in thesecond dielectric layer 138 as described instep 316 of theflow chart 300 and as shown inFIG. 12 . Thevias 158 extend between thefirst side 152 and thesecond side 154 of thesecond dielectric layer 138. Thevias 158 are fabricated by forming holes through thesecond dielectric layer 138 wherein the holes contact specific portions of theconductive material 144 of theconductive layer 136. The holes may be formed in the same way as the holes that are formed in thefirst dielectric layer 134 to fabricate thevias 156. Likewise, the holes may be filled with or plated with a conductive material to form thevias 158. - The
circuit 100 now has an encapsulateddie 108 with electrical connections between the die 108 and thesecond side 154 of the seconddielectric material 138. Theconnection mechanism 112 may now be affixed to thesecond side 154 of the seconddielectric material 138 as described instep 318 of theflow chart 300 and as shown inFIG. 1 . Theconnection mechanism 112 electrically and/or mechanically connects thecircuit 100 to other devices. For example, theconnection mechanism 112 may provide input and output signals to and from thedie 108. Theconnection mechanism 112 may also enable thecircuit 100 to be physically attached to a substrate (not shown), such as a printed circuit board, or other physical structure. - As briefly described above, the
connection mechanism 112 may include a plurality ofconductors 162 that are attached to thesecond side 154 of thesecond dielectric layer 138. Theconductors 162 are electrically connected to thevias 158 in order to provide electrical connections to thedie 108. Theconductors 162 may be conventional metal layers, such as under bump metal layers that are commonly used to supportsolder balls 160. Thesolder balls 160 may be attached to theconductors 162 in a conventional manner. - The
circuit 100 has many advantages over conventional integrated circuits. For example, thecircuit 100 was encapsulated early in the production process. Therefore, thecircuit 100 may be handled and maneuvered with a lower probability of becoming damaged during the remaining production processes. In addition, thecircuit 100 is less susceptible to damage from contaminants during production. - The die 108 of the
circuit 100 is less likely to be damaged by the formation of vias extending to the die 108 as are required in conventional circuit. As described above, no holes are required to be formed in thefirst dielectric layer 134. Instead of holes and vias, theconductive studs 132 connect the die 108 directly to theconductive layer 136. Therefore, the time required to fabricate thecircuit 100 is reduced by not having to form the vias. In addition, theconductive adhesive 141 can be cured to thefirst side 148 of theconductive layer 136 simultaneous to the curing of thefirst dielectric layer 134 and theencapsulant 106. - Electrically, the
circuit 100 has many benefits over conventional integrated circuits. Thecircuit 100 does not require any wire bonds. Therefore, thecircuit 100 is not subject to the increased parasitic capacitance or inductance associated with wire bonds. In addition, theconductive layer 136 enables the lead lengths between theconductive pads 130 on thedie 108 and theconnection mechanism 112 to be very short. The short distance reduces the electromagnetic interference that thecircuit 100 is subject to. It follows that thecircuit 100 is better suited to operate in high frequency, high speed, and low power applications. - Having described some embodiments of fabricating the
circuit 100, other embodiments, will now be described. In some embodiments, thefirst dielectric layer 134 is applied directly to the die 108 and theencapsulant 106 without the use of theconductive layer 136,FIG. 7 . In such an application, thecircuit 100 may be positioned so that thefirst side 120 of theencapsulant 106 and thefirst side 126 of thedie 108 are facing up. Thefirst dielectric layer 134 may then be applied to thefirst surface 120 of theencapsulant 106 and thefirst surface 126 of thedie 108. Thefirst dielectric layer 134 may then be cured wherein the curing may also simultaneously cure theencapsulant 106. In this embodiment, thefirst dielectric layer 134 is fabricated onto thedie 108 with theconductive studs 132 located proximate thesecond side 142 of thefirst dielectric layer 134. Theconductive adhesive 141 may be applied to thesecond sides 135 of theconductive studs 132 at this time. Fabrication of thecircuit 100 may continue by applying theconductive layer 136 to thesecond side 142 of thefirst dielectric layer 134 so that thefirst side 148 of theconductive layer 136 bonds to theconductive adhesive 141. - In another embodiment of the fabrication process, the
conductive adhesive 141 is located on thefirst side 148 of theconductive layer 136. Theconductive studs 132 are forced into theconductive adhesive 141 as theconductive layer 136 is placed onto thefirst dielectric layer 134. - In other embodiments, heat spreaders are used in conjunction with or as an alternative to the
encapsulant 106. For example, thedie 108 may be located in a heat spreader prior to encapsulation. Alternatively, thedie 108 may be located in a heat spreader in lieu of encapsulation. - It will be appreciated from the above description that a method of fabricating a circuit may comprise the method set forth in the
flow chart 400 ofFIG. 13 with additional reference toFIG. 1 . The method commences atstep 402 with providing adie 108 wherein thedie 108 has aside 126. The method continues atstep 404 with connecting aconductive stud 132 to theside 126 of thedie 108, wherein theconductive stud 132 has afirst end 133 that is connected to the die 108 and an oppositesecond end 135. At step 406 a firstdielectric layer 134 is affixed to theside 126 of thedie 108, thefirst dielectric layer 134 having afirst side 140 and asecond side 142, wherein thefirst side 140 of thefirst dielectric layer 134 is affixed to theside 126 of thedie 108, and wherein theconductive stud 132 enters thefirst side 140 of thefirst dielectric layer 134. At step 408 aconductive layer 136 is affixed to thesecond side 142 of thefirst dielectric layer 134. The method concludes atstep 410 with adhering thesecond side 135 of theconductive stud 132 to theconductive layer 136 using aconductive adhesive 141. - While illustrative and presently preferred embodiments of the invention have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed and that the appended claims are intended to be construed to include such variations except insofar as limited by the prior art.
Claims (20)
1. A circuit comprising:
a die having a side;
a conductive stud having a first end and an opposite second end, wherein the first end is connected to the side of the die and wherein the conductive stud extends from the side;
a first dielectric layer having a first side and a second side, wherein the first side of the first dielectric layer is located proximate the side of the die so that the conductive stud extends into the first dielectric layer from the first side;
a conductive layer having a first side and a second side, wherein the first side is located adjacent the second side of the first dielectric layer and proximate the second end of the conductive stud; and
a conductive adhesive adhered to the second side of the conductive stud and the first side of the conductive layer.
2. The circuit of claim 1 , wherein said first dielectric layer is adhered to the side of said die.
3. The circuit of claim 1 , and further comprising a connection mechanism electrically connected to at least a portion of the second side of the conductive layer.
4. The circuit of claim 1 , wherein at least a portion of the die is encapsulated with an encapsulant.
5. The circuit of claim 4 , wherein at least a portion of the first dielectric layer contacts the encapsulant.
6. The circuit of claim 1 and further comprising a second dielectric layer having a first side and a second side, wherein the first side is located adjacent the second side of the conductive layer, wherein the second dielectric layer has a via extending between the first side and the second side, and wherein the via is electrically connected to the second side of the conductive layer.
7. The circuit of claim 6 , and further comprising a connection mechanism electrically connected to the via.
8. The circuit of claim 1 , wherein the conductive adhesive is solder.
9. The circuit of claim 1 , wherein the conductive stud comprises copper.
10. The circuit of claim 1 , wherein the side of the die comprises a pad and wherein the conductive stud is connected to the pad.
11. A method of fabricating a circuit, the method comprising:
providing a die, the die having a side;
connecting a conductive stud to the side of the die, wherein the conductive stud has a first end that is connected to the die and an opposite second end;
affixing a first dielectric layer to the side of the die, the first dielectric layer having a first side and a second side, wherein the first side of the first dielectric layer is affixed to the side of the die, and wherein the conductive stud enters the first side of the first dielectric layer; and
affixing a conductive layer to the second side of the first dielectric layer; and
adhering the second side of the conductive stud to the conductive layer using a conductive adhesive.
12. The method of claim 11 and further comprising encapsulating said die prior to said affixing said first dielectric layer to said side of said die wherein said encapsulating comprises substantially encapsulating said die, except for said side.
13. The method of claim 11 , wherein said first dielectric layer is affixed to said die in an uncured state and further comprising:
applying an uncured encapsulant to said die; and
curing said encapsulant and said first dielectric layer simultaneously.
14. The method of claim 13 , wherein the conductive adhesive is cured simultaneously with the encapsulant and the first dielectric layer.
15. The method of claim 14 , wherein the conductive adhesive is solder.
16. The method of claim 11 and further comprising:
affixing a second dielectric layer to the conductive layer, the second dielectric layer having a first side and a second side, wherein the first side of the second dielectric layer is located adjacent the conductive layer; and
forming a second via between the conductive layer and the second side of the second dielectric layer.
17. The method of claim 1 and further comprising affixing a connection mechanism to the second side of the second dielectric layer, the connection mechanism being electrically connected to the second via.
18. The method of claim 11 , wherein said affixing a first dielectric layer comprises affixing a first dielectric material to the conductive layer and applying the dielectric material with the conductive layer to the side of said die.
19. The method of claim 11 , and further comprising applying a conductive adhesive to the second side of the conductive stud and wherein the adhering comprises adhering the second side of the conductive stud to the conductive layer using the conductive adhesive.
20. A circuit comprising:
a die having a side;
an encapsulant encapsulating at least a portion of the die other than the side;
a conductive stud having a first end and an opposite second end, wherein the first end is connected to the side of the die and wherein the conductive stud extends from the side;
a first dielectric layer having a first side and a second side, wherein the first side of the first dielectric layer is located proximate the side of the die so that the conductive stud extends into the first dielectric layer from the first side and wherein the first dielectric layer is adhered to at least a portion of the encapsulant; and
a conductive layer having a first side and a second side, wherein the first side is located adjacent the second side of the first dielectric layer and proximate the second end of the conductive stud;
a conductive adhesive adhered to the second side of the conductive stud and the first side of the conductive layer;
a second dielectric layer adhered to the second side of the conductive layer;
a via extending through the second dielectric layer; and
a connection mechanism attached to the second dielectric layer and electrically connected to the via.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/563,345 US20130075894A1 (en) | 2011-09-23 | 2012-07-31 | Integrated circuit and method of making |
US14/582,349 US9875930B2 (en) | 2011-09-23 | 2014-12-24 | Method of packaging a circuit |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201161538365P | 2011-09-23 | 2011-09-23 | |
US201261596617P | 2012-02-08 | 2012-02-08 | |
US13/443,401 US20130075928A1 (en) | 2011-09-23 | 2012-04-10 | Integrated circuit and method of making |
US13/481,275 US9142472B2 (en) | 2011-09-23 | 2012-05-25 | Integrated circuit and method of making |
US13/563,345 US20130075894A1 (en) | 2011-09-23 | 2012-07-31 | Integrated circuit and method of making |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US13/443,401 Continuation-In-Part US20130075928A1 (en) | 2011-09-23 | 2012-04-10 | Integrated circuit and method of making |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US14/582,349 Division US9875930B2 (en) | 2011-09-23 | 2014-12-24 | Method of packaging a circuit |
Publications (1)
Publication Number | Publication Date |
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US20130075894A1 true US20130075894A1 (en) | 2013-03-28 |
Family
ID=47910371
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/563,345 Abandoned US20130075894A1 (en) | 2011-09-23 | 2012-07-31 | Integrated circuit and method of making |
US14/582,349 Active 2032-06-05 US9875930B2 (en) | 2011-09-23 | 2014-12-24 | Method of packaging a circuit |
Family Applications After (1)
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US14/582,349 Active 2032-06-05 US9875930B2 (en) | 2011-09-23 | 2014-12-24 | Method of packaging a circuit |
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US (2) | US20130075894A1 (en) |
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US9536781B2 (en) * | 2011-09-23 | 2017-01-03 | Texas Instruments Incorporated | Method of making integrated circuit |
US11430723B2 (en) * | 2013-09-25 | 2022-08-30 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device with a semiconductor die embedded between an extended substrate and a bottom substrate |
Also Published As
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US20150111344A1 (en) | 2015-04-23 |
US9875930B2 (en) | 2018-01-23 |
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