TWI398943B - 半導體封裝結構及其製程 - Google Patents

半導體封裝結構及其製程 Download PDF

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Publication number
TWI398943B
TWI398943B TW099128499A TW99128499A TWI398943B TW I398943 B TWI398943 B TW I398943B TW 099128499 A TW099128499 A TW 099128499A TW 99128499 A TW99128499 A TW 99128499A TW I398943 B TWI398943 B TW I398943B
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Taiwan
Prior art keywords
wafer
semiconductor
primer
conductive bumps
interposer
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TW099128499A
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English (en)
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TW201209986A (en
Inventor
Meng Jen Wang
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Advanced Semiconductor Eng
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Priority to TW099128499A priority Critical patent/TWI398943B/zh
Priority to US12/907,028 priority patent/US8310063B2/en
Publication of TW201209986A publication Critical patent/TW201209986A/zh
Application granted granted Critical
Publication of TWI398943B publication Critical patent/TWI398943B/zh

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Description

半導體封裝結構及其製程
本發明是有關於一種半導體封裝結構及其製程，且特別是有關於一種具有穿矽導孔(through silicon via，TSV)的半導體封裝結構及其製程。
在半導體封裝技術中，穿矽導孔的作用是在晶片與晶片間、晶圓與晶圓間製作垂直導通互連之角色，為目前三維積體電路製程整合技術中，能實現晶片之間互連的關鍵技術。有別於過去之積體電路封裝技術，藉由穿矽導孔技術能使晶片在三維方向堆疊的密度最大化，外形尺寸降低，並提升元件速度、減少信號延遲和功率消耗，因此矽導通孔被視為應用於三維積體電路技術之新一代的垂直式內連線(Interconnect)結構。
詳細而言，在半導體封裝製程當中，可先將半導體晶圓薄化以使半導體晶圓內的穿矽導孔裸露，此時的半導體晶圓可先暫時固定在承載晶圓(carrier wafer)上，並且在未進行切割的情況下，進行晶片對半導體晶圓的結合，接著將半導體晶圓與承載晶圓分離，以對半導體晶圓進行後續製程。當分離半導體晶圓與承載晶圓時，半導體晶圓可能會因結構應力的變化而產生翹曲變形的現象，降低製程良率。
本發明提供一種半導體封裝結構，具有較佳的結構強度。
本發明提供一種半導體封裝製程，可避免半導體晶圓在製造過程中翹曲變形。
本發明提出一種半導體封裝結構，包括線路載板、第一晶片、多個第一導電凸塊、第二晶片、多個第二導電凸塊、中介基材及多個第三導電凸塊。線路載板具有承載面以及相對於承載面的底面。第一晶片設置於線路載板的承載面上方，第一晶片具有第一表面以及相對於第一表面的第二表面，第二表面面向線路載板，且第一晶片具有多個穿矽導孔以及位於第一表面上的多個第一接墊與多個第二接墊，第一接墊電性連接至所對應的穿矽導孔。第一導電凸塊配置於第一晶片與線路載板之間，第一晶片的穿矽導孔分別經由第一導電凸塊電性連接至線路載板。第二晶片配置於第一晶片上方，並且暴露出第一表面的局部區域。第二導電凸塊分別配置於第一接墊上，第二晶片經由第二導電凸塊電性連接至所對應的穿矽導孔。中介基材配置於第一晶片上方，並且位於第一表面的局部區域內，中介基材的頂面與第二晶片的頂面實質上相互齊平。第三導電凸塊分別配置於第二接墊上，中介基材經由第三導電凸塊接合至第二接墊。
在本發明之一實施例中，上述之中介基材的側面與第一晶片的側面實質上相互齊平。
在本發明之一實施例中，上述之半導體封裝結構更包括第一底膠，填充於第一晶片與線路載板之間，第一底膠包覆第一導電凸塊。
在本發明之一實施例中，上述之半導體封裝結構更包括第二底膠，填充於第二晶片與第一晶片之間，第二底膠包覆第二導電凸塊。
在本發明之一實施例中，上述之半導體封裝結構更包括第三底膠，填充於中介基材與第一晶片之間，第三底膠包覆第三導電凸塊。
在本發明之一實施例中，上述之半導體封裝結構更包括多個銲球，配置於線路載板的底面。
在本發明之一實施例中，上述之半導體封裝結構更包括散熱片，覆蓋第二晶片與中介基材，且散熱片熱接合至第二晶片與中介基材。
在本發明之一實施例中，上述之半導體封裝結構更包括導熱膠，配置於散熱片與第二晶片之間以及散熱片與中介基材之間。
在本發明之一實施例中，上述之半導體封裝結構更包括導熱環，配置於線路載板上，並且圍繞第一晶片，導熱環熱接合於散熱片與線路載板之間。
在本發明之一實施例中，上述之散熱片接地。
本發明提出一種半導體封裝製程。首先，提供半導體晶圓，半導體晶圓具有第二表面，且半導體晶圓內具有多個穿矽導孔。接著，在第二表面上形成多個第一導電凸塊，第一導電凸塊分別電性連接至穿矽導孔。由第二表面的對側來薄化半導體晶圓，以暴露出每一穿矽導孔的一端以及半導體晶圓的第一表面，每一穿矽導孔的另一端連接第一表面。在第一表面上形成多個第一接墊以及多個第二接墊，其中第一接墊電性連接至所對應的穿矽導孔。接合多個第二晶片至半導體晶圓的第一表面，其中每一第二晶片經由多個第二導電凸塊電性連接至所對應的第一接墊。形成第二底膠於每一第二晶片與半導體晶圓之間，第二底膠在每一第二晶片接合至半導體晶圓之前被預先形成於半導體晶圓上，或是在每一第二晶片接合至半導體晶圓之後被填入每一第二晶片與半導體晶圓之間，第二底膠包覆第二導電凸塊。接合中介晶圓至半導體晶圓的第一表面，其中中介晶圓具有多個開孔分別對應並暴露第二晶片，中介晶圓經由多個第三導電凸塊電性連接至所對應的第二接墊，且中介晶圓的頂面與第二晶片的頂面實質上相互齊平。同時裁切中介晶圓與半導體晶圓，以形成多個封裝單元，其中半導體晶圓被裁切為多個相互分離的第一晶片，且中介晶圓被裁切為多個相互分離的中介基材。接合封裝單元至線路載板，其中第一晶片的穿矽導孔經由所對應的第一導電凸塊電性連接至線路載板。
在本發明之一實施例中，上述之半導體封裝製程更包括形成第一底膠於第一晶片與線路載板之間，第一底膠在第一晶片接合至線路載板之後被填入第一晶片與線路載板之間，第一底膠包覆第一導電凸塊。
在本發明之一實施例中，上述之半導體封裝製程更包括形成第三底膠於中介晶圓與半導體晶圓之間，第三底膠在中介晶圓接合至半導體晶圓之前被預先形成於半導體晶圓上，或是在中介晶圓接合至半導體晶圓之後被填入中介晶圓與半導體晶圓之間，第三底膠包覆第三導電凸塊。
在本發明之一實施例中，上述之半導體封裝製程更包括配置散熱片於封裝單元上，散熱片覆蓋並且熱接合至第二晶片與中介基材。
基於上述，在本發明的半導體封裝製程中，於半導體晶圓被第二晶片暴露的部分配置中介晶圓，以提升整體結構強度，而可避免半導體晶圓在製造過程中因應力變化而產生翹曲變形的現象。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1K為本發明一實施例之半導體封裝製程的流程圖。請參考圖1A，首先，提供半導體晶圓50，其中半導體晶圓50具有第二表面52，且半導體晶圓50內具有多個穿矽導孔126。在第二表面52上形成多個第一導電凸塊130，第一導電凸塊130分別電性連接至穿矽導孔126。
接著，如圖1B所示，將圖1A的半導體晶圓50及第一導電凸塊130固定於一承載件(例如一承載晶圓60)上。請參考圖1C，由第二表面52的對側來薄化半導體晶圓50，以暴露出每一穿矽導孔126的一端以及半導體晶圓50的第一表面54。在第一表面54上形成多個第一接墊122a以及多個第二接墊122b，其中第一接墊122a電性連接至所對應的穿矽導孔126。
請參考圖1D，接合多個第二晶片140至半導體晶圓50的第一表面54，其中每一第二晶片140經由多個第二導電凸塊150連接至所對應的第一接墊122a。請參考圖1E，形成第二底膠180b於每一第二晶片140與半導體晶圓50之間以包覆第二導電凸塊150。在本實施例中，第二底膠180b在每一第二晶片140接合至半導體晶圓50之後被填入每一第二晶片140與半導體晶圓50之間。然本發明不以此為限，亦可在每一第二晶片140接合至半導體晶圓50之前，預先形成第二底膠180b於半導體晶圓50上。
圖2為應用於圖1A至圖1K之半導體封裝製程的中介晶圓的示意圖。請參考圖1F及圖2，接合中介晶圓70至半導體晶圓50的第一表面54，其中中介晶圓70具有多個開孔72分別對應並暴露第二晶片140。中介晶圓70經由多個第三導電凸塊170電性連接至所對應的第二接墊122b，且中介晶圓70的頂面與第二晶片140的頂面實質上相互齊平。需注意的是，在其它實施例中，亦可先接合中介晶圓70至半導體晶圓50，再接合第二晶片140至半導體晶圓50，本發明不對其順序加以限制。
請參考圖1G，形成第三底膠180c於中介晶圓70與半導體晶圓50之間以包覆第三導電凸塊170。在本實施例中，第三底膠180c在中介晶圓70接合至半導體晶圓50之後被填入中介晶圓70與半導體晶圓50之間。然本發明不以此為限，第三底膠180c亦可在中介晶圓70接合至半導體晶圓50之前被預先形成於半導體晶圓50上。此外，第三底膠180c非本發明必要元件，亦即可以省略第三底膠180c形成步驟。
請參考圖1H，移除承載晶圓60，並同時裁切中介晶圓70與半導體晶圓50，以形成多個封裝單元80，其中半導體晶圓50被裁切為多個相互分離的第一晶片120，且中介晶圓70被裁切為多個相互分離的中介基材160，其中中介基材160的側面與第一晶片120的側面實質上相互齊平。半導體晶圓50例如是以膠合的方式固定於承載晶圓60，當移除承載晶圓60時，半導體晶圓50可能會因結構應力的變化而翹曲變形。配置於半導體晶圓50上的中介晶圓70具有提升整體結構強度的效果，因此可避免半導體晶圓50與承載晶圓60分離時產生所述翹曲變形的現象，或降低其翹曲變形的程度。
請參考圖1I，接合封裝單元80至線路載板110，其中第一晶片120的穿矽導孔126經由所對應的第一導電凸塊130電性連接至線路載板110。請參考圖1J，形成第一底膠180a於第一晶片120與線路載板110之間以包覆第一導電凸塊130。第一底膠180a在第一晶片120接合至線路載板110之後被填入第一晶片120與線路載板110之間。請參考圖1K，配置多個銲球190於線路載板110的底面114，而完成半導體封裝結構100的製作。
半導體封裝結構100包括線路載板110、第一晶片120、多個第一導電凸塊130、第二晶片140、多個第二導電凸塊150、中介基材160、多個第三導電凸塊170、第一底膠180a、第二底膠180b、第三底膠180c及多個銲球190。線路載板110具有承載面112以及相對於承載面112的底面114。第一晶片120設置於線路載板110的承載面112上方，第一晶片120具有第一表面122以及相對於第一表面122的第二表面124，第二表面124面向線路載板110，且第一晶片120具有多個穿矽導孔126以及位於第一表面122上的多個第一接墊122a與多個第二接墊122b。
第一接墊122a電性連接至所對應的穿矽導孔126，第二接墊122b亦連接穿矽導孔126，以達到較佳的散熱效果。第一導電凸塊130配置於第一晶片120與線路載板110之間，第一晶片120的穿矽導孔126分別經由第一導電凸塊130電性連接至線路載板110。第二晶片140配置於第一晶片120上方，並且暴露出第一表面122的局部區域。第二導電凸塊150分別配置於第一接墊122a上，第二晶片140經由第二導電凸塊150電性連接至所對應的穿矽導孔126。中介基材160配置於第一晶片120上方，並且位於第一表面122被第二晶片140暴露的局部區域內。
中介基材160的頂面與第二晶片140的頂面實質上相互齊平。第三導電凸塊170分別配置於第二接墊122b上，中介基材160經由第三導電凸塊170接合至第二接墊122b。銲球190配置於線路載板110的底面114，使半導體封裝結構100適於透過銲球190電性連接其它元件。第一底膠180a配置於第一晶片120與線路載板110之間以包覆第一導電凸塊130。第二底膠180b配置於第二晶片140與第一晶片120之間以包覆第二導電凸塊150。第三底膠180c配置於中介基材160與第一晶片120之間以包覆第三導電凸塊170。此外，在其它實施例中，第三底膠180c亦可同時包覆第一晶片120、第二晶片140、中介基材160及第三導電凸塊170。
圖3為圖1K之半導體封裝結構配置散熱片的示意圖。請參考圖3，在完成圖1K所示之半導體封裝結構100之後，可配置圍繞第一晶片120的導熱環90b於線路載板110上。接著，配置散熱片90a於封裝單元80上，散熱片80覆蓋並且熱接合至第二晶片140與中介基材160，導熱環90b熱接合於散熱片90a與線路載板110之間。所述熱接合係指可使兩元件之間達成良好之熱傳導的接合方式，其間可能存在其它的導熱黏著層，如導熱膠90d及導熱膠90e。由於本實施例的中介基材160的頂面與第二晶片140的頂面實質上相互齊平，因此第二晶片140與中介基材160適於共同支撐散熱片90a，讓整體結構更為穩固。
此外，可於散熱片90a與第二晶片140之間以及散熱片110與中介基材160之間形成導熱膠90c以固定散熱片90a。半導體封裝結構100產生的熱可透過導熱環90b及導熱膠90c傳遞至散熱片90a以進行散熱。在本實施例中，散熱片90a除了具有散熱功能之外，半導體封裝結構100更可藉由散熱片90a進行接地。在其它實施例中，散熱片90a亦可為其它型態，如散熱片90a與導熱環90b一體成型，或僅配置散熱片90a而不配置導熱環90b。
綜上所述，在本發明的半導體封裝製程中，於半導體晶圓被第二晶片暴露的部分配置中介晶圓，以提升整體結構強度，而可避免半導體晶圓在製造過程中因應力變化而產生翹曲變形的現象。此外，半導體封裝結構具有由裁切中介晶圓而形成的中介基材，中介基材圍繞第二晶片且可與第二晶片共同支撐散熱片，而使半導體封裝結構具有較佳的結構強度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
50．．．半導體晶圓
52、124．．．第二表面
54、122．．．第一表面
60．．．承載晶圓
70．．．中介晶圓
72．．．開孔
80．．．封裝單元
90a．．．散熱片
90b．．．導熱環
90c、90d、90e．．．導熱膠
100．．．半導體封裝結構
110．．．線路載板
112．．．承載面
114．．．底面
120．．．第一晶片
122a．．．第一接墊
122b．．．第二接墊
126．．．穿矽導孔
130．．．第一導電凸塊
140．．．第二晶片
150．．．第二導電凸塊
160．．．中介基材
170．．．第三導電凸塊
180a．．．第一底膠
180b．．．第二底膠
180c．．．第三底膠
190．．．銲球
圖1A至圖1K為本發明一實施例之半導體封裝製程的流程圖。
圖2為應用於圖1A至圖1K之半導體封裝製程的中介晶圓的示意圖。
圖3為圖1K之半導體封裝結構配置散熱片的示意圖。
72．．．開孔
90a．．．散熱片
90b．．．導熱環
90c、90d、90e．．．導熱膠
100．．．半導體封裝結構
110．．．線路載板
112．．．承載面
114．．．底面
120．．．第一晶片
122．．．第一表面
122a．．．第一接墊
122b．．．第二接墊
124．．．第二表面
126．．．穿矽導孔
130．．．第一導電凸塊
140．．．第二晶片
150．．．第二導電凸塊
160．．．中介基材
170．．．第三導電凸塊
180a．．．第一底膠
180b．．．第二底膠
180c．．．第三底膠
190．．．銲球

Claims (12)

  1. 一種半導體封裝結構，包括：一線路載板，具有一承載面以及相對於該承載面的一底面；一第一晶片，設置於該線路載板的承載面上方，該第一晶片具有一第一表面以及相對於該第一表面的一第二表面，該第二表面面向該線路載板，且該第一晶片具有多個穿矽導孔以及位於該第一表面上的多個第一接墊與多個第二接墊，該些第一接墊電性連接至所對應的該些穿矽導孔；多個第一導電凸塊，配置於該第一晶片與該線路載板之間，該第一晶片的該些穿矽導孔分別經由該些第一導電凸塊電性連接至該線路載板；一第二晶片，配置於該第一晶片上方，並且暴露出該第一表面的局部區域；多個第二導電凸塊，分別配置於該些第一接墊上，該第二晶片經由該些第二導電凸塊電性連接至所對應的該些穿矽導孔；一中介基材，配置於該第一晶片上方，並且位於該第一表面的局部區域內，該中介基材的頂面與該第二晶片的頂面實質上相互齊平；以及多個第三導電凸塊，分別配置於該些第二接墊上，該中介基材經由該些第三導電凸塊接合至該些第二接墊。
  2. 如申請專利範圍第1項所述之半導體封裝結構，其中該中介基材的側面與該第一晶片的側面實質上相互齊平。
  3. 如申請專利範圍第1項所述之半導體封裝結構，更包括：一第一底膠，填充於該第一晶片與該線路載板之間，該第一底膠包覆該些第一導電凸塊。
  4. 如申請專利範圍第1項所述之半導體封裝結構，更包括：一第二底膠，填充於該第二晶片與該第一晶片之間，該第二底膠包覆該些第二導電凸塊。
  5. 如申請專利範圍第1項所述之半導體封裝結構，更包括：一第三底膠，填充於該中介基材與該第一晶片之間，該第三底膠包覆該些第三導電凸塊。
  6. 如申請專利範圍第1項所述之半導體封裝結構，更包括：多個銲球，配置於該線路載板的該底面。
  7. 如申請專利範圍第1項所述之半導體封裝結構，更包括：一散熱片，覆蓋該第二晶片與該中介基材，且該散熱片熱接合至該第二晶片與該中介基材。
  8. 如申請專利範圍第7項所述之半導體封裝結構，更包括：一導熱環，配置於該線路載板上，並且圍繞該第一晶片，該導熱環熱接合於該散熱片與該線路載板之間。
  9. 一種半導體封裝製程，包括：提供一半導體晶圓，該半導體晶圓具有一第二表面，且該半導體晶圓內具有多個穿矽導孔；在該第二表面上形成多個第一導電凸塊，該些第一導電凸塊分別電性連接至該些穿矽導孔；由該第二表面的對側來薄化該半導體晶圓，以暴露出每一穿矽導孔的一端以及該半導體晶圓的一第一表面；在該第一表面上形成多個第一接墊以及多個第二接墊，其中該些第一接墊電性連接至所對應的該些穿矽導孔；接合多個第二晶片至該半導體晶圓的該第一表面，其中每一第二晶片經由多個第二導電凸塊連接至所對應的該些第一接墊；形成一第二底膠於每一第二晶片與該半導體晶圓之間，該第二底膠在每一第二晶片接合至該半導體晶圓之前被預先形成於該半導體晶圓上，或是在每一第二晶片接合至該半導體晶圓之後被填入每一第二晶片與該半導體晶圓之間，該第二底膠包覆該些第二導電凸塊；接合一中介晶圓至該半導體晶圓的該第一表面，其中該中介晶圓具有多個開孔分別對應並暴露該些第二晶片，該中介晶圓經由多個第三導電凸塊電性連接至所對應的該些第二接墊，且該中介晶圓的頂面與該第二晶片的頂面實質上相互齊平；同時裁切該中介晶圓與該半導體晶圓，以形成多個封裝單元，其中該半導體晶圓被裁切為多個相互分離的第一晶片，且該中介晶圓被裁切為多個相互分離的中介基材；以及接合該封裝單元至一線路載板，其中該第一晶片的該些穿矽導孔經由所對應的該些第一導電凸塊電性連接至該線路載板。
  10. 如申請專利範圍第9項所述之半導體封裝製程，更包括：形成一第一底膠於該第一晶片與該線路載板之間，該第一底膠在該第一晶片接合至該線路載板之後被填入該第一晶片與該線路載板之間，該第一底膠包覆該些第一導電凸塊。
  11. 如申請專利範圍第9項所述之半導體封裝製程，更包括：形成一第三底膠於該中介晶圓與該半導體晶圓之間，該第三底膠在該中介晶圓接合至該半導體晶圓之前被預先形成於該半導體晶圓上，或是在該中介晶圓接合至該半導體晶圓之後被填入該中介晶圓與該半導體晶圓之間，該第三底膠包覆該些第三導電凸塊。
  12. 如申請專利範圍第9項所述之半導體封裝製程，更包括：配置一散熱片於該封裝單元上，該散熱片覆蓋並且熱接合至該第二晶片與該中介基材。
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