TWI790054B - 天線整合式封裝結構 - Google Patents
天線整合式封裝結構 Download PDFInfo
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- TWI790054B TWI790054B TW110147388A TW110147388A TWI790054B TW I790054 B TWI790054 B TW I790054B TW 110147388 A TW110147388 A TW 110147388A TW 110147388 A TW110147388 A TW 110147388A TW I790054 B TWI790054 B TW I790054B
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- chip
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- antenna
- rewiring
- conductive
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Abstract
一種天線整合式封裝結構,包括第一重佈線結構、第一晶片、散熱結構、第二晶片以及天線結構。第一晶片位於第一重佈線結構的第一側,且電性連接第一重佈線結構。散熱結構導熱連接至第一晶片,且第一晶片位於散熱結構與第一重佈線結構之間。第二晶片位於第一重佈線結構的相對於第一側的第二側,且電性連接所述第一重佈線結構。天線結構電性連接第一重佈線結構。
Description
本發明是有關於一種天線整合式封裝結構。
隨著5G通訊時代的到來,毫米波(millimeter wave)、波束成形(beam forming)與陣列天線(antenna array)的相關技術已成為了未來發展的趨勢。小型基地台(small cell)可應用於5G通訊,並可提升資料容量、資料傳輸速度及整體網路效率,故可有效地提升通訊品質。為了改善小型基地台的效能,如何提升天線的效能則成為了一個重要的議題。
相位陣列天線包含多個天線單元,而這些天線單元則由晶片進行驅動;然而,現有的晶片由於封裝結構的限制,使晶片產生的熱能難以散出,故也影響了天線單元的效能。因此,如何提出一種封裝結構,能夠有效改善晶片的散熱問題已成為一個刻不容緩的問題。
本發明提供一種天線整合式封裝結構,具有高散熱效率的優點。
本發明的至少一實施例提供一種天線整合式封裝結構,包括第一重佈線結構、第一晶片、散熱結構、第二晶片以及天線結構。第一晶片位於第一重佈線結構的第一側,且電性連接第一重佈線結構。散熱結構導熱連接至第一晶片,且第一晶片位於散熱結構與第一重佈線結構之間。第二晶片位於第一重佈線結構的相對於第一側的第二側,且電性連接所述第一重佈線結構。天線結構電性連接第一重佈線結構。
本發明的至少一實施例提供一種天線整合式封裝結構,包括第一晶片、第二晶片、第一重佈線結構、第一封裝層、散熱結構以及天線結構。第一重佈線結構位於第一晶片與第二晶片之間。第一封裝層環繞第一晶片。散熱結構位於第一晶片與第一封裝層下方,且導熱連接至第一晶片。天線結構電性連接第一重佈線結構。
基於上述,第一晶片與第二晶片分別位於第一重佈線結構的兩側,且散熱結構導熱連接至第一晶片,因此,天線整合式封裝結構具有高散熱效率的優點。
圖1是依照本發明的一實施例的一種天線整合式封裝結構的剖面示意圖。
請參考圖1,天線整合式封裝結構10包括第一重佈線結構RDL1、第一晶片C1、散熱結構HD、第二晶片C2以及天線結構700。在本實施例中,天線整合式封裝結構10還包括第一封裝層500、第二封裝層600以及導電柱800。
第一重佈線結構RDL1具有第一側S1以及相對於第一側S1的第二側S2。第一重佈線結構RDL1包括至少一第一導電層以及重疊於第一導電層的至少一第一絕緣層。在本實施例中,第一重佈線結構RDL1包括多個第一導電層120, 140以及多個第一絕緣層110。相鄰的第一導電層120, 140藉由第一導電孔130而彼此電性連接至。在本實施例中,第一重佈線結構RDL1的第一側S1具有多個第一導電孔130,且第一重佈線結構RDL1的第二側S2具有第一導電層140。第一導電層140為第一重佈線結構RDL1的最頂層導電層。
在一些實施例中,第一絕緣層110的厚度在0.5微米至20微米的範圍之間。在一些實施例中,第一導電層120的厚度在0.5微米至20微米的範圍之間。在一些實施例中,最頂層之第一導電層140的厚度大於或等於其他第一導電層120之厚度,但本發明不以此為限。
第一晶片C1位於第一重佈線結構RDL1的第一側S1,且電性連接第一重佈線結構RDL。在一些實施例中,多個第一晶片C1位於第一重佈線結構RDL1的第一側S1,且各自電性連接第一重佈線結構RDL1。在本實施例中,第一晶片C1包括第一半導體結構300、多個第一連接端子320以及至少一第一連接結構330。第一連接端子320位於第一半導體結構300的主動面,且電性連接第一半導體結構300至第一重佈線結構RDL1。在一些實施例中,第一連接端子320與第一半導體結構300之間更包括重佈線結構(未繪出)。
在一些實施例中,第一連接端子320為單層或多層結構。在一些實施例中,第一連接端子320包括凸塊或其他合適的導電連接結構。第一連接端子320的形狀可以依照實際需求而調整。在一些實施例中,第一連接端子320的材料包括金、錫、銅、前述材料的合金或其他合適的導電材料。第一連接結構330設置於第一半導體結構300相對於第一連接端子320的一側。第一連接結構330例如為熱介面材料、銲料層或其他合適的材料,其中銲料層例如為金錫銲料或其他合適的銲料。
在一些實施例中,第一半導體結構300的厚度在25微米至800微米的範圍之間。在一些實施例中,第一連接端子320的厚度在10微米至30微米的範圍之間。在一些實施例中,形成第一連接端子320的方法包括打線成球,且第一連接端子320上部較窄之部分的線徑在10微米至30微米的範圍之間。在一些實施例中,第一連接結構330的厚度在10微米至100微米的範圍之間。
導電柱800位於第一重佈線結構RDL1的第一側S1,且電性連接第一重佈線結構RDL。在本實施例中,導電柱800位於第一封裝層500中,且導電柱800為穿模通孔(Through Molding Via,TMV)。在一些實施例中,導電柱800的材料包括金、錫、銅、前述材料的合金或其他合適的導電材料。在一些實施例中,導電柱800的直徑在50微米至2000微米的範圍之間。
第二晶片C2位於第一重佈線結構RDL1的第二側S2,且電性連接第一重佈線結構RDL1。在一些實施例中,多個第二晶片C2位於第一重佈線結構RDL1的第二側S2,且各自電性連接第一重佈線結構RDL1。在本實施例中,第二晶片C2包括第二半導體結構400、重佈線結構410以及多個第二連接端子420。第二連接端子420位於第二半導體結構400的主動面,且重佈線結構410設置於第二連接端子420與第二半導體結構400之間。在一些實施例中,第二半導體結構400的表面設置有緩衝層402,且重佈線結構410設置於緩衝層402上。重佈線結構410例如包括互相堆疊的至少一絕緣層412與至少一導電層414。第二連接端子420電性連接第二半導體結構400至第一重佈線結構RDL1。第一連接端子320與第二連接端子420分別連接第一重佈線結構RDL1的第一側S1與第二側S2。
在一些實施例中,第二連接端子420為單層或多層結構。在一些實施例中,第二連接端子420包括柱形凸塊422以及銲料424。第二連接端子420的形狀可以依照實際需求而調整。在一些實施例中,柱形凸塊422的材料包括金、錫、銅、前述材料的合金或其他合適的導電材料。
在本實施例中,第一重佈線結構RDL1位於第一晶片C1與第二晶片C2之間,第一晶片C1與第二晶片C2分別位於第一重佈線結構RDL1的第一側S1與第二側S2,因此,可以更有效的利用天線整合式封裝結構10的線路布局空間,使天線整合式封裝結構10可以整合更多數量的晶片。在本實施例中,第一晶片C1與第二晶片C2的主動面皆朝向第一重佈線結構RDL1,但本發明不以此為限。在其他實施例中,第一晶片C1的主動面朝向第一重佈線結構RDL1,第二晶片C2的主動面背對第一重佈線結構RDL1。
第一封裝層500與第二封裝層600分別位於第一重佈線結構RDL1的第一側S1與第二側S2。第一封裝層500與第二封裝層600可以為任何合適的封裝材料,舉例來說,第一封裝層500與第二封裝層600為環氧成型模料(Epoxy Molding Compound,EMC)、樹脂或其他合適的材料。在一些實施例中,第一封裝層500與第二封裝層600內還可以設置有填充材料,但本發明不以此為限。
第一封裝層500環繞第一晶片C1與導電柱800。在本實施例中,第一封裝層500除了覆蓋第一晶片C1的側面之外,還位於第一晶片C1與第一重佈線結構RDL1之間,並包覆第一晶片C1的第一連接端子320。
第二封裝層600環繞第二晶片C2。在本實施例中,第二封裝層600除了覆蓋第二晶片C2的側面之外,還位於第二晶片C2與第一重佈線結構RDL1之間,並包覆第二晶片C2的第二連接端子420。
在一些實施例中,第一封裝層500的厚度在100微米至150微米的範圍之間。在一些實施例中,第二封裝層600的厚度在200微米至800微米的範圍之間。
散熱結構HD位於第一晶片C1下方,且導熱連接至第一晶片C1。第一晶片C1位於散熱結構HD與第一重佈線結構RDL1之間。在一些實施例中,在天線整合式封裝結構10運作時,第一晶片C1所發出的熱量比第二晶片C2所發出的熱量多,因此,散熱結構HD導熱連接至第一晶片C1可以有效提升天線整合式封裝結構10的散熱效率。在一些實施例中,第一晶片C1例如為功率放大器(Power Amplifier),且第二晶片C2例如為開關(Switch)。
在本實施例中,散熱結構HD包括第二重佈線結構RDL2與散熱基底900。第一晶片C1位於第二重佈線結構RDL2與第一重佈線結構RDL1之間。散熱基底900導熱連接至第二重佈線結構RDL2,且第一晶片C1透過第二重佈線結構RDL2而導熱連接至散熱基底900。
在一些實施例中,散熱基底900包括半導體(例如矽)或金屬。在一些實施例中,散熱基底900與第二重佈線結構RDL2之間還夾有緩衝層902。緩衝層902例如為氧化矽、氮化矽或其他合適的材料。在一些實施例中,散熱基底900的外側表面可以設置散熱結構,例如散熱鰭片、水冷裝置或其他合適的散熱結構。
第二重佈線結構RDL2包括至少一第二導電層以及重疊於第二導電層的至少一第二絕緣層。在本實施例中,第二重佈線結構RDL2包括多個第二導電層220, 240以及多個第一絕緣層210。在一些實施例中,第二導電層240為第二重佈線結構RDL2的最頂層導電層。在一些實施例中,第二導電層240為球下金屬層(Under Bump Metallurgy,UBM)。在一些實施例中,第一晶片C1與導電柱800分別透過第一連接結構330以及連接結構810而電性連接第二重佈線結構RDL2,且導電柱800電性連接第二重佈線結構RDL2至第一重佈線結構RDL1。
在一些實施例中,第二絕緣層210的厚度在0.5微米至20微米的範圍之間。在一些實施例中,第二導電層220的厚度在0.5微米至20微米的範圍之間。在一些實施例中,最頂層之第二導電層240的厚度大於或等於其他第一導電層220之厚度,但本發明不以此為限。在一些實施例中,最頂層之第二導電層240的厚度在0.5微米至20微米的範圍之間。
天線結構700電性連接至第一重佈線結構RDL1。在本實施例中,天線結構700位於第一重佈線結構RDL1的第二側S2,且連接至第一重佈線結構RDL1的第一導電層140。在本實施例中,天線結構700形成於第二封裝層600上,且透過第二封裝層600中的導電通孔602而電性連接至第一重佈線結構RDL1。在一些實施例中,天線結構700進一步透過導電柱800而電性連接至第二重佈線結構RDL2。天線結構700的饋線(Feed line)設置於第一重佈線結構RDL1及/或第二重佈線結構RDL2中。在一些實施例中,導電通孔602的直徑為100微米至2000微米的範圍之間,且導電通孔602設置於第一導電層140中的接墊上。
在一些實施例中,天線結構700可以是任何形式的天線。舉例來說,天線結構700為包含多個天線單元的天線陣列、平面型倒F天線(Printed Inverted-F antenna,PIFA)或其他天線結構。每個天線單元各自電性連接至第一重佈線結構RDL1。在一些實施例中,天線結構700適用於端射式(End-fire)或側射式(Broadside)天線,且被配置成在迴路損失(Return loss)小於10dB的頻率介於26GHz至33GHz。
在一些實施例中,天線整合式封裝結構10的熱傳模擬分析結果如下表1所示。
表1
散熱條件 (W-K/mm 2) | Ta ( ℃ ) | H (W) | Tj ( ℃ ) | Tc ( ℃ ) | Rjc ( ℃/W ) | Rja ( ℃/W ) |
5000 | 25 | 10 | 94.39 | 61.22 | 3.314 | 6.93 |
10000 | 25 | 10 | 83.79 | 50.57 | 3.319 | 5.87 |
在表1中,散熱條件為散熱結構HD底下的散熱條件,Ta為環境溫度,H為第一晶片C1所釋放的熱,Tj為第一晶片C1之發熱位置的最高溫度,Tc為散熱結構HD底部的平均溫度,Rjc為(Tj-Tc)/H,Rja為(Tj-Ta)/H。
由表1可以得知,天線整合式封裝結構10具有高散熱效率的優點。
在一些實施例中,第二封裝層600上還可以設置有接墊(未繪出),前述接墊例如與天線結構700形成於同一膜層。前述接墊電性連接至第一重佈線結構RDL1,且適用於連接其他電路板。
圖2是依照本發明的一實施例的一種天線整合式封裝結構的剖面示意圖。在此必須說明的是,圖2的實施例沿用圖1的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,在此不贅述。
請參考圖2,天線整合式封裝結構20包括第一重佈線結構RDL1、第一晶片C1、散熱結構HD、第二晶片C2以及天線結構700。在本實施例中,天線整合式封裝結構20還包括第一封裝層500以及導電柱800。
在本實施例中,第一重佈線結構RDL1位於第一晶片C1與第二晶片C2之間,第一晶片C1與第二晶片C2分別位於第一重佈線結構RDL1的第一側S1與第二側S2,因此,可以更有效的利用天線整合式封裝結構20的線路布局空間,使天線整合式封裝結構20可以整合更多數量的晶片。
散熱結構HD位於第一晶片C1下方,且導熱連接至第一晶片C1。第一晶片C1位於散熱結構HD與第一重佈線結構RDL1之間。在一些實施例中,在天線整合式封裝結構20運作時,第一晶片C1所發出的熱量比第二晶片C2所發出的熱量多,因此,散熱結構HD導熱連接至第一晶片C1可以有效提升天線整合式封裝結構20的散熱效率。
在一些實施例中,第一重佈線結構RDL1的第二側S2未設置封裝層,且天線結構700直接形成於第一重佈線結構RDL1上。天線結構700的頂面較第二晶片C2的頂面更靠近第一重佈線結構RDL1。在一些實施例中,天線結構700與第一重佈線結構RDL1的最頂層第一導電層140屬於同一膜層,藉此節省製造天線結構700所需要的成本。
圖3是依照本發明的一實施例的一種天線整合式封裝結構的剖面示意圖。在此必須說明的是,圖3的實施例沿用圖1的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,在此不贅述。
請參考圖3,天線整合式封裝結構30包括第一重佈線結構RDL1、第一晶片C1、散熱結構HD、第二晶片C2以及天線結構700。在本實施例中,天線整合式封裝結構30還包括第一封裝層500、第二封裝層600以及導電柱800。
在本實施例中,第一重佈線結構RDL1位於第一晶片C1與第二晶片C2之間,第一晶片C1與第二晶片C2分別位於第一重佈線結構RDL1的第一側S1與第二側S2,因此,可以更有效的利用天線整合式封裝結構30的線路布局空間,使天線整合式封裝結構30可以整合更多數量的晶片。在本實施例中,第一晶片C1的主動面朝向第一重佈線結構RDL1,第二晶片C2的主動面背對第一重佈線結構RDL1。
散熱結構HD位於第一晶片C1下方,且導熱連接至第一晶片C1。第一晶片C1位於散熱結構HD與第一重佈線結構RDL1之間。在一些實施例中,在天線整合式封裝結構30運作時,第一晶片C1所發出的熱量比第二晶片C2所發出的熱量多,因此,散熱結構HD導熱連接至第一晶片C1可以有效提升天線整合式封裝結構30的散熱效率。
在本實施例中,第二晶片C2是藉由打線接合的方式電性連接至第一重佈線結構RDL1的第一導電層140,且第二晶片C2的第二連接端子420為金屬導線。
圖4是依照本發明的一實施例的一種天線整合式封裝結構的剖面示意圖。在此必須說明的是,圖4的實施例沿用圖1的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,在此不贅述。
請參考圖4,天線整合式封裝結構40包括第一重佈線結構RDL1、第一晶片C1、散熱結構HD、第二晶片C2以及天線結構700。在本實施例中,天線整合式封裝結構30還包括第一底部填充材510、第二底部填充材610、第一封裝層500、第二封裝層600、導電柱800、接墊710以及電路板1000。
在本實施例中,第一重佈線結構RDL1位於第一晶片C1與第二晶片C2之間,第一晶片C1與第二晶片C2分別位於第一重佈線結構RDL1的第一側S1與第二側S2,因此,可以更有效的利用天線整合式封裝結構40的線路布局空間,使天線整合式封裝結構40可以整合更多數量的晶片。在本實施例中,第一重佈線結構RDL1的最頂層第一導電層140連接至第二晶片C2,且第一重佈線結構RDL1的最底層第一導電層150連接至第一晶片C1。
在本實施例中,第一底部填充材510填入第一晶片C1與第一重佈線結構RDL1之間,且環繞第一晶片C1的第一連接端子320。第一封裝層500環繞第一晶片C1與第一底部填充材510。
第二底部填充材610填入第二晶片C2與第一重佈線結構RDL1之間,且環繞第二晶片C2的第二連接端子420。第二封裝層600環繞第二晶片C2與第二底部填充材610。
散熱結構HD位於第一晶片C1下方,且導熱連接至第一晶片C1。第一晶片C1位於散熱結構HD與第一重佈線結構RDL1之間。在一些實施例中,在天線整合式封裝結構40運作時,第一晶片C1所發出的熱量比第二晶片C2所發出的熱量多,因此,散熱結構HD導熱連接至第一晶片C1可以有效提升天線整合式封裝結構40的散熱效率。
在本實施例中,第一晶片C1更包括散熱材料層340。散熱材料層340位於第一半導體結構300相對於第一連接端子320的一側,且第一晶片C1的散熱材料層340導熱連接至散熱結構HD。在一些實施例中,散熱材料層340包括熱介面材料、金屬或其他導熱材料。
在一些實施例中,散熱結構HD包括第二重佈線結構RDL2與散熱基底900,但本發明不以此為限。在一些實施例中,使用較厚之第二導電層220, 252,則散熱結構HD不需要額外設置散熱基底900就可以有足夠的散熱能力。舉例來說,第二導電層220, 252的厚度大於第一導電層120, 140的厚度。在本實施例中,第二導電層220藉由第二導電孔230而導熱連接至第一晶片C1及導電柱800。第二重佈線結構RDL2的最底層第二導電層252導熱連接至第二導電層220,並透過導熱材料254而連接至可選的散熱基底900。導熱材料254例如為熱介面材料、銲料或其他合適的材料。
在本實施例中,接墊710位於第二封裝層600上。接墊710例如與天線結構700形成於同一膜層。接墊710電性連接至第一重佈線結構RDL1(例如透過圖示中未繪出之透過貫穿第一封裝層500的其他導電通孔),且適用於連接電路板1000。舉例來說,電路板1000透過導電連接結構1010而連接至接墊710。導電連接結構1010例如為銲料、導電膠或其他合適的材料。
圖5A至圖5E是依照本發明的一實施例的一種天線整合式封裝結構的製造方法的剖面示意圖。在此必須說明的是,圖5A至圖5E的實施例沿用圖1的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,在此不贅述。
請參考圖5A,於散熱基底900上形成第二重佈線結構RDL2。在本實施例中,於散熱基底900上先形成緩衝層902,接著再於緩衝層902上形成第二重佈線結構RDL2。
請參考圖5B,將第一晶片C1與導電柱800置於第二重佈線結構RDL2上。第一晶片C1藉由第一連接結構330而連接至第二重佈線結構RDL2,且導電柱800藉由連接結構810而連接至第二重佈線結構RDL2。
請參考圖5C,形成第一封裝層500於第二重佈線結構RDL2上。舉例來說,形成第一封裝層500的方法包括:先形成封裝材料於第二重佈線結構RDL2上以包覆第一晶片C1與導電柱800,接著研磨前述封裝材料,直至第一晶片C1的第一連接端子320與導電柱800被暴露出來。在一些實施例中,在研磨封裝材料時,第一連接端子320與導電柱800亦會在研磨製程中被部分移除。
請參考圖5D,形成第一重佈線結構RDL1於第一封裝層500、第一晶片C1與導電柱800上,且第一重佈線結構RDL1電性連接至第一晶片C1與導電柱800。
請參考圖5E,將第二晶片C2置於第一重佈線結構RDL1上。第二晶片C2藉由第二連接端子420而連接至第一重佈線結構RDL1。形成封裝材料600’於第一重佈線結構RDL1上以包覆第二晶片C2。
接著請參考圖1,於封裝材料600’中形成通孔,以形成第二封裝層600。形成天線結構700於第二封裝層600上,並使天線結構700電性連接至第一重佈線結構RDL1。至此,天線整合式封裝結構10大致完成。
圖6A至圖6F是依照本發明的一實施例的一種天線整合式封裝結構的製造方法的剖面示意圖。在此必須說明的是,圖6A至圖6F的實施例沿用圖4的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,在此不贅述。
請參考圖6A,形成第一重佈線結構RDL1於載板C上。在本實施例中,第一重佈線結構RDL1包括多個第一導電層120, 140, 150以及多個第一絕緣層110。第一導電層120, 140, 150藉由第一導電孔130而彼此電性連接。
請參考圖6B,將第一晶片C1與導電柱800置於第一重佈線結構RDL1的第一側S1上。第一晶片C1藉由第一連接端子320而連接至第一重佈線結構RDL1的第一導電層150,且導電柱800亦連接至第一重佈線結構RDL1的第一導電層150。在一些實施例中,導電柱800與第一導電層150之間更包括連接結構(例如銲料或導電膠)。
形成第一底部填充材510於第一重佈線結構RDL1的第一側S1上,以包覆第一晶片C1的第一連接端子320。
形成封裝材料500’於第一重佈線結構RDL1的第一側S1上以包覆第一底部填充材510、第一晶片C1與導電柱800。
請參考圖6C,研磨封裝材料500’,直至第一晶片C1的散熱材料層340與導電柱800被暴露出來,以形成第一封裝層500。在一些實施例中,散熱材料層340與導電柱800亦會在研磨製程中被部分移除。
於第一封裝層500、散熱材料層340與導電柱800上形成第二重佈線結構RDL2。
請參考圖6D,將載板C自第一重佈線結構RDL1下方移除。
請參考圖6E,將第二晶片C2置於第一重佈線結構RDL1的第二側S2上。第二晶片C2藉由第二連接端子420而連接至第一重佈線結構RDL1的第一導電層140。
形成第二底部填充材610於第一重佈線結構RDL1的第二側S2上,以包覆第二晶片C2的第二連接端子420。
請參考圖6F,形成第二封裝層600於第一重佈線結構RDL1的第二側S2上。舉例來說,形成第二封裝層600的方法包括:先形成封裝材料於第一重佈線結構RDL1上以包覆第二底部填充材610與第二晶片C2,接著於前述封裝材料中形成暴露出第一重佈線結構RDL1的通孔。
接著,形成天線結構700與接墊710於第二封裝層600上。天線結構700與接墊710例如同時形成,且天線結構700與接墊710電性連接至第一重佈線結構RDL1。
接著請參考圖4,將電路板1000連接至接墊710。選擇性地將散熱基底900連接至第二重佈線結構RDL2。至此,天線整合式封裝結構40大致完成。
綜上所述,第一晶片與第二晶片分別位於第一重佈線結構的第一側與第二側,因此,可以更有效的利用天線整合式封裝結構的線路布局空間,使天線整合式封裝結構可以整合更多數量的晶片。此外,散熱結構導熱連接至第一晶片可以有效提升天線整合式封裝結構的散熱效率。
10, 20, 30, 40:天線整合式封裝結構
110:第一絕緣層
120, 140, 150:第一導電層
130:第一導電孔
210:第二絕緣層
220, 240, 252:第二導電層
230:第二導電孔
254:導熱材料
300:第一半導體結構
320:第一連接端子
330:第一連接結構
340:散熱材料層
400:第二半導體結構
402:緩衝層
410:重佈線結構
412:絕緣層
414:導電層
420:第二連接端子
422:凸塊
424:銲料
500:第一封裝層
500’, 600’:封裝材料
510:第一底部填充材
600:第二封裝層
602:導電通孔
610:第二底部填充材
700:天線結構
710:接墊
800:導電柱
810:連接結構
900:散熱結構
902:緩衝層
1000:電路板
1010:導電連接結構
C:載板
C1:第一晶片
C2:第二晶片
HD:散熱結構
RDL1:第一重佈線結構
RDL2:第二重佈線結構
S1:第一側
S2:第二側
圖1是依照本發明的一實施例的一種天線整合式封裝結構的剖面示意圖。
圖2是依照本發明的一實施例的一種天線整合式封裝結構的剖面示意圖。
圖3是依照本發明的一實施例的一種天線整合式封裝結構的剖面示意圖。
圖4是依照本發明的一實施例的一種天線整合式封裝結構的剖面示意圖。
圖5A至圖5E是依照本發明的一實施例的一種天線整合式封裝結構的製造方法的剖面示意圖。
圖6A至圖6F是依照本發明的一實施例的一種天線整合式封裝結構的製造方法的剖面示意圖。
10:天線整合式封裝結構
110:第一絕緣層
120,140:第一導電層
130:第一導電孔
210:第二絕緣層
220,240:第二導電層
300:第一半導體結構
320:第一連接端子
330:第一連接結構
400:第二半導體結構
402:緩衝層
410:重佈線結構
412:絕緣層
414:導電層
420:第二連接端子
422:凸塊
424:銲料
500:第一封裝層
600:第二封裝層
602:導電通孔
700:天線結構
800:導電柱
810:連接結構
900:散熱結構
902:緩衝層
C1:第一晶片
C2:第二晶片
HD:散熱結構
RDL1:第一重佈線結構
RDL2:第二重佈線結構
S1:第一側
S2:第二側
Claims (16)
- 一種天線整合式封裝結構,包括:第一重佈線結構;第一晶片,位於所述第一重佈線結構的第一側,且電性連接所述第一重佈線結構;散熱結構,導熱連接至所述第一晶片,且所述第一晶片位於所述散熱結構與所述第一重佈線結構之間,其中所述散熱結構包括第二重佈線結構,且所述第一晶片位於所述第二重佈線結構與所述第一重佈線結構之間;第二晶片,位於所述第一重佈線結構的相對於所述第一側的第二側,且電性連接所述第一重佈線結構;以及天線結構,電性連接所述第一重佈線結構。
- 如請求項1所述的天線整合式封裝結構,更包括:第一封裝層,環繞所述第一晶片;以及第二封裝層,環繞所述第二晶片,其中所述第一封裝層與所述第二封裝層分別位於所述第一重佈線結構的所述第一側與所述第二側。
- 如請求項2所述的天線整合式封裝結構,其中所述天線結構形成於所述第二封裝層上,且透過所述第二封裝層中的導電通孔而電性連接至所述第一重佈線結構。
- 如請求項1所述的天線整合式封裝結構,更包括:第一封裝層,環繞所述第一晶片;以及導電柱,其中所述第一封裝層環繞所述導電柱,且所述導電柱電性連接所述第二重佈線結構至所述第一重佈線結構。
- 請求項1所述的天線整合式封裝結構,其中所述第一重佈線結構包括至少一第一導電層以及重疊於所述第一導電層的至少一第一絕緣層,所述第二重佈線結構包括至少一第二導電層以及重疊於所述第二導電層的至少一第二絕緣層,其中所述第二導電層的厚度大於所述第一導電層的厚度。
- 請求項1所述的天線整合式封裝結構,其中所述散熱結構更包括:散熱基底,導熱連接至所述第二重佈線結構。
- 如請求項1所述的天線整合式封裝結構,其中:所述第一晶片包括:第一半導體結構;以及多個第一連接端子,電性連接所述第一半導體結構至所述第一重佈線結構;且所述第二晶片包括:第二半導體結構;以及多個第二連接端子,電性連接所述第二半導體結構至所述第一重佈線結構,其中所述第一連接端子與所述第二連接端子分別連接所述第一重佈線結構的所述第一側與所述第二側。
- 如請求項1所述的天線整合式封裝結構,其中所述天線結構直接形成於所述第一重佈線結構上,且所述天線結構的頂面較所述第二晶片的頂面更靠近所述第一重佈線結構。
- 一種天線整合式封裝結構,包括:第一晶片與第二晶片;第一重佈線結構,位於所述第一晶片與所述第二晶片之間;第一封裝層,環繞所述第一晶片;散熱結構,位於所述第一晶片與所述第一封裝層下方,且導熱連接至所述第一晶片,其中所述散熱結構包括第二重佈線結構,且所述第一晶片位於所述第二重佈線結構與所述第一重佈線結構之間;以及天線結構,電性連接所述第一重佈線結構。
- 如請求項9所述的天線整合式封裝結構,更包括:第二封裝層,環繞所述第二晶片,其中所述第一封裝層與所述第二封裝層分別位於所述第一重佈線結構的相對兩側。
- 如請求項10所述的天線整合式封裝結構,其中所述天線結構形成於所述第二封裝層上,且透過所述第二封裝層中的導電通孔而電性連接至所述第一重佈線結構。
- 如請求項9所述的天線整合式封裝結構,更包括:導電柱,其中所述第一封裝層環繞所述導電柱,且所述導電柱電性連接所述第二重佈線結構至所述第一重佈線結構。
- 請求項9所述的天線整合式封裝結構,其中所述第一重佈線結構包括至少一第一導電層以及重疊於所述第一導電層的至少一第一絕緣層,所述第二重佈線結構包括至少一第二導電層以及重疊於所述第二導電層的至少一第二絕緣層,其中所述第二導電層的厚度大於所述第一導電層的厚度。
- 請求項9所述的天線整合式封裝結構,其中所述散熱結構更包括:散熱基底,導熱連接至所述第二重佈線結構。
- 如請求項9所述的天線整合式封裝結構,其中:所述第一晶片包括:第一半導體結構;以及多個第一連接端子,電性連接所述第一半導體結構至所述第一重佈線結構;且所述第二晶片包括:第二半導體結構;以及多個第二連接端子,電性連接所述第二半導體結構至所述第一重佈線結構,其中所述第一連接端子與所述第二連接端子分別連接所述第一重佈線結構的所述第一側與所述第二側。
- 如請求項9所述的天線整合式封裝結構,其中所述天線結構直接形成於所述第一重佈線結構上,且所述天線結構的頂面較所述第二晶片的頂面更靠近所述第一重佈線結構。
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