US20130154106A1 - Stacked Packaging Using Reconstituted Wafers - Google Patents

Stacked Packaging Using Reconstituted Wafers Download PDF

Info

Publication number
US20130154106A1
US20130154106A1 US13/325,951 US201113325951A US2013154106A1 US 20130154106 A1 US20130154106 A1 US 20130154106A1 US 201113325951 A US201113325951 A US 201113325951A US 2013154106 A1 US2013154106 A1 US 2013154106A1
Authority
US
United States
Prior art keywords
die
reconstituted wafer
rdl
molding compound
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/325,951
Inventor
Kevin Kunzhong Hu
Sam Ziqun Zhao
Rezaur Rahman Khan
Pieter Vorenkamp
Sampath K.V. Karikalan
Xiangdong Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies General IP Singapore Pte Ltd
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Priority to US13/325,951 priority Critical patent/US20130154106A1/en
Assigned to BROADCOM CORPORATION reassignment BROADCOM CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, XIANGDONG, HU, KEVIN KUNZHONG, KARIKALAN, SAMPATH K.V., KHAN, REZAUR RAHMAN, VORENKAMP, PIETER, ZHAO, SAM ZIQUN
Publication of US20130154106A1 publication Critical patent/US20130154106A1/en
Assigned to BANK OF AMERICA, N.A., AS COLLATERAL AGENT reassignment BANK OF AMERICA, N.A., AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: BROADCOM CORPORATION
Assigned to AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. reassignment AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BROADCOM CORPORATION
Assigned to BROADCOM CORPORATION reassignment BROADCOM CORPORATION TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Assignors: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401Structure
    • H01L2224/24011Deposited, e.g. MCM-D type
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24146Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009Pre-treatment of the connector or the bonding area
    • H01L2224/8203Reshaping, e.g. forming vias
    • H01L2224/82035Reshaping, e.g. forming vias by heating means
    • H01L2224/82039Reshaping, e.g. forming vias by heating means using a laser
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009Pre-treatment of the connector or the bonding area
    • H01L2224/8203Reshaping, e.g. forming vias
    • H01L2224/82047Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821Forming a build-up interconnect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/9202Forming additional connectors after the connecting process
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92132Sequential connecting processes the first connecting process involving a build-up interconnect
    • H01L2224/92133Sequential connecting processes the first connecting process involving a build-up interconnect the second connecting process involving a bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06524Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06527Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06548Conductive via connections through the substrate, container, or encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.

Description

    BACKGROUND
  • Packaging for dies that include, for example, at least one integrated circuit (IC), is continually trending towards reduced package size with increased package density. For example, electronic devices that include these packages, such as cell phones, hands-free headsets, camcorders, cameras, and personal computers, continue to be made smaller. At the same time, these electronic devices increasingly demand higher levels of functionality. However, incorporating higher levels of functionality into these electronic devices tends to increase package size and reduce package density. For example, incorporating higher levels of functionality typically requires additional circuitry and/or dies. The additional circuitry and/or dies can complicate packaging. As one example, among other considerations, the additional circuitry and/or dies may require accommodation of additional input/output (I/O) pads.
  • Complications to packaging may be of particular concern in electronic devices, such as portable devices, where component space and layout options for packages are limited. For example, a cell phone may have a form factor that constrains component space in a particular dimension. One approach to coping with limited component space and layout options would be to stack packaged dies to reduce their combined footprint. For example, each of the packaged dies may be housed in a respective package. Then, using package level processes, the respective packages could be stacked on one another and interconnected.
  • SUMMARY
  • The present disclosure is directed to stacked packaging using reconstituted wafers, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 presents an exemplary flowchart illustrating a method for manufacturing a stacked package, according to an implementation of the present disclosure.
  • FIG. 2A presents an exemplary perspective view of a reconstituted wafer stack, according to an implementation of the present disclosure.
  • FIG. 2B presents an exemplary cross-sectional view of a portion of a reconstituted wafer stack, according to an implementation of the present disclosure.
  • FIG. 2C presents an exemplary cross-sectional view of a portion of a reconstituted wafer stack, according to an implementation of the present disclosure.
  • FIG. 2D presents an exemplary cross-sectional view of a stacked package, according to an implementation of the present disclosure.
  • FIG. 3 presents an exemplary cross-sectional view of a stacked package, according to an implementation of the present disclosure.
  • DETAILED DESCRIPTION
  • The following description contains specific information pertaining to implementations in the present disclosure. One skilled in the art will recognize that the present disclosure may be implemented in a manner different from that specifically discussed herein. The drawings in the present application and their accompanying detailed description are directed to merely exemplary implementations. Unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions.
  • FIG. 1 presents exemplary flowchart 100 illustrating a method for manufacturing a stacked package. The approach and technique indicated by flowchart 100 are sufficient to describe at least one implementation of the present disclosure, however, other implementations of the disclosure may utilize approaches and techniques different from those shown in flowchart 100. Furthermore, while flowchart 100 is described with respect to FIGS. 2A, 2B, 2C, & 2D the disclosed inventive concepts are not intended to be limited by specific features shown in FIGS. 2A, 2B, 2C, & 2D.
  • Referring now to flowchart 100 of FIG. 1 and FIGS. 2A and 2B, flowchart 100 includes stacking a top reconstituted wafer having a top die over a bottom reconstituted wafer having a bottom die to form a reconstituted wafer stack (action 170 in flowchart 100). FIGS. 2A and 2B show portions of reconstituted wafer stack 280 after action 170, in accordance with implementations of the present disclosure.
  • FIG. 2A presents a perspective view of reconstituted wafer stack 280, according to an implementation of the present disclosure. Reconstituted wafer stack 280 includes top reconstituted wafer 202 and bottom reconstituted wafer 204. As shown in FIG. 2A, top reconstituted wafer 202 includes stacked package region 218, which is designated for formation of a stacked package, such as stacked package 284 in FIG. 2D. In FIG. 2A, stacked package region 218 is rectangular and extends completely through reconstituted wafer stack 280. FIG. 2B presents a cross-sectional view of a portion of reconstituted wafer stack 280 along cross-section 220.
  • As shown in FIG. 2A, top reconstituted wafer 202 includes top dies 214, of which top dies 206, 208, 210, and 212 are individually labeled, and top molding compound 216 (or more generally “top passivation 216”). FIG. 2A shows top dies 214 being arranged in a grid-like pattern, with each being flanked by top molding compound 216. As shown in FIG. 2A, top molding compound 216 forms a border around and flanks each of top dies 214.
  • In one implementation, top dies 214 have been singulated from a same wafer, such as a silicon wafer. In other implementations, at least one of top dies 214 has been singulated from a different wafer than at least another of top dies 214. Furthermore, any or all of top dies 214 can be of substantially identical dimensions with respect to one another (e.g., width, length, thickness), or any dimension can be different. Any of top dies 214 can include an integrated circuit (IC) and/or other electrical components, such as, for example, passive components. In one implementation, each of top dies 214 includes an IC.
  • Top reconstituted wafer 202 can be fabricated utilizing various means. In one implementation, top reconstituted wafer 202 is fabricated utilizing embedded wafer level techniques, although in some implementations, other or additional techniques are utilized. In one specific implementation, top dies 214 are placed on an adhesive layer in a grid-like pattern. Top dies 214 are then covered with top molding compound 216 so as to be embedded within top molding compound 216. Subsequently, top molding compound 216 is thinned to form top reconstituted wafer 202. In the implementations shown, top molding compound 216 is thinned to reach top dies 214. However, in other implementations, a layer of top molding compound 216 can remain than covers each of top dies 214.
  • Bottom reconstituted wafer 204 can be fabricated by utilizing the same, similar, or different means as top reconstituted wafer 202. Similar to top dies 214 of top reconstituted wafer 202, bottom reconstituted wafer 204 includes a plurality of bottom dies, of which bottom die 224 is shown in FIG. 2B. Furthermore, similar to top dies 214, the plurality of bottom dies can be arranged in a grid-like pattern, which can be different than the grid-like pattern of top dies 214 (not shown). Also, similar to top dies 214, bottom molding compound 226 (or more generally “bottom passivation 226”) forms a border around and flanks each of the plurality of bottom dies.
  • As shown in FIG. 2B, in some implementations, top reconstituted wafer 202 has top redistribution layer (top RDL) 228 a. Additionally or instead, in some implementations, bottom reconstituted wafer 204 has bottom redistribution layer (bottom RDL) 228 b. Top RDL 228 a is electrically connected top die 206 and bottom RDL 228 h is electrically connected to bottom die 224. Top RDL 228 a and bottom RDL 228 b include conductive material, such as copper and route respective top and bottom input and/or output (I/O) pads 230 and 232 of top die 206 and bottom die 224. Although only top RDL 228 a, bottom RDL 228 b, and top and bottom I/O pads 230 and 232 are shown, top reconstituted wafer 202 and bottom reconstituted wafer 204 each include a plurality of RDLs and I/O pads that are not visible in FIGS. 2A and 2B. Furthermore, any of the plurality of RDLs and I/O pads can be on either side of top reconstituted wafer 202 and bottom reconstituted wafer 204 and may include one or multiple levels or layers. As one example, top RDL 228 a and top I/O pad 230 are on top side 222, but may be on bottom side 240 in some implementations (or may not be present at all).
  • As shown in FIG. 2B, top RDL 228 a is on top die passivation 234 (which may also be referred to as “top die RDL passivation 234”) and bottom RDL 228 b is on bottom die passivation 236 (which may also be referred to as “bottom die RDL passivation 236”). Also, bottom RDL passivation 238 is on bottom RDL 228 b. Top die passivation 234, bottom die passivation 236, and bottom RDL passivation 238 each include dielectric material. For example, in the present implementation, top die passivation 234, bottom die passivation 236, and bottom RDL passivation 238 are dielectric polymers. In various implementations, top die passivation 234, bottom die passivation 236, and bottom RDL passivation 238 can be the same or different materials than one another.
  • As shown in FIGS. 2A and 2B, top reconstituted wafer 202 having top die 206 is stacked over bottom reconstituted wafer 204 having bottom die 224 to form reconstituted wafer stack 280. In one implementation, top reconstituted wafer 202 is fabricated separately from bottom reconstituted wafer 204 and top reconstituted wafer 202 is subsequently stacked over bottom reconstituted wafer 204. In other implementations, top reconstituted wafer 202 is formed over and/or on bottom reconstituted wafer 204, thereby stacking top reconstituted wafer 202 over bottom reconstituted wafer 204. While top reconstituted wafer 202 is stacked so that bottom side 240 faces downward, in other implementations, bottom side 240 can face upward. Also, in some implementations, bottom reconstituted wafer 204 is utilized as a carrier wafer.
  • In various implementations, any of top RDL 228 a, bottom RDL 228 b, top I/O pad 230, bottom I/O pad 232, top die passivation 234, bottom die passivation 236, and bottom RDL passivation 238 and/or other features can be formed prior to stacking top reconstituted wafer 202 over bottom reconstituted wafer 204. In some implementations, at least some of top RDL 228 a, top I/O pad 230, top die passivation 234, and/or other features can be formed after stacking top reconstituted wafer 202 over bottom reconstituted wafer 204.
  • In various implementations, stacking includes adhering the top reconstituted wafer to the bottom reconstituted wafer using a passivation layer. For example, in the present implementation, stacking includes adhering top reconstituted wafer 202 to bottom reconstituted wafer 204 using bottom RDL passivation 238. Thus, reconstituted wafer stack 280 can be thin to provide high package density, as in the implementation shown. Referring now to flowchart 100 of FIG. 1 and FIG. 2C, flowchart 100 includes interconnecting the top die of the top reconstituted wafer and the bottom die of the bottom reconstituted wafer through an insulation arrangement (action 172 in flowchart 100). FIG. 2C shows a portion of reconstituted wafer stack 282, which results from action 172 being performed on reconstituted wafer stack 280, in accordance with implementations of the present disclosure. In the present implementation, top die 206 of top reconstituted wafer 202 and bottom die 224 of bottom reconstituted wafer 224 are interconnected through insulation arrangement 242.
  • In the present implementation, insulation arrangement 242 includes top molding compound 216, bottom molding compound 226, top die passivation 234, bottom die passivation 236, bottom RDL passivation 238, and top RDL passivation 244. However, in other implementations, insulation arrangement 242 can have different constituents and/or additional constituents.
  • In some implementations, interconnecting comprises forming a conductive via through the insulation arrangement. However, interconnecting can be accomplished in various manners. FIG. 2C shows conductive via 250 formed through insulation arrangement 242. Forming conductive via 250 through insulation arrangement 242 can include drilling a hole through at least one of top molding compound 216, bottom molding compound 226, top die passivation 234, bottom die passivation 236, bottom RDL passivation 238, and top RDL passivation 244 (although a hole is not drilled through top RDL passivation 244 in the implementation shown). The hole can be drilled, for example, utilizing a mechanical drill, a laser, or other means.
  • In the present implementation, a hole is drilled through bottom molding compound 226, top die passivation 234, bottom die passivation 236, and bottom RDL passivation 238, as well as top RDL 228 a and bottom RDL 228 b of reconstituted wafer stack 280 in FIG. 2B. The hole can subsequently be filled with conductive material to form conductive via 250, thereby shorting top RDL 228 a and bottom RDL 228 b. Top RDL passivation 244 can later be formed on top RDL 228 a. Top RDL passivation 244 includes dielectric material, such as a dielectric polymer, as one example. It is noted that in various implementations, top RDL passivation 244 and/or other constituents can be formed prior to drilling the hole and the present disclosure is not limited by the specific implementation shown.
  • Thus, as described above, in the present implementation, top die 206 of top reconstituted wafer 202 and bottom die 224 of bottom reconstituted wafer 204 are interconnected by connecting top RDL 228 a to bottom RDL 228 b. More particularly, top die 206 and bottom die 224 are interconnected by forming conductive via 250 through top RDL 228 a and optionally through bottom RDL 228 b.
  • Referring now to flowchart 100 of FIG. 1 and FIG. 2C, flowchart 100 includes forming package terminals for connection to the top die of the top reconstituted wafer and the bottom die of the bottom reconstituted wafer (action 174 in flowchart 100). For example, FIG. 2C shows reconstituted wafer stack 282, which results from action 174 being performed on reconstituted wafer stack 280, in accordance with implementations of the present disclosure. In the present implementation, package terminal 252 is formed for connection to both top die 206 of top reconstituted wafer 202 and bottom die 224 of bottom reconstituted wafer 204. Package terminal 252 is also formed for connection to both top RDL 228 a and bottom RDL 228 b.
  • In the present implementation, package terminal 252 is formed in top RDL passivation 244 on under bump metallization (UBM) 254 and top RDL 228 a. It is noted that UBM 254 is optional. For example, in some implementations, package terminal 252 is formed in top RDL passivation 224 and on top RDL 228 a. Also, in the present implementation, package terminal 252 is a solder ball that is part of a ball grid array (BGA). While package terminal 252 is shown as a solder ball, package terminal 252 is exemplary and other types of package terminals can be employed in addition to or instead of a solder ball. In one implementation, for example, a conductive pad is utilized as a package terminal. Also, while only one package terminal is shown, a plurality of package terminals can be formed. For example, reconstituted wafer stack 282 can include, additional package terminals for connection to only one of top die 206 or bottom die 224 or other constituents (not shown). The additional package terminals can be formed concurrently or non-concurrently with package terminal 252, in accordance with various implementations.
  • It is noted that while flowchart 100 shows action 174 as being after action 172, in accordance with various implementations, action 174 can occur before, during, and/or after action 172.
  • Referring now to flowchart 100 of FIG. 1 and FIGS. 2C and 2D, flowchart 100 includes singulating the reconstituted wafer stack to form individual stacked packages (action 176 in flowchart 100). For example, in the present implementation, reconstituted wafer stack 282 of FIG. 2C is singulated to form stacked package 284. More particularly, reconstituted wafer stack 282 is singulated along stacked package region 218 shown in FIG. 2A. Other individual stacked packages are formed while singulating reconstituted wafer stack 282, which may be substantially similar to or different than stacked package 284.
  • While stacked package 284 includes only top die 206 and bottom die 224, in other implementations, stacked package 284 includes more than two dies. For example, stacked package region 218 can include additional dies within top reconstituted wafer 202 and/or bottom reconstituted wafer 204. As one example, top die 208 in FIG. 2A can be within stacked package region 218. Furthermore, the additional dies can be interconnected with each other, top die 206 and/or bottom die 224 through insulation arrangement 242 utilizing any of RDLs, conductive vias (e.g. conductive via 250), and or other means. For example, top RDL 228 a can interconnect top die 206 and top die 208. Also, while only top reconstituted wafer 202 and bottom reconstituted wafer 204 are shown, stacked package 284 can include dies from other reconstituted wafers. For example, one or more additional reconstituted wafers can be in any of reconstituted wafer stacks 280 and 282. Also, additional RDLs, passivation, and other constituents can be included with the one or more additional reconstituted wafers.
  • Furthermore, while only conductive via 250 is shown, more than one conductive via can be utilized to connect dies from different reconstituted wafers. In one implementation, the conductive vias extend through at least top molding compound 216 of insulation arrangement 242. Furthermore, where stacked package 284 includes a die from an additional reconstituted wafer (not shown), a conductive via (or other interconnect) may interconnect the die to only one of or to both of top die 206 and bottom die 224.
  • In the present implementation, package terminal 252 and/or other package terminals are formed prior to singulating reconstituted wafer stack 282 to form stacked package 284. However, in other implementations, package terminal 252 and/or other package terminals can be formed after reconstituted wafer stack 282 is singulated. Furthermore, in some implementations, top die 206 and bottom die 224 and/or other dies can be interconnected after singulating reconstituted wafer stack 282.
  • However, by forming package terminal 252 and/or other package terminals and interconnecting top die 206 and bottom die 224 and/or other dies prior to singulating reconstituted wafer stack 282, stacked package 284 can be simply and efficiently formed utilizing wafer level and/or panel (e.g. substrate) level processes. For example, in accordance with some implementations, the method illustrated by flowchart 100 is performed utilizing only wafer level and/or panel level processes on top reconstituted wafer 202 and bottom reconstituted wafer 204. Thus, among other advantages, stacked package 284 can be much thinner than packages that could be formed utilizing package level processes.
  • As shown in FIG. 2D, stacked package 284 includes top die 206 from top reconstituted wafer 202 situated over bottom die 224 from bottom reconstituted wafer 204. Top die 206 and bottom die 224 are insulated from one another by insulation arrangement 242. Insulation arrangement 242 includes top molding compound 216 that flanks top die 206 and bottom molding compound 226 that flanks bottom die 224, where top molding compound 216 is situated over bottom molding compound 226.
  • Top die 206 and bottom die 224 are interconnected through insulation arrangement 242. More particularly, top die 206 and bottom die 224 are interconnected through top molding compound 216. In the present implementation, top die 206 and bottom die 224 are interconnected through conductive via 250, which extends within insulation arrangement 242. Top die 206 has top RDL 228 a, and bottom die 224 has bottom RDL 228 a that is connected to top RDL 228 a through conductive via 250.
  • Thus, as described above, top die 206 and bottom die 224 can be interconnected through insulation arrangement 242, effectively and efficiently. For example, insulation arrangement 242 can facilitate interconnection between top die 206 and bottom die 224 while providing sufficient mechanical support for stacked package 284. Furthermore, top RDL 228 a and bottom RDL 228 b can be easily interconnected by connecting top RDL 228 a to bottom RDL 228 b using, for example, conductive via 250 formed through insulation arrangement 242.
  • By utilizing RDLs, such as top RDL 228 a and bottom RDL 228 b, and wafer and/or panel level processes, stacked package 284 can advantageously support higher levels of functionality while accommodating additional circuitry and/or dies without complicating packaging and reducing package density. For example, additional RDLs, I/O pads, and/or dies can easily be incorporated into stacked package 284 as desired without substantially complicating packaging and increasing package density.
  • Also, in various implementations, a carrier wafer is utilized to fabricate bottom reconstituted wafer 204 and is utilized as part of stacked package 284. For example, the carrier wafer can be a silicon wafer or a substrate panel that is integrated into stacked package 284. For example, the carrier wafer could be integrated into stacked package 284 as a heat sink. In one implementation, the carrier wafer is a copper leadframe panel.
  • Referring now to FIG. 3, FIG. 3 presents a cross-sectional view of stacked package 300, according to an implementation of the present disclosure. Stacked package 300 can be fabricated utilizing the method for manufacturing a stacked package illustrated by flowchart 100. Stacked package 300 includes top die 306, top molding compound 316, bottom die 324, bottom molding compound 326, top RDL 328 a, bottom RDL 328 b, top I/O pad 330, bottom I/O pad 332, top die passivation 334, bottom die passivation 336, bottom RDL passivation 338, top RDL passivation 344, insulation arrangement 342, and conductive via 350, corresponding respectively to top die 206, top molding compound 216, bottom die 224, bottom molding compound 226, top RDL 228 a, bottom RDL 228 b, top I/O pad 230, bottom I/O pad 232, top die passivation 234, bottom die passivation 236, bottom RDL passivation 238, top RDL passivation 244, insulation arrangement 242, and conductive via 250 in stacked package 284 of FIG. 2D.
  • While stacked package 284 has package terminal 252 on top side 222 of top reconstituted wafer 202, at least one package terminal can be formed on bottom side 256 of bottom reconstituted wafer 204 in addition to or instead of on top side 222. For example, stacked package 300 includes package terminals 352 a, 352 b, 352 c, 352 d, 352 e, 352 f, and 352 g on bottom die 324 and bottom side 356. Package terminals 352 a, 352 b, 352 c, 352 d, 352 e, 352 f, and 352 g may be only for connection to bottom die 324 or may also or instead be for connection to top die 306 and/or other dies. Stacked package 300 also includes package terminals 352 h and 352 i on conductive interface 358 and bottom side 356. Like package terminal 252 in FIG. 2C, package terminals 352 a, 352 b, 352 c, 352 d, 352 e, 352 f, 352 g, 352 h and 352 i can be solder balls that are part of a BGA or can be other types of package terminals. While not shown, in some implementations, stacked package 300 has additional solder balls on molding compound 326 for mechanical stability.
  • Stacked package 300 also has electrical component 360 connected to top die 306 through top RDL 328 a. Electrical component 360 is an individual die in the present implementation, is on top RDL passivation 344, and is connected to top die 306 through top RDL passivation 344 by interconnects 362 a and 362 b. Electrical component 360 can also be connected to top die 306 through other RDLs and/or other interconnects not shown in FIG. 3. Furthermore, at least one additional individual die can be connected to top die 306 in a same or different manner than individual die 306. In one implementation, electrical component 360 is connected to top die 306 prior to singulating a reconstituted wafer stack to form stacked package 300. In another implementation, electrical component 360 is connected to top die 306 after singulating a reconstituted wafer stack to form stacked package 300 (e.g., after action 176). Furthermore, in some implementations, electrical component 360 is on bottom side 356 of stacked package 300.
  • Thus, as described above, implementations of the present disclosure result in a stacked package having a top die from a top reconstituted wafer and a bottom die from a bottom reconstituted wafer. In various implementations, complications in packaging and reduced package density can advantageously be avoided or minimized while still providing for a stacked package that has a high level of functionality. Furthermore, it will be appreciated that implementations of the present disclosure offer significant flexibility in coping with limited component space and layout options.
  • From the above description it is manifest that various techniques can be used for implementing the concepts described in the present application without departing from the scope of those concepts. Moreover, while the concepts have been described with specific reference to certain implementations, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of those concepts. As such, the described implementations are to be considered in all respects as illustrative and not restrictive. It should also be understood that the present application is not limited to the particular implementations described herein, but many rearrangements, modifications, and substitutions are possible without departing from the scope of the present disclosure.

Claims (20)

1. A stacked package comprising:
a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer;
said top die and said bottom die being insulated from one another by an insulation arrangement;
said top die and said bottom die being interconnected through said insulation arrangement.
2. The stacked package of claim 1, wherein said top die and said bottom die are interconnected through a conductive via.
3. The stacked package of claim 2, wherein said conductive via extends within said insulation arrangement.
4. The stacked package of claim 1, wherein said top die has a top redistribution layer, and said bottom die has a bottom redistribution layer that is connected to said top redistribution layer.
5. The method of claim 1, wherein said insulation arrangement comprises a top molding compound that flanks said top die and a bottom molding compound that flanks said bottom die.
6. The method of claim 5, wherein said top molding compound is situated over said bottom molding compound.
7. The method of claim 1, wherein said insulation arrangement comprises a top molding compound that flanks said top die, said top die and said bottom die being interconnected through at least said top molding compound.
8. A method for manufacturing a stacked package, said method comprising:
stacking a top reconstituted wafer having a top die over a bottom reconstituted wafer having a bottom die to form a reconstituted wafer stack;
interconnecting said top die of said top reconstituted wafer and said bottom die of said bottom reconstituted wafer through an insulation arrangement;
singulating said reconstituted wafer stack to form said stacked package.
9. The method of claim 8, wherein said interconnecting comprises forming a conductive via through said insulation arrangement.
10. The method of claim 8, wherein said insulation arrangement comprises a top molding compound that flanks said top die of said top reconstituted wafer and a bottom molding compound that flanks said bottom die of said bottom reconstituted wafer.
11. The method of claim 10, wherein said top molding compound is situated over said bottom molding compound.
12. The method of claim 8, further comprising forming a package terminal for connection to said top die of said top reconstituted wafer and said bottom die of said bottom reconstituted wafer prior to said singulating.
13. The method of claim 8, wherein said stacking comprises adhering said top reconstituted wafer to said bottom reconstituted wafer using a passivation layer.
14. A method for manufacturing a stacked package, said method comprising:
stacking a top reconstituted wafer having a top die over a bottom reconstituted wafer having a bottom die to form a reconstituted wafer stack, said top die having a top redistribution layer, and said bottom die having a bottom redistribution layer;
interconnecting said top die of said top reconstituted wafer and said bottom die of said bottom reconstituted wafer by connecting said top redistribution layer to said bottom redistribution layer;
singulating said reconstituted wafer stack to form said stacked package.
15. The method of claim 14, wherein said interconnecting comprises forming a conductive via through said top redistribution layer.
16. The method of claim 14, wherein said interconnecting comprises forming a conductive via through said bottom redistribution layer.
17. The method of claim 14, wherein said interconnecting is through an insulation arrangement.
18. The method of claim 14, further comprising forming a package terminal for connection to said top die and said bottom die prior to said singulating.
19. The method of claim 14, wherein said stacking comprises adhering said top reconstituted wafer to said bottom reconstituted wafer using a passivation layer.
20. The method of claim 19, wherein said passivation layer is a bottom redistribution layer passivation.
US13/325,951 2011-12-14 2011-12-14 Stacked Packaging Using Reconstituted Wafers Abandoned US20130154106A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/325,951 US20130154106A1 (en) 2011-12-14 2011-12-14 Stacked Packaging Using Reconstituted Wafers

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US13/325,951 US20130154106A1 (en) 2011-12-14 2011-12-14 Stacked Packaging Using Reconstituted Wafers
EP12005904.3A EP2605279A1 (en) 2011-12-14 2012-08-16 Stacked packaging using reconstituted wafers
TW101132865A TWI555160B (en) 2011-12-14 2012-09-07 Stacked packaging using reconstituted wafers
KR1020120099951A KR20130069338A (en) 2011-12-14 2012-09-10 Stacked packaging using reconstituted wafers
CN201210365311.9A CN103165585B (en) 2011-12-14 2012-09-26 The stacked package of wafer is reproduced in use
CN2012204980772U CN202816934U (en) 2011-12-14 2012-09-26 Stacked package
HK13111040.2A HK1183744A1 (en) 2011-12-14 2013-09-27 Stacked packaging using reconstituted wafers
US14/175,985 US9293393B2 (en) 2011-12-14 2014-02-07 Stacked packaging using reconstituted wafers
US15/018,818 US20160155728A1 (en) 2011-12-14 2016-02-08 Stacked packaging using reconstituted wafers

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/175,985 Continuation US9293393B2 (en) 2011-12-14 2014-02-07 Stacked packaging using reconstituted wafers

Publications (1)

Publication Number Publication Date
US20130154106A1 true US20130154106A1 (en) 2013-06-20

Family

ID=46924193

Family Applications (3)

Application Number Title Priority Date Filing Date
US13/325,951 Abandoned US20130154106A1 (en) 2011-12-14 2011-12-14 Stacked Packaging Using Reconstituted Wafers
US14/175,985 Active US9293393B2 (en) 2011-12-14 2014-02-07 Stacked packaging using reconstituted wafers
US15/018,818 Abandoned US20160155728A1 (en) 2011-12-14 2016-02-08 Stacked packaging using reconstituted wafers

Family Applications After (2)

Application Number Title Priority Date Filing Date
US14/175,985 Active US9293393B2 (en) 2011-12-14 2014-02-07 Stacked packaging using reconstituted wafers
US15/018,818 Abandoned US20160155728A1 (en) 2011-12-14 2016-02-08 Stacked packaging using reconstituted wafers

Country Status (6)

Country Link
US (3) US20130154106A1 (en)
EP (1) EP2605279A1 (en)
KR (1) KR20130069338A (en)
CN (2) CN103165585B (en)
HK (1) HK1183744A1 (en)
TW (1) TWI555160B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140090882A1 (en) * 2012-09-28 2014-04-03 Taiwan Semiconductor Manufacturing Company Limited Pad structure
US20140332810A1 (en) * 2013-05-09 2014-11-13 International Business Machines Corporation Temporary liquid thermal interface material for surface tension adhesion and thermal control
CN104517934A (en) * 2013-09-27 2015-04-15 英特尔公司 Method for manufacturing interconnected and stacked semiconductor devices
GB2520405A (en) * 2013-09-27 2015-05-20 Intel Corp Method for interconnecting stacked semiconductor devices
US20160358891A1 (en) * 2014-12-15 2016-12-08 Intel Corporation Opossum-die package-on-package apparatus
US20170301651A1 (en) * 2016-04-18 2017-10-19 Broadcom Corporation Wafer level system in package (sip) using a reconstituted wafer and method of making
RU2664894C1 (en) * 2017-08-14 2018-08-23 Интел Корпорейшн Method of connecting multilevel semiconductor devices

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9117715B2 (en) * 2012-07-18 2015-08-25 Hong Kong Applied Science and Technology Research Institute Company Limited Wafer-level device packaging
US9806059B1 (en) * 2016-05-12 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
KR102005350B1 (en) * 2017-01-03 2019-07-31 삼성전자주식회사 Fan-out semiconductor package
US10763242B2 (en) 2017-06-23 2020-09-01 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US20190181120A1 (en) * 2017-12-08 2019-06-13 Infineon Technologies Ag Semiconductor Package with Air Cavity

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090053858A1 (en) * 2007-08-24 2009-02-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor package using redistribution substrate
US20100148360A1 (en) * 2008-12-12 2010-06-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
US8298866B1 (en) * 2002-11-08 2012-10-30 Amkor Technology, Inc. Wafer level package and fabrication method
US8304913B2 (en) * 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US20130193578A1 (en) * 2011-04-13 2013-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon vias for semicondcutor substrate and method of manufacture
US20130200528A1 (en) * 2008-12-12 2013-08-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

Family Cites Families (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198963A (en) 1991-11-21 1993-03-30 Motorola, Inc. Multiple integrated circuit module which simplifies handling and testing
US6400573B1 (en) * 1993-02-09 2002-06-04 Texas Instruments Incorporated Multi-chip integrated circuit module
US5851845A (en) * 1995-12-18 1998-12-22 Micron Technology, Inc. Process for packaging a semiconductor die using dicing and testing
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
JP3792445B2 (en) 1999-03-30 2006-07-05 日本特殊陶業株式会社 Wiring board with capacitor
TW411037U (en) 1999-06-11 2000-11-01 Ind Tech Res Inst Integrated circuit packaging structure with dual directions of thermal conduction path
JP2001203318A (en) 1999-12-17 2001-07-27 Texas Instr Inc <Ti> Semiconductor assembly having plural flip-chips
JP3597754B2 (en) 2000-04-24 2004-12-08 Necエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
CN1278413C (en) 2000-09-25 2006-10-04 揖斐电株式会社 Semiconductor element and method of manufacturing and multi-layer printed circuit board and mfg. method
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6525407B1 (en) 2001-06-29 2003-02-25 Novellus Systems, Inc. Integrated circuit package
JP4595265B2 (en) 2001-08-13 2010-12-08 日本テキサス・インスツルメンツ株式会社 Manufacturing method of semiconductor device
KR100486832B1 (en) * 2002-02-06 2005-05-03 삼성전자주식회사 Semiconductor Chip, Chip Stack Package And Manufacturing Method
US7633765B1 (en) * 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7573136B2 (en) 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
JP2004079701A (en) 2002-08-14 2004-03-11 Sony Corp Semiconductor device and its manufacturing method
TWI278048B (en) 2003-11-10 2007-04-01 Casio Computer Co Ltd Semiconductor device and its manufacturing method
US7071715B2 (en) 2004-01-16 2006-07-04 Formfactor, Inc. Probe card configuration for low mechanical flexural strength electrical routing substrates
US7095108B2 (en) 2004-05-05 2006-08-22 Intel Corporation Array capacitors in interposers, and methods of using same
US7786591B2 (en) 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
TWI245388B (en) 2005-01-06 2005-12-11 Phoenix Prec Technology Corp Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same
TWI269423B (en) 2005-02-02 2006-12-21 Phoenix Prec Technology Corp Substrate assembly with direct electrical connection as a semiconductor package
TWI264094B (en) 2005-02-22 2006-10-11 Phoenix Prec Technology Corp Package structure with chip embedded in substrate
US7326592B2 (en) * 2005-04-04 2008-02-05 Infineon Technologies Ag Stacked die package
US7208345B2 (en) * 2005-05-11 2007-04-24 Infineon Technologies Ag Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device
JP4551321B2 (en) * 2005-07-21 2010-09-29 新光電気工業株式会社 Electronic component mounting structure and manufacturing method thereof
US7262615B2 (en) 2005-10-31 2007-08-28 Freescale Semiconductor, Inc. Method and apparatus for testing a semiconductor structure having top-side and bottom-side connections
US7585702B1 (en) 2005-11-08 2009-09-08 Altera Corporation Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate
US7981726B2 (en) 2005-12-12 2011-07-19 Intel Corporation Copper plating connection for multi-die stack in substrate package
SG135074A1 (en) * 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7714453B2 (en) 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
DE102006032251A1 (en) 2006-07-12 2008-01-17 Infineon Technologies Ag Method for producing chip packages and chip package produced in this way
US7473577B2 (en) 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
US7829438B2 (en) * 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US8513789B2 (en) * 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7901989B2 (en) * 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
KR100840788B1 (en) 2006-12-05 2008-06-23 삼성전자주식회사 Chip stacking packages and method of manufacturing the same
JP2008166373A (en) 2006-12-27 2008-07-17 Nec Electronics Corp Semiconductor device and its manufacturing method
US20080157322A1 (en) 2006-12-27 2008-07-03 Jia Miao Tang Double side stacked die package
JP4926692B2 (en) 2006-12-27 2012-05-09 新光電気工業株式会社 Wiring board, manufacturing method thereof, and semiconductor device
DE102007012155B4 (en) * 2007-03-12 2015-01-22 Intel Mobile Communications GmbH Shaped bodies and benefits with semiconductor chips and method of making the benefit
US7675163B2 (en) 2007-03-21 2010-03-09 Sun Microsystems, Inc. Carbon nanotubes for active direct and indirect cooling of electronics device
DE102007019552B4 (en) 2007-04-25 2009-12-17 Infineon Technologies Ag Method for producing a substrate with feedthrough and substrate and semiconductor module with feedthrough
KR100923562B1 (en) 2007-05-08 2009-10-27 삼성전자주식회사 Semiconductor package and method of forming the same
KR100865125B1 (en) 2007-06-12 2008-10-24 삼성전기주식회사 Semiconductor and method for manufacturing thereof
WO2009017758A2 (en) * 2007-07-27 2009-02-05 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
CN101861646B (en) * 2007-08-03 2015-03-18 泰塞拉公司 Stack packages using reconstituted wafers
KR101213175B1 (en) 2007-08-20 2012-12-18 삼성전자주식회사 Semiconductor package having memory devices stacked on logic chip
US7834464B2 (en) * 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
US7618849B2 (en) 2007-10-22 2009-11-17 Broadcom Corporation Integrated circuit package with etched leadframe for package-on-package interconnects
JP5341337B2 (en) * 2007-10-25 2013-11-13 スパンション エルエルシー Semiconductor device and manufacturing method thereof
JP2009135398A (en) 2007-11-29 2009-06-18 Ibiden Co Ltd Combination substrate
US7956453B1 (en) * 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US8030136B2 (en) 2008-05-15 2011-10-04 Stats Chippac, Ltd. Semiconductor device and method of conforming conductive vias between insulating layers in saw streets
US7741156B2 (en) * 2008-05-27 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
US8030208B2 (en) * 2008-06-02 2011-10-04 Hong Kong Applied Science and Technology Research Institute Company Limited Bonding method for through-silicon-via based 3D wafer stacking
US8106504B2 (en) * 2008-09-25 2012-01-31 King Dragon International Inc. Stacking package structure with chip embedded inside and die having through silicon via and method of the same
US8350377B2 (en) 2008-09-25 2013-01-08 Wen-Kun Yang Semiconductor device package structure and method for the same
US7705447B2 (en) 2008-09-29 2010-04-27 Intel Corporation Input/output package architectures, and methods of using same
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US20100133534A1 (en) 2008-12-03 2010-06-03 Byung Tai Do Integrated circuit packaging system with interposer and flip chip and method of manufacture thereof
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
CN102422412A (en) * 2009-03-13 2012-04-18 德塞拉股份有限公司 Stacked microelectronic assemblies having vias extending through bond pads
JP5330065B2 (en) * 2009-04-13 2013-10-30 新光電気工業株式会社 Electronic device and manufacturing method thereof
US8263434B2 (en) 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
WO2011036819A1 (en) * 2009-09-28 2011-03-31 株式会社 東芝 Method for manufacturing semiconductor device
KR101086972B1 (en) 2009-10-01 2011-11-29 앰코 테크놀로지 코리아 주식회사 Wafer Level Package having Through Silicon Via
US20110241185A1 (en) 2010-04-05 2011-10-06 International Business Machines Corporation Signal shielding through-substrate vias for 3d integration
US8455995B2 (en) 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
KR101680082B1 (en) 2010-05-07 2016-11-29 삼성전자 주식회사 Wafer level package and methods for fabricating the same
US8674513B2 (en) 2010-05-13 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for substrate
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8847376B2 (en) * 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
TWI398943B (en) 2010-08-25 2013-06-11 Advanced Semiconductor Eng Semiconductor package structure and manufacturing process thereof
US8518746B2 (en) * 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8421193B2 (en) * 2010-11-18 2013-04-16 Nanya Technology Corporation Integrated circuit device having through via and method for preparing the same
TWI416679B (en) 2010-12-06 2013-11-21 Ind Tech Res Inst Semiconductor structure and manufacturing method thereof
US8299371B2 (en) 2010-12-20 2012-10-30 Endicott Interconnect Technologies, Inc. Circuitized substrate with dielectric interposer assembly and method
US8617987B2 (en) 2010-12-30 2013-12-31 Stmicroelectronics Pte Ltd. Through hole via filling using electroless plating
US20120168935A1 (en) * 2011-01-03 2012-07-05 Nanya Technology Corp. Integrated circuit device and method for preparing the same
KR101817159B1 (en) 2011-02-17 2018-02-22 삼성전자 주식회사 Semiconductor package having TSV interposer and method of manufacturing the same
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US9064781B2 (en) 2011-03-03 2015-06-23 Broadcom Corporation Package 3D interconnection and method of making same
US8535981B2 (en) 2011-03-10 2013-09-17 Stats Chippac Ltd. Integrated circuit package-on-package system with underfilling structures and method of manufacture thereof
US8779562B2 (en) 2011-03-24 2014-07-15 Stats Chippac Ltd. Integrated circuit packaging system with interposer shield and method of manufacture thereof
US8389333B2 (en) * 2011-05-26 2013-03-05 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die
TWI506738B (en) 2011-06-09 2015-11-01 Unimicron Technology Corp Semiconductor package and fabrication method thereof
US8530277B2 (en) 2011-06-16 2013-09-10 Stats Chippac Ltd. Integrated circuit packaging system with package on package support and method of manufacture thereof
US20120319293A1 (en) 2011-06-17 2012-12-20 Bok Eng Cheah Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi-channel communication pathway in same, and method of enabling electrical communication between components of a stacked-die package
US20130000968A1 (en) 2011-06-30 2013-01-03 Broadcom Corporation 1-Layer Interposer Substrate With Through-Substrate Posts
KR20130022821A (en) * 2011-08-26 2013-03-07 삼성전자주식회사 Stacked package and method of manufacturing the same
US9013037B2 (en) 2011-09-14 2015-04-21 Stmicroelectronics Pte Ltd. Semiconductor package with improved pillar bump process and structure
US8816404B2 (en) * 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US8513057B2 (en) * 2011-09-16 2013-08-20 Stats Chippac Ltd. Integrated circuit packaging system with routable underlayer and method of manufacture thereof
US9177832B2 (en) * 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
US8587123B2 (en) 2011-09-27 2013-11-19 Broadcom Corporation Multi-chip and multi-substrate reconstitution based packaging
US8916481B2 (en) * 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8922013B2 (en) 2011-11-08 2014-12-30 Stmicroelectronics Pte Ltd. Through via package
US8659126B2 (en) 2011-12-07 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit ground shielding structure
US20130154091A1 (en) * 2011-12-14 2013-06-20 Jason R. Wright Semiconductor device packaging using encapsulated conductive balls for package-on-package back side coupling
US9548251B2 (en) 2012-01-12 2017-01-17 Broadcom Corporation Semiconductor interposer having a cavity for intra-interposer die
US8766460B2 (en) * 2012-02-02 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package with interposer frame and method of making the same
US8946072B2 (en) * 2012-02-02 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. No-flow underfill for package with interposer frame
US20140225248A1 (en) * 2013-02-13 2014-08-14 Qualcomm Incorporated Power distribution and thermal solution for direct stacked integrated circuits
US8941225B2 (en) * 2013-04-18 2015-01-27 Sts Semiconductor & Telecommunications Co., Ltd. Integrated circuit package and method for manufacturing the same
TWI491017B (en) * 2013-04-25 2015-07-01 Siliconware Prec Ind Co Ltd Semiconductor package and method of manufacture
US9685414B2 (en) * 2013-06-26 2017-06-20 Intel Corporation Package assembly for embedded die and associated techniques and configurations

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8298866B1 (en) * 2002-11-08 2012-10-30 Amkor Technology, Inc. Wafer level package and fabrication method
US20090053858A1 (en) * 2007-08-24 2009-02-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor package using redistribution substrate
US20100148360A1 (en) * 2008-12-12 2010-06-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
US20130200528A1 (en) * 2008-12-12 2013-08-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
US8304913B2 (en) * 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US20130193578A1 (en) * 2011-04-13 2013-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon vias for semicondcutor substrate and method of manufacture

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9699897B2 (en) * 2012-09-28 2017-07-04 Taiwan Semiconductor Manufacturing Company Limited Pad structure
US20140090882A1 (en) * 2012-09-28 2014-04-03 Taiwan Semiconductor Manufacturing Company Limited Pad structure
US20140332810A1 (en) * 2013-05-09 2014-11-13 International Business Machines Corporation Temporary liquid thermal interface material for surface tension adhesion and thermal control
US9269603B2 (en) * 2013-05-09 2016-02-23 Globalfoundries Inc. Temporary liquid thermal interface material for surface tension adhesion and thermal control
CN107579011A (en) * 2013-09-27 2018-01-12 英特尔公司 Method for the semiconductor devices of interconnection stack
GB2520405A (en) * 2013-09-27 2015-05-20 Intel Corp Method for interconnecting stacked semiconductor devices
KR101834096B1 (en) * 2013-09-27 2018-03-02 인텔 코포레이션 Method for interconnecting stacked semiconductor devices
TWI573206B (en) * 2013-09-27 2017-03-01 英特爾股份有限公司 Stacked semiconductor devices and method for interconnecting stacked semiconductor devices
US9627358B2 (en) * 2013-09-27 2017-04-18 Intel Corporation Method for interconnecting stacked semiconductor devices
EP3050101A4 (en) * 2013-09-27 2017-05-24 Intel Corporation Method for interconnecting stacked semiconductor devices
US20150325550A1 (en) * 2013-09-27 2015-11-12 Junfeng Zhao Method for interconnecting stacked semiconductor devices
RU2629904C2 (en) * 2013-09-27 2017-09-04 Интел Корпорейшн Method of connecting multilevel semiconductor devices
US9899354B2 (en) 2013-09-27 2018-02-20 Intel Corporation Method for interconnecting stacked semiconductor devices
GB2520405B (en) * 2013-09-27 2018-01-17 Intel Corp Method for interconnecting stacked semiconductor devices
CN104517934A (en) * 2013-09-27 2015-04-15 英特尔公司 Method for manufacturing interconnected and stacked semiconductor devices
US10643975B2 (en) 2013-09-27 2020-05-05 Intel Corporation Method for interconnecting stacked semiconductor devices
US20160358891A1 (en) * 2014-12-15 2016-12-08 Intel Corporation Opossum-die package-on-package apparatus
US9842827B2 (en) * 2016-04-18 2017-12-12 Avago Technologies General Ip (Singapore) Pte. Ltd. Wafer level system in package (SiP) using a reconstituted wafer and method of making
US20170301651A1 (en) * 2016-04-18 2017-10-19 Broadcom Corporation Wafer level system in package (sip) using a reconstituted wafer and method of making
RU2664894C1 (en) * 2017-08-14 2018-08-23 Интел Корпорейшн Method of connecting multilevel semiconductor devices

Also Published As

Publication number Publication date
TWI555160B (en) 2016-10-21
KR20130069338A (en) 2013-06-26
US20140151900A1 (en) 2014-06-05
HK1183744A1 (en) 2016-12-30
CN103165585B (en) 2016-05-04
CN202816934U (en) 2013-03-20
TW201330212A (en) 2013-07-16
CN103165585A (en) 2013-06-19
EP2605279A1 (en) 2013-06-19
US9293393B2 (en) 2016-03-22
US20160155728A1 (en) 2016-06-02

Similar Documents

Publication Publication Date Title
US10283400B1 (en) Semiconductor device package and manufacturing method thereof
KR101688741B1 (en) Novel three dimensional integrated circuits stacking approach
US10559546B2 (en) Package on package structure and method for forming the same
KR101884971B1 (en) Fan-out stacked system in package(sip) having dummy dies and methods of making the same
US10741416B2 (en) Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB
KR20200010521A (en) A semiconductor device and a method of making a semiconductor device
US9490167B2 (en) Pop structures and methods of forming the same
US9633974B2 (en) System in package fan out stacking architecture and process flow
TWI621228B (en) Semiconductor package and method for forming the same
TWI538145B (en) Package structure and methods of forming the same
TWI541915B (en) Semiconductor device and method of forming low profile 3d fan-out package
KR101939015B1 (en) A package that is a vertical stacking system including a first level die, a stack of back level second level dies, and a third level die having corresponding first, second and third rewiring layers and a method of making the same
US10269778B2 (en) Package on package (PoP) bonding structures
KR101730691B1 (en) Mechanisms for forming package structure
US9553041B1 (en) Semiconductor device package and manufacturing method thereof
US10497668B2 (en) Integrated fan-out package including voltage regulators and methods forming same
US10134706B2 (en) Warpage control of semiconductor die package
US9768143B2 (en) Hybrid bonding with through substrate via (TSV)
TWI605526B (en) Fan out system in package and method for forming the same
TWI514542B (en) Die package with openings surrounding end-portions of through package vias (tpvs) and package on package (pop) using the die package
US20160079171A1 (en) Semiconductor package including an embedded surface mount device and method of forming the same
US9978665B2 (en) Semiconductor device and method of forming low profile fan-out package with vertical interconnection units
US10672647B2 (en) Wafer level chip scale packaging intermediate structure apparatus and method
US9799620B2 (en) Warpage reduction and adhesion improvement of semiconductor die package
US8878360B2 (en) Stacked fan-out semiconductor chip

Legal Events

Date Code Title Description
AS Assignment

Owner name: BROADCOM CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HU, KEVIN KUNZHONG;ZHAO, SAM ZIQUN;KHAN, REZAUR RAHMAN;AND OTHERS;REEL/FRAME:027388/0576

Effective date: 20111212

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001

Effective date: 20160201

Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001

Effective date: 20160201

AS Assignment

Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:041706/0001

Effective date: 20170120

Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:041706/0001

Effective date: 20170120

AS Assignment

Owner name: BROADCOM CORPORATION, CALIFORNIA

Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041712/0001

Effective date: 20170119