US8941225B2 - Integrated circuit package and method for manufacturing the same - Google Patents
Integrated circuit package and method for manufacturing the same Download PDFInfo
- Publication number
- US8941225B2 US8941225B2 US13/932,930 US201313932930A US8941225B2 US 8941225 B2 US8941225 B2 US 8941225B2 US 201313932930 A US201313932930 A US 201313932930A US 8941225 B2 US8941225 B2 US 8941225B2
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- substrate
- semiconductor chip
- integrated circuit
- circuit package
- interposer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 111
- 239000004065 semiconductor Substances 0.000 claims abstract description 93
- 238000000465 moulding Methods 0.000 claims abstract description 31
- 229910000679 solder Inorganic materials 0.000 claims abstract description 28
- 239000008393 encapsulating agent Substances 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 description 4
- 238000003754 machining Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000000470 constituent Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
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- 238000012536 packaging technology Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Definitions
- the present invention relates to an integrated circuit package, and more particularly to a stacked integrated circuit package having a package-on-package structure and a method for manufacturing the same.
- Integrated circuit packaging is a technology of forming input/output signal terminals to a main board using a lead frame or a printed circuit board and molding the terminals with a encapsulant to protect a semiconductor chip such as a single device and an integrated circuit, formed by stacking electric circuits and wires, from various external environmental factors such as dust, moisture, and electric and mechanical loads and to optimize or maximize electrical performance of the semiconductor chip.
- SIP System in Package
- POP Package on Package
- TSV through mold via
- FIGS. 1A to 1E are cross-sectional views illustrating the processes of manufacturing a conventional TMV-type stacked integrated circuit package. The method for manufacturing the conventional TMV-type stacked integrated circuit package is described below with reference to FIGS. 1A to 1E .
- a substrate 10 provided with wire terminals 11 , external terminals 12 and via contacts 13 electrically connecting the wire terminals 11 and the external terminals 12 is first prepared.
- the semiconductor chip 20 and solder balls 30 are attached to the substrate 10 .
- the semiconductor chip 20 is connected to the wire terminals 11 on the substrate 10 via conductive bumps 22 in a flip chip bonding manner, with the circuit pattern 21 of the semiconductor chip 20 facing downward.
- the solder balls 30 are formed at the edge of the substrate 10 .
- the space between the semiconductor chip 20 and the substrate 10 is filled with an underfill 41 .
- molding is performed on the entire upper surfaces of the semiconductor chip 20 and the substrate 10 using the encapsulant to form a molding portion 40 .
- the molding portion 40 is subjected to etching through laser machining to form a via hole 50 such that a part of the solder ball 30 on the upper surface of the substrate 10 is exposed.
- an upper integrated circuit package 60 is stacked on the lower integrated circuit package which is formed through the processes shown in FIGS. 1A to 1D , and then solder balls are formed on the bottom surface of the substrate 10 .
- the present invention has been made in view of the above problems, and it is an object of the present invention to provide a stacked integrated circuit package which can substantially address various problems caused by limitations and disadvantages of the conventional technology and a method for manufacturing the same.
- TMV through mold via
- a stacked integrated circuit package including a first integrated circuit package comprising a first substrate provided with a circuit pattern, a first semiconductor chip mounted on the first substrate to be electrically connected to the circuit pattern, and a first molding portion formed such that at least one surface of the first semiconductor chip is exposed, an interposer mounted on the first substrate to be electrically connected to the circuit pattern of the first substrate by a first solder bump, the interposer being provided with an opening to accommodate the first semiconductor chip, and a second integrated circuit package stacked on the first integrated circuit package and the interposer and electrically connected to the interposer by a second solder bump, the second integrated circuit package comprising a second substrate provided with a circuit pattern, a second semiconductor chip mounted on the second substrate to be electrically connected to the circuit pattern, and a second molding portion formed to completely seal one surface of the second semiconductor chip and the second substrate.
- At least one of the first semiconductor chip and the second semiconductor chip may be mounted on the first substrate or the second substrate through a flip chip boding structure.
- At least one of the first semiconductor chip and the second semiconductor chip may be mounted on the first substrate or the second substrate through a wire bonding structure.
- the interposer may be provided with a layer structure identical to a layer structure of at least one of the first substrate and the second substrate.
- the interposer may include an insulating substrate, a circuit pattern formed on each of an upper surface and a lower surface of the insulating substrate, and a via contact provided to electrically connect the circuit pattern on the upper surface to the circuit pattern on the lower surface.
- the interposer may be provided with a lead frame or a layer structure allowing interconnection.
- a method for manufacturing a stacked integrated circuit package comprising the steps of mounting a first semiconductor chip on a first substrate provided with a circuit pattern, mounting an interposer on the first substrate, the interposer being provided with an opening to accommodate the first semiconductor chip, filling a space between the first substrate and the first semiconductor chip, between the first substrate and the interposer and between the first semiconductor chip and the interposer with an encapsulant such that at least one surface of the first substrate is exposed, and stacking, on the first semiconductor chip, an integrated circuit package including a second substrate and a second semiconductor chip mounted on the second substrate the second semiconductor chip, such that the second semiconductor chip is electrically connected to the first semiconductor chip via the interposer.
- At least one of the first semiconductor chip and the second semiconductor chip may be mounted on the first substrate or the second substrate in a flip chip bonding process.
- At least one of the first semiconductor chip and the second semiconductor chip may be mounted on the first substrate or the second substrate in a wire bonding process.
- the step of filling may include a film assisted molding (FAM) process.
- FAM film assisted molding
- FIGS. 1A to 1E are cross-sectional views illustrating the processes of manufacturing a conventional TMV-type stacked integrated circuit package
- FIG. 2 is a cross-sectional view showing the structure of a stacked integrated circuit package according to an exemplary embodiment of the present invention
- FIG. 3 is a plan view showing the configuration of an interposer according to an embodiment of the present invention.
- FIGS. 4A to 4F are cross-sectional views illustrating the processes of manufacturing a stacked integrated circuit package according to one embodiment of the present invention.
- FIG. 5 is a cross-sectional view showing an interposer according to another embodiment of the present invention.
- FIG. 2 is a cross-sectional view showing the structure of a stacked integrated circuit package according to an exemplary embodiment of the present invention.
- FIG. 3 is a plan view showing the configuration of an interposer according to an embodiment of the present invention.
- FIGS. 4A to 4F are cross-sectional views illustrating the processes of manufacturing a stacked integrated circuit package according to one embodiment of the present invention.
- a stacked integrated circuit package of the illustrated embodiment includes a lower (first) integrated circuit package 100 , an upper (second) integrated circuit package 200 stacked on the lower integrated circuit package 100 , and an interposer 300 interposed between the lower integrated circuit package 100 and the upper integrated circuit package 200 .
- the stacked integrated circuit package further includes first to third solder bumps 400 , 500 and 600 formed between the interposer 300 and the lower integrated circuit package 100 or the upper integrated circuit package 200 and on the bottom surface of the lower integrated circuit package 100 .
- the lower integrated circuit package 100 includes a first substrate 110 , a first semiconductor chip 120 , and a first molding portion 130 .
- the first substrate 110 includes a wire terminal 111 formed on the upper surface (one surface) of the first substrate 110 , an external terminal 112 formed on the lower surface (the other surface) of the first substrate 110 to be connected to an external device via the solder ball 400 , and a via contact 113 formed through the first substrate 110 to connect the wire terminal 111 to the external terminal 112 .
- the first substrate 110 may further include a solder ball pad (not shown) on the upper surface.
- the first semiconductor chip 120 is flip-chip bonded, via the solder balls 121 , to the wire terminals 111 formed on the upper surface of the first substrate 110 .
- the first semiconductor chip 120 is flip-chip bonded to the first substrate 110 , facing downward.
- the first semiconductor chip 120 is electrically connected to the wire terminals 111 of the first substrate 110 via the solder balls 121 formed on the first semiconductor chip 120 .
- the first molding portion 130 which is a film assisted mold (FAM), is formed such that the upper surface of the first semiconductor chip 120 is exposed.
- FAM film assisted mold
- the upper integrated circuit package 200 includes a second substrate 210 , a second semiconductor 220 , and a second molding portion 230 .
- the second substrate 210 includes a wire terminal 211 formed on the upper surface (one surface) of the second substrate 210 , an external terminal 212 formed on the lower surface (the other surface) of the second substrate 210 to be connected to an external device via the interposer 300 , and a via contact 213 formed through the second substrate 210 to connect the wire terminal 211 to the external terminal 212 .
- the second semiconductor 220 is flip-chip bonded, via the solder balls 221 , to the wire terminal 211 formed on the upper surface of the second substrate 210 .
- the second semiconductor 220 is electrically connected, via the solder balls 221 formed on the second substrate 210 , to the wire terminals 211 of the second substrate 210 , facing downward.
- the second molding portion 230 is formed over the entire upper surfaces of the second semiconductor 220 and the second substrate 210 .
- the second molding portion 230 may be formed of a selected one of, for example, epoxy resin, silicone resin and equivalents thereof.
- the second molding portion 230 further includes an underfill between the second semiconductor 220 and the second substrate 210 .
- the interposer 300 is provided with an opening 350 to accommodate a semiconductor chip, as shown in FIG. 3 .
- the opening 350 is provided to accommodate the first semiconductor chip 120 and formed to have a larger size than the first semiconductor chip 120 to allow the encapsulant to fill the space between the first semiconductor chip 120 and the opening 350 .
- the opening 350 is preferably formed at the center of the interposer 300 .
- the interposer 300 may have the same layer structure as that of the first substrate 110 or the second substrate 210 . That is, the interposer 300 may include wire terminals 311 and 312 formed on the upper and lower surfaces of the interposer substrate 310 , and via contacts 313 connecting the wire terminals 311 and 312 to each other. In addition, the interposer 300 may be formed of a material having a coefficient of thermal expansion similar to that of the first substrate 110 or the second substrate 210 to reduce warpage occurring due to differences in coefficients of thermal expansion between the substrate, semiconductor chip and molding portion during a high temperature reflow process.
- the first solder bumps 400 are attached to the wire terminals 312 formed on the lower surface of the interposer 300 to be electrically connected to the substrate of the lower integrated circuit package, i.e., the first substrate.
- the third solder bumps 600 are attached to the external terminals 212 formed on the bottom surface of the substrate of the upper integrated circuit package, i.e., the second substrate 210 to allow the lower integrated circuit package 100 and the upper integrated circuit package 200 to be connected to each other via the third solder bumps 600 .
- the second solder bumps 500 are attached to the external terminals 112 formed on the bottom surface of the first substrate 110 to electrically connect a POP integrated circuit package formed by stacking the upper integrated circuit package on the lower integrated circuit package to an external device (not shown) or substrate.
- the size, shape and arrangement of the first to third solder bumps 400 , 500 and 600 are not specifically limited, but can be properly designed as necessary.
- the interposer in the illustrated embodiment is interposed between the lower integrated circuit package and the upper integrated circuit package. Thereby, rewiring of the upper integrated circuit package and increase in the number of I/O terminals are made possible.
- the upper surface of the semiconductor chip of the lower integrated circuit package is exposed, and molding is performed on the interposer and the entire substrate of the lower integrated circuit package.
- FIGS. 4A to 4F are cross-sectional views illustrating the processes of manufacturing a stacked integrated circuit package according to one embodiment of the present invention. A method for manufacturing a stacked integrated circuit package according to the illustrated embodiment is described below with reference to FIGS. 4A to 4F .
- a first substrate 110 provided with wire terminals 111 arranged on the upper surface, external terminals 112 arranged on the lower surface, and via contacts 113 connecting the wire terminal 111 to the external terminal 112 is first prepared.
- a semiconductor chip 120 is flip-chip bonded to the wire terminal 111 of the first substrate 110 using the solder balls 121 .
- the interposer 300 is attached to the first substrate 110 .
- the interposer 300 is disposed such that the first semiconductor chip 120 is accommodated in the opening of the interposer 300 .
- the interposer 300 is attached to the wire terminals 111 of the first substrate 110 using the first solder bumps 400 .
- the space between the first semiconductor chip 120 and the first substrate 110 , between the first semiconductor chip 120 and the interposer 300 , and between the first semiconductor substrate 110 and the interposer 300 is sealed with an encapsulant to form the first molding portion 130 .
- the first molding portion 130 is formed in the process of film assisted molding (FAM) such that the upper surface of the first semiconductor chip 120 is exposed.
- FAM film assisted molding
- second solder bumps 500 are formed on the external terminals 112 formed on the bottom surface of the first substrate 110 .
- the second integrated circuit package 200 is stacked on the first integrated circuit package 100 using the third solder bumps 600 .
- the second integrated circuit package 200 includes wire terminals 211 , a second substrate 210 provided with external terminals 212 and via contacts 213 , a second semiconductor 220 electrically connected to the wire terminals 211 of the second substrate 210 via solder balls 221 , and a second molding portion 230 formed on the entire upper surfaces of the second semiconductor 220 and the second substrate 210 .
- the wire terminals 311 of the interposer 300 are electrically connected to the external terminals 213 of the second substrate 210 via the third solder bumps 600 .
- attachment of the interposer is performed after the first semiconductor chip is attached to the first substrate.
- the interposer may first be stacked on the first substrate, and then the first semiconductor chip may be stacked such that the first semiconductor chip is accommodated in the opening of the interposer.
- a wire bonding structure may be formed in place of the flip chip bonding structure.
- a lead frame 300 a may be used as the interposer.
- other constituents except the lead frame 300 a are the same as those of the lower integrated circuit package of FIG. 2 , and thus a detailed description thereof will be omitted.
- the molding process is performed to form a molding portion on the semiconductor chip of the lower integrated circuit package after the interposer is interposed to position the semiconductor chip in the opening of the interposer semiconductor chip. Then, the upper integrated circuit package is mounted on the lower integrated circuit package, molding of which has been completed.
- the laser machining process and underfill process which take a large amount of time, are eliminated, and therefore process time can be reduced and manufacturing costs, in turn, can be reduced.
- the semiconductor chip of the lower integrated circuit package is exposed, and therefore heat dissipation can be improved and high temperature warpage can be reduced.
- an interposer is first interposed to allow a semiconductor chip of a lower integrated circuit package to be positioned in the opening of the interposer, and then an upper integrated circuit package is attached to the interposer.
- the molding process is performed to form a molding portion on the semiconductor chip of the lower integrated circuit package after the interposer is interposed to position the semiconductor chip in the opening of the interposer semiconductor chip. Then, the upper integrated circuit package is mounted on the lower integrated circuit package, molding of which has been completed.
- the semiconductor chip of the lower integrated circuit package is exposed, and therefore heat dissipation can be improved and high temperature warpage can be reduced.
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Abstract
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