KR20150045095A - Interposer, method for manufacturing the same and integrated circuit package with the interposer - Google Patents

Interposer, method for manufacturing the same and integrated circuit package with the interposer Download PDF

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Publication number
KR20150045095A
KR20150045095A KR20130124329A KR20130124329A KR20150045095A KR 20150045095 A KR20150045095 A KR 20150045095A KR 20130124329 A KR20130124329 A KR 20130124329A KR 20130124329 A KR20130124329 A KR 20130124329A KR 20150045095 A KR20150045095 A KR 20150045095A
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South Korea
Prior art keywords
interposer
substrate
integrated circuit
circuit package
semiconductor chip
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KR20130124329A
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Korean (ko)
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박민서
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에스티에스반도체통신 주식회사
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Priority to KR20130124329A priority Critical patent/KR20150045095A/en
Publication of KR20150045095A publication Critical patent/KR20150045095A/en

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Abstract

The present invention relates to a method for manufacturing an interposer, a stacked package using the same, and a manufacturing method thereof. The method for manufacturing an interposer according to the present invention includes the steps of: cutting an interposer substrate made of a single layer composed of insulating mateiral with a preset size; forming a via hole and an opening part (H) to receive a semiconductor chip on the interposer substrate; and forming a connection part by filling the via hole with conductive paste and sintering the conductive paste.

Description

인터포저 제조방법 및 이를 이용한 적층형 패키지와 그 제조방법{INTERPOSER, METHOD FOR MANUFACTURING THE SAME AND INTEGRATED CIRCUIT PACKAGE WITH THE INTERPOSER} BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an interposer,

본 발명은 인터포저 제조방법 및 이를 이용한 적층형 패키지와 그 제조방법에 관한 것이다.
The present invention relates to a method of manufacturing an interposer, a stacked package using the same, and a manufacturing method thereof.

통상, 반도체 산업은 저렴한 가격에 더욱 경량화, 소형화, 다기능화 및 고성능화 추세에 있다. 이러한 추세에 부응하기 위하여 요구되는 중요한 기술 중의 하나가 바로 집적회로 패키징 기술이다.In general, the semiconductor industry is becoming more lightweight, compact, versatile, and high performance at a low price. One of the important technologies required to meet this trend is integrated circuit packaging technology.

집적회로 패키징은 각종 전자 회로 및 배선이 적층되어 형성된 단일 소자 및 집적회로 등의 반도체 칩을 먼지, 습기, 전기적, 기계적 부하 등의 각종 외부 환경으로부터 보호하고 반도체 칩의 전기적 성능을 최적화, 극대화하기 위해 리드 프레임이나 인쇄회로기판(Printed Circuit Board) 등을 이용해 메인보드로의 신호 입/출력 단자를 형성하고 봉지재를 이용하여 몰딩한 것을 일컫는다. Integrated circuit packaging protects semiconductor chips such as single elements and integrated circuits formed by stacking various electronic circuits and wiring lines from various external environments such as dust, moisture, electrical and mechanical loads and optimizes and maximizes the electrical performance of semiconductor chips Output terminal to the main board by using a lead frame, a printed circuit board (Printed Circuit Board), or the like, and molded by using an encapsulating material.

한편, 최근 집적회로 패키지가 실장되는 제품들은 경박단소화되고, 많은 기능이 요구됨에 따라 집적회로 패키지 기술은 집적회로 패키지 내에 복수의 반도체 칩을 실장하는 SIP(System in Package), PoP(Package on Package) 등과 같은 방식을 적용하는 추세이다.In recent years, as the products on which the integrated circuit packages are mounted are thin and short, and many functions are required, the integrated circuit package technology has been widely used in various fields such as SIP (System in Package), PoP ) And the like.

이와 같은 집적회로 패키지의 용량 증가에 따라 입출력 단자의 수가 증가하는데, 집적회로 패키지의 전체 크기를 증가시키지 않으면서 입출력 단자의 수를 증가시키기 위하여 PoP의 하부 패키지 상단에 도전성 와이어(wire)로 범프(bump)를 형성한 다음 상부 패키지와 접속하는 방법이 제안되었다.In order to increase the number of input / output terminals without increasing the overall size of the integrated circuit package, the number of input / output terminals increases with the increase in the capacity of such integrated circuit packages. bump) is formed on the upper package and then connected to the upper package.

도 1a 내지 도 1d는 종래기술에 따른 인터포저를 구비하는 적층형 패키지의 제조과정을 나타낸 공정 단면도이다. FIGS. 1A to 1D are cross-sectional views illustrating a manufacturing process of a stacked package having an interposer according to a related art.

먼저, 도 1a에 도시된 바와 같이 플립칩(Flip-Chip) 구조의 하부 패키지(10)를 준비한 다음 도 1b에서와 같이 기판의 배선 단자와 접속되도록 와이어 범프(15)를 형성한다. 여기서, 와이어 범프는 와이어로 된 범프(15)로서 열압착(thermo compression) 방식에 의해 와이어를 기판의 배선 단자와 접속한 것이다. 열압착 방식은 기판 표면을 예열(250~500 ℃)시켜 5000~10000 lb/sq 압력으로 와이어(wire)를 붙이는 기술이다. First, a lower package 10 having a flip-chip structure is prepared as shown in FIG. 1A, and a wire bump 15 is formed so as to be connected to a wiring terminal of the substrate as shown in FIG. 1B. Here, the wire bump is a bump 15 made of wire, and the wire is connected to the wiring terminal of the board by a thermo compression method. The thermocompression method is a technique of preheating (250 ~ 500 ° C) the surface of the substrate and attaching wire with a pressure of 5000 ~ 10000 lb / sq.

다음으로, 도 1c에 도시된 바와 같이 와이어 범프(15), 반도체 칩(12) 및 기판(11)의 상면 전체를 봉지재로 몰딩하여 몰딩부(16)를 형성한다.Next, as shown in FIG. 1C, the entire upper surface of the wire bumps 15, the semiconductor chip 12, and the substrate 11 is molded with an encapsulating material to form a molding part 16.

다음으로, 도 1d에 도시된 바와 같이 하부 패키지(10) 상에 상부 패키지(20)를 적층한다. 이때, 솔더볼(25)과 와이어 범프(15)를 통해 하부 패키지(10)와 상부 패키지(20)가 전기 접속되도록 한다. Next, the upper package 20 is laminated on the lower package 10 as shown in Fig. 1D. At this time, the lower package 10 and the upper package 20 are electrically connected through the solder ball 25 and the wire bump 15.

그러나, 전술한 종래의 적층형 패키지의 경우 공정이 복잡할 뿐만 아니라 하부의 와이어 범프와 솔더볼을 정확히 정렬해야하는 문제점이 있다.
However, in the case of the above-described conventional stacked package, there is a problem in that the process is complicated and the wire bump and the solder ball are aligned accurately.

대한민국 공개특허공보 2011-0012674(2011.02.09.)Korean Patent Publication No. 2006-0012674 (2011.02.09.)

따라서, 본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 일반적인 목적은 종래 기술에서의 한계와 단점에 의해 발생되는 다양한 문제점을 실질적으로 보완할 수 있는 인터포저 제조방법 및 이를 이용한 적층형 패키지와 그 제조방법을 제공하는 것이다. SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is a general object of the present invention to provide an interposer fabrication method capable of substantially completing various problems caused by limitations and disadvantages of the prior art And a stacked package using the same and a method of manufacturing the same.

본 발명의 보다 구체적인 다른 목적은 제조공정을 단순화하고 크기 조절이 용이한 인터포저 제조방법 및 이를 이용한 적층형 패키지와 그 제조방법을 제공하는 것이다.
It is yet another specific object of the present invention to provide a method of manufacturing an interposer that simplifies a fabrication process and can be easily adjusted in size, a stacked package using the same, and a method of manufacturing the same.

이를 위해 본 발명의 일 실시예에 따른 인터포저 제조방법은 단층의 절연성 재질로 이루어진 인터포저 기판을 예정된 크기로 절단하는 과정과; 상기 인터포저 기판에 반도체 칩을 수용하기 위한 개구(H) 및 비아홀을 형성하는 과정; 및 상기 비아홀에 도전성 페이스트를 채워넣고 소결하여 접속부를 형성하는 과정을 포함하는 것을 특징으로 한다. For this purpose, a method of fabricating an interposer according to an embodiment of the present invention includes: cutting a single-layer interposer substrate made of an insulating material into a predetermined size; Forming an opening (H) and a via hole for accommodating the semiconductor chip on the interposer substrate; And filling the via hole with a conductive paste and sintering the conductive paste to form a connection portion.

본 발명의 일 실시예에 따른 인터포저 제조방법에서, 상기 소결 후 상기 접속부에 솔더를 형성하는 과정을 더 포함할 수 있다. In the method of manufacturing an interposer according to an embodiment of the present invention, the method may further include forming solder on the connection portion after the sintering.

본 발명의 일 실시예에 따른 인터포저 제조방법에서, 상기 개구 및 비아홀을 형성하는 과정은 레이저 또는 드릴 비트를 이용하여 이루어질 수 있다.In the method of fabricating an interposer according to an embodiment of the present invention, the process of forming the opening and the via hole may be performed using a laser or a drill bit.

본 발명의 일 실시예에 따른 인터포저 제조방법에서, 상기 비아홀에 도전성 페이스트를 채우는 과정은 스크린 프린팅 기법에 의해 이루어질 수 있다. In the method of fabricating an interposer according to an embodiment of the present invention, the process of filling the via hole with the conductive paste may be performed by a screen printing technique.

본 발명의 일 실시예에 따른 인터포저 제조방법에서, 상기 도전성 페이스트는 솔더 페이스트 또는 금속 페이스트일 수 있다.In the method of manufacturing an interposer according to an embodiment of the present invention, the conductive paste may be a solder paste or a metal paste.

본 발명의 일 실시예에 따른 인터포저 제조방법에서, 상기 절연성 재질은 폴리머 또는 세라믹일 수 있다. In the method of manufacturing an interposer according to an embodiment of the present invention, the insulating material may be a polymer or a ceramic.

또한, 본 발명의 일 실시예에 따른 인터포저를 이용한 적층형 패키지는 제 1 항 내지 제 6 항 중 어느 하나의 항에 따른 인터포저 제조방법에 의해 제조된 인터포저를 포함하는 것을 특징으로 한다. The stacked package using the interposer according to an embodiment of the present invention includes the interposer manufactured by the method of manufacturing the interposer according to any one of claims 1 to 6.

또한, 본 발명의 일 실시예에 따른 인터포저를 이용한 적층형 패키지 제조방법은 상면에 제1 배선 단자가 구비되고, 하면에 제1 외부 단자가 구비되며 상기 제1 배선 단자와 상기 제1 외부 단자를 연결하는 제1 비어콘택이 구비된 제1 기판과, 상기 제1 기판 위에 탑재된 제1 반도체 칩을 포함하는 제1 집적회로 패키지를 준비하는 과정과; 상기 제1 배선 단자 상에 제1 솔더볼을 형성하는 과정과; 상기 제1 집적회로 패키지 상에 개구 및 접속부를 구비하는 인터포저를 탑재하되, 상기 개구 내에 상기 제1 반도체 칩이 수용되고 상기 접속부가 상기 제1 배선 단자에 형성된 제1 솔더볼과 접속되도록 상기 인터포저를 정렬 배치하는 과정과; 제2 배선 단자, 제2 외부 단자 및 제2 비아콘택을 구비하는 제2 기판과, 상기 제2 기판 상에 탑재된 제2 반도체 칩을 포함하는 제2 집적회로 패키지의 상기 제2 기판 하면에 상기 제2 외부 단자와 접속되도록 제3 솔더볼을 형성하는 과정과; 상기 제1 집적회로 패키지 상부에 상기 제2 집적회로 패키지를 적층하되, 상기 제2 집적회로 패키지의 하면에 형성된 상기 제3 솔더볼이 상기 접속부와 접속되도록 상기 제2 집적회로 패키지를 정렬 배치하는 과정을 포함하는 것을 특징으로 한다. A method of fabricating a stacked package using an interposer according to an embodiment of the present invention includes a first wiring terminal on an upper surface thereof, a first external terminal on a lower surface thereof, a first wiring terminal and a first external terminal, Preparing a first integrated circuit package including a first substrate having a first via contact connected thereto and a first semiconductor chip mounted on the first substrate; Forming a first solder ball on the first wiring terminal; And an interposer having an opening and a connection portion on the first integrated circuit package so that the first semiconductor chip is received in the opening and the connection portion is connected to a first solder ball formed on the first wiring terminal, Aligning and arranging the plurality of light sources; A second substrate having a second wiring terminal, a second external terminal, and a second via contact, and a second semiconductor chip mounted on the second substrate; Forming a third solder ball to be connected to a second external terminal; The step of stacking the second integrated circuit package on the first integrated circuit package and the second integrated circuit package so that the third solder ball formed on the lower surface of the second integrated circuit package is connected to the connection portion, .

본 발명의 일 실시예에 따른 집적회로 패키지 제조방법에서, 상기 제1 반도체 칩 또는 상기 제2 반도체 칩 중 적어도 하나는 플립칩 본딩 구조로 상기 제1 기판 또는 상기 제2 기판에 탑재될 수 있다. In the method of manufacturing an integrated circuit package according to an embodiment of the present invention, at least one of the first semiconductor chip or the second semiconductor chip may be mounted on the first substrate or the second substrate with a flip chip bonding structure.

본 발명의 일 실시예에 따른 적층형 패키지 제조방법에서, 상기 제1 반도체 칩 또는 상기 제2 반도체 칩 중 적어도 하나는 와이어 본딩 구조로 상기 제1 기판 또는 상기 제2 기판에 탑재될 수 있다.
In the method of manufacturing a stacked package according to an embodiment of the present invention, at least one of the first semiconductor chip or the second semiconductor chip may be mounted on the first substrate or the second substrate with a wire bonding structure.

본 발명에 따른 인터포저 제조방법에 의하면, 인터포저의 몸체를 이루는 인터포저 기판이 단층의 절연성 재질로 이루어지므로 두께 조절이 용이할 뿐만 아니라 원하는 크기(size)로 절단 가공이 가능하다. According to the method of manufacturing the interposer according to the present invention, since the interposer substrate constituting the body of the interposer is made of a single-layer insulating material, it is easy to adjust the thickness and can be cut to a desired size.

또한, 인터포저 기판을 레이저 또는 드릴 비트를 이용하여 관통홀(개구, 비아홀)을 형성할 수 있고, 비아홀에 솔더 페이스트 또는 금속 페이스트를 스크린 프린팅 등의 기법으로 채워넣어 접속부를 형성함으로써 인터포저 제조공정을 단축할 수 있고 이에 따라 제조비용을 절감할 수 있다.In addition, the interposer substrate can be formed with through holes (openings, via holes) by using laser or drill bits, and solder paste or metal paste is filled into the via holes by a technique such as screen printing to form connection portions, It is possible to shorten the manufacturing cost and thereby reduce the manufacturing cost.

또한, 본 발명에 따른 인터포저를 이용한 적층형 패키지에 의하면, 하부 집적회로 패키지의 반도체 칩이 인터포저의 개구부 내에 위치하도록 인터포저를 개재한 다음 그 위에 상부 집적회로 패키지를 부착함으로써 인터포저를 통해 재배선이 가능하고, 입출력 단자 수를 증가시킬 수 있다.In addition, according to the stacked package using the interposer according to the present invention, an interposer is interposed so that the semiconductor chip of the lower integrated circuit package is positioned in the opening of the interposer, and then an upper integrated circuit package is attached thereon. The number of input / output terminals can be increased.

또한, 본 발명에 따른 인터포저를 이용한 적층형 패키지 제조방법에 의하면, 하부 집적회로 패키지의 반도체 칩을 몰딩하기 전에 인터포저의 개구부 내에 반도체 칩이 위치하도록 인터포저를 개재한 다음 하부 집적회로 패키지 위에 상부 집적회로 패키지를 탑재함으로써 장시간이 소요되는 레이저가공, 언더필 등의 공정을 진행하지 않으므로 공정과정을 단축할 수 있고 이에 따라 제조비용을 절감할 수 있다.
According to the method of manufacturing a stacked package using the interposer according to the present invention, the interposer is interposed so that the semiconductor chip is positioned in the opening of the interposer before molding the semiconductor chip of the lower integrated circuit package, By mounting the integrated circuit package, the processes such as laser processing and underfilling which require a long time are not performed, so that the process can be shortened and manufacturing cost can be reduced accordingly.

도 1a 내지 도 1d는 종래기술에 따른 적층형 패키지의 제조과정을 나타낸 공정 단면도이다.
도 2는 본 발명의 일 실시예에 따른 인터포저의 구성을 나타낸 도면이다.
도 3a 내지 도 3c는 본 발명의 일 실시예에 따른 인터포저 제조과정을 나타낸 공정 단면도이다.
도 4는 본 발명의 일 실시예에 따른 인터포저를 구비하는 적층형 패키지의 구조를 나타낸 단면도이다.
도 5a 내지 도 5f는 본 발명의 일 실시예에 따른 인터포저를 구비하는 적층형 패키지 제조과정을 나타낸 단면도이다. 1A to 1D are process cross-sectional views illustrating a manufacturing process of a stacked package according to the related art.
2 is a view illustrating the configuration of an interposer according to an embodiment of the present invention.
3A to 3C are cross-sectional views illustrating a process of manufacturing an interposer according to an embodiment of the present invention.
4 is a cross-sectional view illustrating a structure of a stacked package including an interposer according to an embodiment of the present invention.
5A to 5F are cross-sectional views illustrating a process for fabricating a stacked package including an interposer according to an embodiment of the present invention.

이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명하면 다음과 같다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명을 설명함에 있어서, 관련된 공지기능 혹은 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명은 생략한다. 또한, 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자의 의도 또는 판례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the terms described below are defined in consideration of the functions of the present invention, and these may vary depending on the intention or precedent of the user. Therefore, the definition should be based on the contents throughout this specification.

도 2는 본 발명의 일 실시예에 따른 인터포저의 구성을 나타낸 도면이다. 2 is a view illustrating the configuration of an interposer according to an embodiment of the present invention.

도 2를 참조하면, 본 실시예에 따른 인터포저(100)는 반도체 칩을 수요하기 위한 개구(H)를 구비하는 인터포저 기판(110)과, 상기 인터포저 기판(110)을 관통하며 상기 인터포저(100) 상면 및 하면을 전기적으로 연결하기 위한 접속부(120)를 포함한다. Referring to FIG. 2, the interposer 100 according to the present embodiment includes an interposer substrate 110 having an opening H for demanding a semiconductor chip, And a connection portion 120 for electrically connecting the upper surface and the lower surface of the sensor 100.

상기 인터포저 기판(110)은 하부 패키지 또는 상부 패키지에 탑재된 반도체 칩이나 부품을 수용하기 위한 개구(H)를 구비하고 있으며, 단층의 절연성 기판으로서 반도체 제조에 주로 사용되는 절연체 예를 들면, 폴리머, 세라믹 등으로 이루어질 수 있다. 상기 개구(H)는 수용하고자 하는 반도체 칩 또는 부품의 크기보다 큰 사이즈로 형성되며, 인터포저 기판(110)의 중심부에 형성되는 것이 바람직하다. The interposer substrate 110 has an opening H for accommodating a semiconductor chip or a component mounted on a lower package or an upper package. An insulating substrate such as a polymer , Ceramics, and the like. It is preferable that the opening H is formed in a size larger than the size of a semiconductor chip or a part to be received, and is formed at the center of the interposer substrate 110.

상기 접속부(120)는 인터포저를 사이에 두고 상부 및 하부에 위치하는 집적회로 패키지를 전기적으로 상호 접속하기 위한 것으로, 인터포저 기판(110)의 상면부터 하면까지 관통하도록 형성된 비아홀에 솔더 페이스트(paste) 또는 금속 페이스트를 스크린 프린팅 등의 기법으로 채워넣어 구현할 수 있다. The connection part 120 is for electrically interconnecting the upper and lower integrated circuit packages with the interposer interposed therebetween. The interposer substrate 110 has solder paste (paste) formed in a via hole formed to penetrate from the upper surface to the lower surface of the interposer substrate 110, ) Or by filling a metal paste with a technique such as screen printing.

전술한 구성을 갖는 본 발명의 일 실시예에 따른 인터포저 제조방법을 설명하면 다음과 같다.A method of manufacturing an interposer according to an embodiment of the present invention will now be described.

도 3a 내지 도 3c는 본 발명의 일 실시예에 따른 인터포저 제조과정을 나타낸 공정 단면도이다. 3A to 3C are cross-sectional views illustrating a process of manufacturing an interposer according to an embodiment of the present invention.

먼저, 도 3a에 도시된 바와 같이 인터포저 기판(110)을 준비한다. 상기 인터포저 기판(110)은 단층의 절연성 기판으로서 예를 들면, 폴리머, 세라믹 등이 될 수 있다. 상기 인터포저 기판(110)은 예를 들면, 직사각형 또는 정사각형 형상으로 적층 패키지의 목적에 맞도록 설계된 가로, 세로, 두께를 갖도록 개별 절단 가공이 가능하며, 단층의 절연성 물질로 이루어지므로 필요에 따라 두께를 웨이퍼 레벨 패키지에 적합하도록 얇게 형성할 수 있다. First, an interposer substrate 110 is prepared as shown in FIG. 3A. The interposer substrate 110 may be a single-layer insulating substrate, for example, a polymer, a ceramic, or the like. For example, the interposer substrate 110 may have a rectangular shape or a square shape, and may be individually cut to have a width, a length, and a thickness designed to meet the purpose of the stacked package. Since the interposer substrate 110 is formed of a single- May be formed thin to fit the wafer level package.

다음으로, 도 3b에 도시된 바와 같이 인터포저 기판(110)에 반도체 칩을 수용하기 위한 개구(H) 및 비아홀(120H)을 형성한다. 상기 개구(H) 및 비아홀(120H)은 인터포저 기판(110)의 상면에서 저면까지 관통하도록 형성되며, 레이저 또는 드릴 비트를 이용하여 형성할 수 있다.Next, as shown in FIG. 3B, an opening H for accommodating the semiconductor chip and a via hole 120H are formed in the interposer substrate 110. Next, as shown in FIG. The opening H and the via hole 120H are formed to penetrate from the upper surface to the lower surface of the interposer substrate 110 and may be formed using a laser or a drill bit.

다음으로, 도 3c에 도시된 바와 같이 비아홀(120H)에 솔더 페이스트 또는 금속 페이스트를 스크린 프린팅 기법으로 채워넣고 소결하여 접속부(120)를 형성한다. 소결 후, 솔더 등을 추가하여 접합성을 향상시킬 수 있다. Next, as shown in FIG. 3C, a solder paste or a metal paste is filled in the via hole 120H by a screen printing technique, and sintered to form a connection part 120. Next, as shown in FIG. After sintering, solder or the like may be added to improve the bonding property.

전술한 바와 같이 본 실시예에 따른 인터포저 제조방법에 의하면, 인터포저의 몸체를 이루는 인터포저 기판이 단층의 절연성 재질로 이루어지므로 두께 조절이 용이할 뿐만 아니라 원하는 크기(size)로 절단 가공이 가능하다. As described above, according to the method of manufacturing the interposer according to the present embodiment, since the interposer substrate constituting the body of the interposer is made of a single-layer insulating material, it is easy to adjust the thickness and can be cut to a desired size Do.

또한, 인터포저 기판을 레이저 또는 드릴 비트를 이용하여 관통홀(개구, 비아홀)을 형성할 수 있고, 비아홀에 솔더 페이스트 또는 금속 페이스트를 스크린 프린팅 등의 기법으로 채워넣어 접속부를 형성함으로써 인터포저 제조공정을 단축할 수 있고 이에 따라 제조비용을 절감할 수 있다.In addition, the interposer substrate can be formed with through holes (openings, via holes) by using laser or drill bits, and solder paste or metal paste is filled into the via holes by a technique such as screen printing to form connection portions, It is possible to shorten the manufacturing cost and thereby reduce the manufacturing cost.

도 4는 본 발명의 일 실시예에 따른 인터포저를 구비하는 적층형 패키지의 구조를 나타낸 단면도이다. 4 is a cross-sectional view illustrating a structure of a stacked package including an interposer according to an embodiment of the present invention.

도 4를 참조하면, 본 실시예에 따른 적층형 패키지는 하부(제1) 집적회로 패키지(200)와, 상기 하부 집적회로 패키지(200) 상에 적층된 상부(제2) 집적회로 패키지(300) 및 하부 집적회로 패키지(200)와 상부 집적회로 패키지(300) 사이에 개재된 인터포저(100)를 포함한다. 또한, 인터포저(100)와 하부 집적회로 패키지(200) 또는 상부 집적회로 패키지(300)의 사이 및 하부 집적회로 패키지 저면에 형성된 제1 내지 제3 솔더범프(250, 270, 350)를 포함한다. 4, the stacked package according to the present embodiment includes a lower (first) integrated circuit package 200, an upper (second) integrated circuit package 300 stacked on the lower integrated circuit package 200, And an interposer 100 interposed between the lower integrated circuit package 200 and the upper integrated circuit package 300. The first to third solder bumps 250, 270, and 350 formed on the bottom surface of the lower integrated circuit package and between the interposer 100 and the lower integrated circuit package 200 or the upper integrated circuit package 300 .

상기 하부 집적회로 패키지(200)는 제1 기판(210)과, 제1 반도체 칩(220), 제1 솔더볼(250) 및 제2 솔더볼(270)을 포함한다. The lower integrated circuit package 200 includes a first substrate 210, a first semiconductor chip 220, a first solder ball 250, and a second solder ball 270.

상기 제1 기판(210)은 상면(일면)에 형성되는 배선 단자(211)와, 하면(타면)에 형성되며 솔더볼(270)을 통하여 외부와 접속하기 위한 외부 단자(212) 및 배선 단자(211)와 외부 단자(212)를 연결하기 위해 제1 기판(210)을 관통하도록 형성된 비아콘택(213)을 포함한다. The first substrate 210 includes a wiring terminal 211 formed on an upper surface thereof and an external terminal 212 and a wiring terminal 211 connected to the outside through a solder ball 270, And a via contact 213 formed to penetrate the first substrate 210 to connect the external terminal 212 with the external terminal 212.

상기 제1 반도체 칩(220)은 제1 기판(210)의 상면에 형성된 배선 단자(211)에 플립칩 본딩되어 있다. 여기서, 제1 반도체 칩(220)은 페이스-다운(face-down) 형태로 제1 기판(210) 상에 플립칩 본딩되어 제1 반도체 칩(220) 상에 형성된 다수의 솔더범프(221)를 통하여 제1 기판(210)의 배선 단자(211)와 전기적으로 연결된다. The first semiconductor chip 220 is flip-chip bonded to the wiring terminal 211 formed on the upper surface of the first substrate 210. The first semiconductor chip 220 is flip-chip bonded on the first substrate 210 in face-down fashion to form a plurality of solder bumps 221 formed on the first semiconductor chip 220 And is electrically connected to the wiring terminal 211 of the first substrate 210.

상기 상부 집적회로 패키지(300)는 제2 기판(310)과, 제2 반도체 칩(320)과, 몰딩부(330)를 포함한다. The upper integrated circuit package 300 includes a second substrate 310, a second semiconductor chip 320, and a molding part 330.

상기 제2 기판(310)은 상면(일면)에 형성되는 배선 단자(311)와, 하면(타면)에 형성되며 인터포저(100)를 통하여 외부와 접속하기 위한 외부 단자(312) 및 배선 단자(311)와 외부 단자(312)를 연결하기 위해 제2 기판(310)을 관통하도록 형성된 비아콘택(313)을 포함한다. The second substrate 310 includes a wiring terminal 311 formed on an upper surface thereof and an external terminal 312 formed on a lower surface of the second substrate 310 for connection to the outside through the interposer 100, And a via contact 313 formed to penetrate the second substrate 310 to connect the external terminal 312 and the external terminal 312.

상기 제2 반도체 칩(320)은 전도성 와이어(321)를 통해 제2 기판(310) 상면에 형성된 배선 단자(311)에 와이어 본딩 되어 있다. 여기서, 제2 반도체 칩(320)은 페이스-업(face-up) 형태로 와이어 본딩을 통해 제2 기판(310)의 배선 단자(311)와 전기적으로 연결된다. The second semiconductor chip 320 is wire-bonded to the wiring terminal 311 formed on the upper surface of the second substrate 310 through the conductive wire 321. Here, the second semiconductor chip 320 is electrically connected to the wiring terminal 311 of the second substrate 310 through wire bonding in face-up form.

상기 몰딩부(330)는 제2 반도체 칩(320)과 제2 기판(310)의 상면 전체에 형성되며, 예를 들면, 에폭시 수지, 실리콘 수지 또는 그 등가물 중 선택된 어느 하나로 이루어질 수 있다. The molding part 330 is formed on the entire upper surface of the second semiconductor chip 320 and the second substrate 310 and may be made of any one selected from epoxy resin, silicone resin and the like, for example.

상기 인터포저(100)는 하부 집적회로 패키지(200)와 상부 집적회로 패키지(300) 사이에 개재되며, 제1 반도체 칩(220)을 수용하기 위한 개구를 구비하고 있다. 상기 인터포저(100)는 단일 절연층으로 이루어진 인터포저 기판(110)을 구비하며, 인터포저 기판(110)을 관통하도록 형성된 접속부(120)를 통해 하부 패키지(200)와 상부 패키지(300)가 전기접속된다. 또한, 인터포저 기판(110)은 제1 기판(210) 또는 제2 기판(310)과 유사한 열팽창 계수를 갖는 물질로 이루어질 수 있으며, 이는 고온 리플로우 공정시 기판과 반도체 칩, 몰딩부 간의 열팽창계수 차이로 인한 워패이지(warpage)를 감소시키기 위한 것이다.The interposer 100 is interposed between the lower integrated circuit package 200 and the upper integrated circuit package 300 and has an opening for receiving the first semiconductor chip 220. The interposer 100 includes an interposer substrate 110 formed of a single insulating layer and a lower package 200 and an upper package 300 are connected to each other through a connection part 120 formed to penetrate the interposer substrate 110. [ And is electrically connected. The interposer substrate 110 may be made of a material having a thermal expansion coefficient similar to that of the first substrate 210 or the second substrate 310. This is because the thermal expansion coefficient between the substrate and the semiconductor chip, To reduce warpage due to differences.

상기 제1 솔더볼(250)은 제1 기판(210)의 상면에 형성된 배선 단자(211)에 부착된다. 상기 제1 솔더볼(250)은 하부 집적회로 패키지의 기판 즉, 제1 기판(210)과 인터포저(100) 사이의 전기접속을 위한 것으로, 인터포저(100)의 하면에서 접속부(120)와 접속된다. The first solder ball 250 is attached to the wiring terminal 211 formed on the upper surface of the first substrate 210. The first solder ball 250 is used for electrical connection between the substrate of the lower integrated circuit package and the first substrate 210 and the interposer 100. The first solder ball 250 is connected to the connection part 120 at the lower surface of the interposer 100, do.

상기 제2 솔더볼(270)은 제1 기판(210)의 저면에 형성된 외부 단자(212)에 부착되며, 하부 집적회로 패키지 위에 상부 집적회로 패키지가 적층된 PoP 집적회로 패키지를 외부 소자(미도시) 또는 기판과 전기적으로 연결하기 위한 것이다.The second solder ball 270 is attached to an external terminal 212 formed on the bottom surface of the first substrate 210 and the PoP integrated circuit package having the upper integrated circuit package stacked on the lower integrated circuit package is connected to an external device Or for electrically connecting with the substrate.

상기 제3 솔더볼(350)은 상부 집적회로 패키지의 기판, 즉 제2 기판(310)의 저면에 형성된 외부 단자(312)에 부착되며, 하부 집적회로 패키지(200)와 상부 집적회로 패키지(300)가 제3 솔더볼(350)를 통해 적층 될 수 있도록 한다.The third solder ball 350 is attached to an external terminal 312 formed on the substrate of the upper integrated circuit package, that is, the lower surface of the second substrate 310, and the lower integrated circuit package 200 and the upper integrated circuit package 300, So that the third solder ball 350 can be stacked.

제1 내지 제3 솔더볼(250, 270, 350)의 크기, 형태, 배치 등은 특별히 제한되지 않고 필요에 따라 적절히 설계할 수 있다. The size, shape, arrangement, etc. of the first to third solder balls 250, 270 and 350 are not particularly limited and can be appropriately designed according to need.

전술한 바와 같이 본 실시예에서는 하부 집적회로 패키지와 상부 집적회로 패키지 사이에 단일 절연층으로 된 인터포저 기판을 구비하는 인터포저를 개재함으로써 상부 집적회로 패키지의 재배선이 가능하고 입출력 단자 수를 증가시킬 수 있다.As described above, in this embodiment, the upper integrated circuit package can be rewired and the number of input / output terminals can be increased by interposing an interposer having an interposer substrate formed as a single insulating layer between the lower integrated circuit package and the upper integrated circuit package .

도 5a 내지 도 5f는 본 발명의 일 실시예에 따른 인터포저를 구비하는 적층형 패키지 제조과정을 나타낸 단면도로서, 이들 도면을 참조하여 본 발명의 일 실시예에 따른 인터포저를 구비하는 적층형 패키지 제조방법을 설명하면 다음과 같다. 5A to 5F are cross-sectional views illustrating a process for fabricating a stacked package including an interposer according to an embodiment of the present invention. Referring to these drawings, a method for fabricating a stacked package having an interposer according to an embodiment of the present invention As follows.

먼저, 도 5a에 도시된 바와 같이, 상면에 배선 단자(211)가 구비되고, 하면에 외부 단자(212)가 구비되며 배선 단자(211)와 외부 단자(212)를 연결하는 비어콘택(213)이 구비된 제1 기판(210)을 준비한다.First, as shown in FIG. 5A, a via terminal 213 is provided on an upper surface, a via contact 213 having an external terminal 212 on a lower surface and connecting the wiring terminal 211 and the external terminal 212, The first substrate 210 is prepared.

다음으로, 도 5b에 도시된 바와 같이, 제1 기판(210)의 배선 단자(211) 상에 솔더범프(221)를 이용하여 반도체 칩(220)을 플립칩 본딩한 다음 언더필 공정을 진행하여 반도체 칩(220)과 제1 기판(210) 사이를 밀봉한다. 5B, the semiconductor chip 220 is flip-chip bonded on the wiring terminals 211 of the first substrate 210 by using the solder bumps 221, and then the underfill process is performed, Thereby sealing between the chip 220 and the first substrate 210.

다음으로, 도 5c에 도시된 바와 같이, 제1 기판(210)의 배선 단자(211) 상에 제1 솔더볼(250)을 형성한다. 상기 제1 솔더볼(250)은 제1 기판(210)의 상면에 형성된 배선 단자(211)에 인터포저(100)의 접속부를 부착하기 위한 것이다.Next, as shown in FIG. 5C, a first solder ball 250 is formed on the wiring terminal 211 of the first substrate 210. The first solder ball 250 is for attaching the connection portion of the interposer 100 to the wiring terminal 211 formed on the upper surface of the first substrate 210.

다음으로, 도 5d에 도시된 바와 같이 하부 집적회로 패키지(200) 상에 인터포저(100)를 탑재한다. 여기서, 인터포저(100)의 개구 내에 제1 반도체 칩(220)을 수용하면서 접속부(120)가 제1 기판(210)의 배선 단자(211)에 형성된 제1 솔더볼(250)과 접속되도록 인터포저(100)를 정렬 배치한다. Next, the interposer 100 is mounted on the lower integrated circuit package 200 as shown in Fig. 5D. The connection part 120 is connected to the first solder ball 250 formed on the wiring terminal 211 of the first substrate 210 while accommodating the first semiconductor chip 220 in the opening of the interposer 100, (100).

다음으로, 도 5e에 도시된 바와 같이 상부 집적회로 패키지(300)를 준비한 다음 상부 집적회로 패키지(300) 하면에 제3 솔더볼(350)을 형성한다. 상기 상부 집적회로 패키지(300)는 배선 단자(311), 외부 단자(312) 및 비아콘택(313)을 구비하는 제2 기판(310)과, 제2 기판(310) 상에 와이어 본딩에 의해 전기 접속된 제2 반도체 칩(320) 및 몰딩부(330)를 포함하며, 제3 솔더볼(350)은 제2 기판(310)의 하면에서 외부 단자(312)와 접속되도록 부착된다. Next, an upper integrated circuit package 300 is prepared as shown in FIG. 5E, and then a third solder ball 350 is formed on a lower surface of the upper integrated circuit package 300. The upper integrated circuit package 300 includes a second substrate 310 having a wiring terminal 311, an external terminal 312 and a via contact 313 and a second substrate 310 electrically connected to the second substrate 310 by wire bonding And the third solder ball 350 is attached so as to be connected to the external terminal 312 at the lower surface of the second substrate 310. The second semiconductor chip 320 includes a second semiconductor chip 320 and a molding part 330 connected thereto.

다음으로, 도 5f에 도시된 바와 같이 하부 집적회로 패키지(200) 상부에 상부 집적회로 패키지(300)를 적층한다. 여기서, 상부 집적회로 패키지(300)의 하면에 형성된 제3 솔더볼(350)이 인터포저(100)의 접속부(120)와 접속되도록 상부 집적회로 패키지(200)를 정렬 배치한다. Next, the upper integrated circuit package 300 is stacked on the lower integrated circuit package 200 as shown in FIG. 5F. The upper integrated circuit package 200 is aligned so that the third solder ball 350 formed on the lower surface of the upper integrated circuit package 300 is connected to the connection portion 120 of the interposer 100.

한편, 하부 집적회로 패키지 상에 상부 집적회로 패키지를 적층한 다음 봉지재로 몰딩하는 공정을 더 진행할 수 있다. On the other hand, a process of laminating the upper integrated circuit package on the lower integrated circuit package and then molding the encapsulation material may be further performed.

전술한 실시예에서는 제1 기판 위에 제1 반도체 칩을 부착한 후에 인터포저를 탑재하는 구성을 개시하였으나 인터포저를 제1 기판 위에 먼저 탑재한 후 탑재된 인터포저의 개구 내에 제1 반도체 칩이 수용되도록 제1 반도체 칩을 부착할 수 있다. 또한, 플립칩 본딩 구조로 접속된 제1 반도체 칩을 와이어 본딩 구조로 제1 반도체 기판과 접속되도록 할 수 있음은 물론이다. In the above-described embodiment, the first semiconductor chip is mounted on the first substrate and then the interposer is mounted. However, after the interposer is first mounted on the first substrate, the first semiconductor chip is accommodated in the opening of the interposer So that the first semiconductor chip can be attached. It goes without saying that the first semiconductor chip connected by the flip chip bonding structure can be connected to the first semiconductor substrate by the wire bonding structure.

전술한 바와 같이 본 실시예에 따르면 하부 집적회로 패키지의 반도체 칩을 몰딩하기 전에 인터포저의 개구부 내에 반도체 칩이 위치하도록 인터포저를 개재한 다음 하부 집적회로 패키지 위에 상부 집적회로 패키지를 탑재함으로써 장시간이 소요되는 레이저가공, 언더필 등의 공정을 진행하지 않으므로 공정과정을 단축할 수 있고 이에 따라 제조비용을 절감할 수 있다. As described above, according to the present embodiment, by interposing the interposer so that the semiconductor chip is positioned in the opening of the interposer before molding the semiconductor chip of the lower integrated circuit package, and then mounting the upper integrated circuit package on the lower integrated circuit package, It is possible to shorten the process time and thus reduce the manufacturing cost since the laser processing and the underfill process are not performed.

한편, 본 발명의 상세한 설명 및 첨부도면에서는 구체적인 실시예에 관해 설명하였으나, 본 발명은 개시된 실시예에 한정되지 않고 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다. 따라서, 본 발명의 범위는 설명된 실시예에 국한되어 정해져서는 안되며 후술하는 특허청구범위뿐만 아니라 이 특허청구범위와 균등한 것들을 포함하는 것으로 해석되어야 할 것이다.
While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. Accordingly, the scope of the present invention should be construed as being limited to the embodiments described, and it is intended that the scope of the present invention encompasses not only the following claims, but also equivalents thereto.

100 : 인터포저 110, 210, 310 : 기판
120 : 접속부 200, 300 : 집적회로 패키지
220, 320 : 반도체 칩 250, 270, 350 : 솔더볼100: interposer 110, 210, 310: substrate
120: connection part 200, 300: integrated circuit package
220, 320: semiconductor chips 250, 270, 350: solder balls

Claims (10)

단층의 절연성 재질로 이루어진 인터포저 기판을 예정된 크기로 절단하는 과정과;
상기 인터포저 기판에 반도체 칩을 수용하기 위한 개구(H) 및 비아홀을 형성하는 과정; 및
상기 비아홀에 도전성 페이스트를 채워넣고 소결하여 접속부를 형성하는 과정을 포함하는 것을 특징으로 하는 인터포저 제조방법.
Cutting an interposer substrate made of a single-layer insulating material into a predetermined size;
Forming an opening (H) and a via hole for accommodating the semiconductor chip on the interposer substrate; And
And filling the via hole with a conductive paste and sintering the conductive paste to form a connection portion.
제 1 항에 있어서, 상기 소결 후
상기 접속부에 솔더를 형성하는 과정을 더 포함하는 것을 특징으로 하는 인터포저 제조방법.
The method according to claim 1, wherein after the sintering
And forming a solder on the connection portion.
제 1 항에 있어서, 상기 개구 및 비아홀을 형성하는 과정은
레이저 또는 드릴 비트를 이용하여 이루어지는 것을 특징으로 하는 인터포저 제조방법.
The method as claimed in claim 1, wherein the process of forming the opening and the via-
Wherein the step of forming the interposer is performed using a laser or a drill bit.
제 1 항에 있어서, 상기 비아홀에 도전성 페이스트를 채우는 과정은
스크린 프린팅 기법에 의해 이루어지는 것을 특징으로 하는 인터포저 제조방법.
The method according to claim 1, wherein the step of filling the via hole with a conductive paste comprises:
Screen printing technique. ≪ RTI ID = 0.0 > 21. < / RTI >
제 4 항에 있어서, 상기 도전성 페이스트는
솔더 페이스트 또는 금속 페이스트인 것을 특징으로 하는 인터포저 제조방법.
5. The conductive paste according to claim 4, wherein the conductive paste
Solder paste or metal paste.
제 1 항에 있어서, 상기 절연성 재질은
폴리머 또는 세라믹인 것을 특징으로 하는 인터포저 제조방법.
The semiconductor device according to claim 1, wherein the insulating material
Polymer or ceramic. ≪ RTI ID = 0.0 > 11. < / RTI >
제 1 항 내지 제 6 항 중 어느 하나의 항에 따른 인터포저 제조방법에 의해 제조된 인터포저를 구비하는 것을 특징으로 하는 집적회로 패키지.
An integrated circuit package comprising an interposer manufactured by the method of manufacturing an interposer according to any one of claims 1 to 6.
상면에 제1 배선 단자가 구비되고, 하면에 제1 외부 단자가 구비되며 상기 제1 배선 단자와 상기 제1 외부 단자를 연결하는 제1 비어콘택이 구비된 제1 기판과, 상기 제1 기판 위에 탑재된 제1 반도체 칩을 포함하는 제1 집적회로 패키지를 준비하는 과정과;
상기 제1 배선 단자 상에 제1 솔더볼을 형성하는 과정과;
상기 제1 집적회로 패키지 상에 개구 및 접속부를 구비하는 인터포저를 탑재하되, 상기 개구 내에 상기 제1 반도체 칩이 수용되고 상기 접속부가 상기 제1 배선 단자에 형성된 제1 솔더볼과 접속되도록 상기 인터포저를 정렬 배치하는 과정과;
제2 배선 단자, 제2 외부 단자 및 제2 비아콘택을 구비하는 제2 기판과, 상기 제2 기판 상에 탑재된 제2 반도체 칩을 포함하는 제2 집적회로 패키지의 상기 제2 기판 하면에 상기 제2 외부 단자와 접속되도록 제3 솔더볼을 형성하는 과정과;
상기 제1 집적회로 패키지 상부에 상기 제2 집적회로 패키지를 적층하되, 상기 제2 집적회로 패키지의 하면에 형성된 상기 제3 솔더볼이 상기 접속부와 접속되도록 상기 제2 집적회로 패키지를 정렬 배치하는 과정을 포함하는 것을 특징으로 하는 집적회로 패키지 제조방법.
A first substrate having a first wiring terminal on an upper surface thereof and a first via terminal connected to the first wiring terminal and the first external terminal, Preparing a first integrated circuit package including a mounted first semiconductor chip;
Forming a first solder ball on the first wiring terminal;
And an interposer having an opening and a connection portion on the first integrated circuit package so that the first semiconductor chip is received in the opening and the connection portion is connected to a first solder ball formed on the first wiring terminal, Aligning and arranging the plurality of light sources;
A second substrate having a first wiring terminal, a second wiring terminal, a second external terminal, and a second via contact, and a second semiconductor chip mounted on the second substrate; Forming a third solder ball to be connected to a second external terminal;
The step of stacking the second integrated circuit package on the first integrated circuit package and the second integrated circuit package so that the third solder ball formed on the lower surface of the second integrated circuit package is connected to the connection portion, ≪ / RTI >
제 8 항에 있어서,
상기 제1 반도체 칩 또는 상기 제2 반도체 칩 중 적어도 하나는 플립칩 본딩 구조로 상기 제1 기판 또는 상기 제2 기판에 탑재되는 것을 특징으로 하는 적층형 패키지.
9. The method of claim 8,
Wherein at least one of the first semiconductor chip or the second semiconductor chip is mounted on the first substrate or the second substrate with a flip chip bonding structure.
제 8 항에 있어서,
상기 제1 반도체 칩 또는 상기 제2 반도체 칩 중 적어도 하나는 와이어 본딩 구조로 상기 제1 기판 또는 상기 제2 기판에 탑재되는 것을 특징으로 하는 적층형 패키지.9. The method of claim 8,
Wherein at least one of the first semiconductor chip or the second semiconductor chip is mounted on the first substrate or the second substrate with a wire bonding structure.
KR20130124329A 2013-10-18 2013-10-18 Interposer, method for manufacturing the same and integrated circuit package with the interposer KR20150045095A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107808889A (en) * 2017-11-29 2018-03-16 苏州晶方半导体科技股份有限公司 Laminated packaging structure and method for packing
KR20190043892A (en) * 2017-10-19 2019-04-29 삼성전기주식회사 Semiconductor package comprising organic interposer
WO2020204493A1 (en) * 2019-04-01 2020-10-08 주식회사 아모센스 Interposer and method for manufacturing same
KR20200116415A (en) * 2019-04-01 2020-10-12 주식회사 아모센스 Interposer with multiple structure and method thereof
KR20200116414A (en) * 2019-04-01 2020-10-12 주식회사 아모센스 Interposer and method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190043892A (en) * 2017-10-19 2019-04-29 삼성전기주식회사 Semiconductor package comprising organic interposer
US10600706B2 (en) 2017-10-19 2020-03-24 Samsung Electronics Co., Ltd. Semiconductor package including organic interposer
CN107808889A (en) * 2017-11-29 2018-03-16 苏州晶方半导体科技股份有限公司 Laminated packaging structure and method for packing
CN107808889B (en) * 2017-11-29 2023-10-20 苏州晶方半导体科技股份有限公司 Stacked package structure and packaging method
WO2020204493A1 (en) * 2019-04-01 2020-10-08 주식회사 아모센스 Interposer and method for manufacturing same
KR20200116415A (en) * 2019-04-01 2020-10-12 주식회사 아모센스 Interposer with multiple structure and method thereof
KR20200116414A (en) * 2019-04-01 2020-10-12 주식회사 아모센스 Interposer and method thereof

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