CN107808889A - Laminated packaging structure and method for packing - Google Patents
Laminated packaging structure and method for packing Download PDFInfo
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- CN107808889A CN107808889A CN201711226357.1A CN201711226357A CN107808889A CN 107808889 A CN107808889 A CN 107808889A CN 201711226357 A CN201711226357 A CN 201711226357A CN 107808889 A CN107808889 A CN 107808889A
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- 229910000679 solder Inorganic materials 0.000 claims description 27
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- 239000004065 semiconductor Substances 0.000 description 2
- SZUVGFMDDVSKSI-WIFOCOSTSA-N (1s,2s,3s,5r)-1-(carboxymethyl)-3,5-bis[(4-phenoxyphenyl)methyl-propylcarbamoyl]cyclopentane-1,2-dicarboxylic acid Chemical compound O=C([C@@H]1[C@@H]([C@](CC(O)=O)([C@H](C(=O)N(CCC)CC=2C=CC(OC=3C=CC=CC=3)=CC=2)C1)C(O)=O)C(O)=O)N(CCC)CC(C=C1)=CC=C1OC1=CC=CC=C1 SZUVGFMDDVSKSI-WIFOCOSTSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
This application discloses a kind of laminated packaging structure of image sensing chip, the laminated packaging structure includes image sensing chip packing-body, control chip packaging body and circuit board, by the same surface that image sensing chip packing-body and circuit board are juxtaposed on to control chip packaging body, the number of plies of laminated packaging structure can be reduced, and then reduces the gross thickness of laminated packaging structure.In the laminated packaging structure, image sensing chip packing-body includes first substrate and image sensing chip, first substrate includes first surface and second surface, control chip packaging body includes second substrate and control chip, second substrate includes first surface and second surface, in order to realize the transmission of signal, the second surface of first substrate can be electrically connected with the first area of the first surface of second substrate, circuit board electrically connects with the second area of the first surface of second substrate.Disclosed herein as well is a kind of method for packing of laminated packaging structure.
Description
Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a stacked package structure and a package method.
Background
With the continuous development of semiconductor manufacturing technology and three-dimensional packaging technology, electronic devices and electronic products have higher and higher requirements for multi-functionalization and miniaturization. Driven by this trend toward miniaturization, the package size of chips is required to be continuously reduced. According to the international semiconductor technology roadmap, the three-dimensional stack package technology (POP) can better realize the miniaturization of the package.
The three-dimensional laminated package has the following characteristics: the packaging volume is smaller, the packaging three-dimensional space is larger, the lead distance is shortened, so that the signal transmission is faster, the product development period is short, the market launching speed is high, and the like. The three-dimensional laminated packaging is mainly applied to handheld devices and data products such as mobile phones, portable computers and digital cameras.
An example of applying the three-dimensional stack package technology to the field of image sensor chip packaging has appeared. A conventional package structure of an image sensor chip is shown in fig. 1. The image sensor chip package 10 is connected to one surface of the control chip package 20, and the Flexible Printed Circuit (FPC)30 is connected to the other opposite surface of the control chip package 20 to form a stacked structure.
In the stacked package structure of the image sensor chip shown in fig. 1, the Flexible Printed Circuit (FPC)30 and the image sensor chip package 10 are respectively disposed on two surfaces of the control chip package 20 to form a vertical stacked structure of the three, and the thicknesses of the Flexible Printed Circuit (FPC)30, the control chip package 20 and the image sensor chip package 10 all affect the total thickness of the vertical stacked structure, so that the thickness of the stacked package structure of the image sensor chip is relatively thick, which is not favorable for the light and thin of the electronic product.
Disclosure of Invention
In view of the above, the present application provides a stacked package structure and a packaging method thereof, so as to reduce the overall thickness of the stacked package structure of the image sensor chip.
In order to solve the technical problem, the following technical scheme is adopted in the application:
a package on package structure comprising:
the image sensor comprises an image sensing chip packaging body, a control chip packaging body and a circuit board;
the image sensing chip package comprises a first substrate and at least one image sensing chip, wherein the first substrate comprises a first surface and a second surface which are opposite, and the image sensing chip is electrically connected to the first surface of the first substrate;
the control chip package comprises a second substrate and at least one control chip, wherein the second substrate comprises a first surface and a second surface which are opposite, the first surface of the second substrate comprises a first area and a second area,
the control chip is positioned on the second surface side of the second substrate and is electrically connected to the second surface of the second substrate;
the image sensing chip package and the circuit board are both located on the first surface side of the second substrate, the circuit board is located beside the image sensing chip package, the second surface of the first substrate is electrically connected with the first region of the first surface of the second substrate, and the circuit board is electrically connected with the second region of the first surface of the second substrate.
A stack packaging method comprising:
providing an image sensing chip package, a control chip package and a circuit board; the image sensing chip package comprises a first substrate and at least one image sensing chip, wherein the first substrate comprises a first surface and a second surface which are opposite, and the image sensing chip is electrically connected to the first surface of the first substrate; the control chip package comprises a second substrate and at least one control chip, wherein the second substrate comprises a first surface and a second surface which are opposite, and the first surface of the second substrate comprises a first area and a second area; the control chip is positioned on the second surface side of the second substrate and is electrically connected to the second surface of the second substrate;
the image sensing chip package and the circuit board are arranged in parallel on the first surface side of the second substrate, the first region is electrically connected to the second surface of the first substrate, and the second region is electrically connected to the circuit board.
Compared with the prior art, the method has the following beneficial effects:
based on the above technical solution, in the stacked package structure provided by the embodiment of the present application, the image sensing chip package and the circuit board are located on the same surface side of the control chip package, and the circuit board is located beside the image sensing chip package, so the circuit board does not affect the thickness of the whole stacked package structure, and the total thickness of the stacked package structure is the sum of the thicknesses of the image sensing chip package and the control chip package.
Drawings
In order that the present invention and prior art will be clearly understood, a brief description of the drawings, in which the present invention and prior art are described, will now be provided. It is obvious that these drawings are only some embodiments of the invention, and that a person skilled in the art will be able to obtain further drawings without the inventive step.
FIG. 1 is a cross-sectional view of a stacked package structure of an image sensor chip according to the prior art;
fig. 2A to 2E are a schematic cross-sectional view and a top view of a stacked package structure of an image sensor chip according to an embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional view illustrating a package-on-package structure of an image sensor chip according to another embodiment of the present disclosure;
fig. 4 is a schematic cross-sectional view illustrating a package on package structure of an image sensor chip according to another embodiment of the present application;
fig. 5 is a schematic cross-sectional view illustrating a package-on-package structure of an image sensor chip according to still another embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional view illustrating a package-on-package structure of an image sensor chip according to still another embodiment of the present disclosure;
fig. 7 is a schematic cross-sectional view illustrating a package-on-package structure of an image sensor chip according to still another embodiment of the present disclosure;
fig. 8 is a schematic cross-sectional view illustrating a package-on-package structure of an image sensor chip according to still another embodiment of the present disclosure;
fig. 9 is a schematic cross-sectional view illustrating a package-on-package structure of an image sensor chip according to still another embodiment of the present disclosure;
fig. 10 is a flowchart illustrating a packaging method of a stack package structure of an image sensor chip according to an embodiment of the present disclosure;
fig. 11A and 11B are schematic cross-sectional views illustrating a series of steps of a packaging method for a package on package structure of an image sensor chip according to an embodiment of the present disclosure.
Description of reference numerals:
10: an image sensing chip package;
11: a first substrate;
11a first surface of a first substrate;
11 b: a second surface of the first substrate;
111: a first pad;
112: a second pad;
113: an electrical connection structure connecting the first pad and the second pad;
114, a through hole;
12: an image sensing chip;
121: a light sensing area;
122: a third pad;
13: a second lead;
14: plastic packaging material;
15: a transparent protective layer;
16: sealing the cavity;
17: a support structure;
18: a lens module assembly;
181: a lens;
182: a lens holder;
183: bonding glue;
20: a control chip package;
21: a second substrate;
21 a: a first surface of a second substrate;
21 b: a second surface of the second substrate;
i: a first region of a first surface of a second substrate;
II: a second region of the first surface of the second substrate;
211: a fourth pad;
212: a fifth pad;
213: the electric connection structure is used for connecting the fourth welding pad and the fifth welding pad;
22: a control chip;
221: a sixth pad;
23: a first lead;
30: a circuit board;
40: a conductive adhesive;
41: welding flux;
42: and (7) solder balls.
Detailed Description
As described in the background section, in order to achieve the light and thin electronic products, it is necessary to reduce the thickness of the stacked package structure of the image sensor chip and to miniaturize the image sensor. In the conventional stacked package structure of the image sensor chip, the Flexible Printed Circuit (FPC)30 and the image sensor chip package 10 are respectively disposed on two surfaces of the control chip package 20 to form a three-layer vertical stack structure, and the thicknesses of the Flexible Printed Circuit (FPC)30, the control chip package 20 and the image sensor chip package 10 all affect the total thickness of the vertical stack structure, resulting in a thicker stacked package structure of the image sensor chip.
According to the embodiment of the application, the total thickness of the laminated packaging structure of the image sensing chip is reduced by reducing the number of layers of the laminated packaging structure, so that the miniaturization of the image sensor is realized, and the lightness and thinness of electronic products are further realized.
In order to reduce the total thickness of the stacked package structure of the image sensing chip, the circuit board is arranged beside the image sensing chip package body in the embodiment of the application, and the image sensing chip package body and the circuit board are positioned on the same surface side of the control chip package body, so that the circuit board does not influence the thickness of the whole stacked package structure, and the total thickness of the stacked package structure is the sum of the thicknesses of the image sensing chip package body and the control chip package body.
The following detailed description of specific embodiments of the present application is provided in conjunction with the accompanying drawings. It is to be understood that the present invention is not limited to the particular embodiments, and that structural, methodological or functional changes made by those skilled in the art based on the embodiments are intended to be included within the scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In describing the embodiments of the present application in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Please refer to fig. 2A to fig. 2E. Fig. 2A is a schematic cross-sectional structure view of a stacked package structure of an image sensor chip according to an embodiment of the present disclosure, and fig. 2B to 2E are top views of the stacked package structure of the image sensor chip according to the embodiment of the present disclosure. As shown in fig. 2A to 2E, the package-on-package structure of the image sensor chip includes:
an image sensor chip package 10, a control chip package 20 and a circuit board 30,
the image sensing chip package 10 includes a first substrate 11 and an image sensing chip 12, the first substrate 11 includes a first surface 11a and a second surface 11b opposite to each other, and the image sensing chip 12 is electrically connected to the first surface 11a of the first substrate; it should be noted that, in the embodiment of the present application, the package structure 10 of the image sensing chip includes at least one image sensing chip 12, that is, one or more image sensing chips 12 may be disposed on the substrate 11. In the present example, an example in which 3 image sensor chips 12 are provided on one image sensor chip package 10 is described. In the present example, the first substrate 11 is provided with a through hole 114, the image sensing chip 12 is located in the through hole 114, and the front surface of the image sensing chip 12 is flush with the first surface 11a of the first substrate 11.
In the package structure of the image sensor chip according to the embodiment of the present application, one image sensor chip 12 is disposed in one through hole 114, wherein the front surface of each image sensor chip 12 is flush with the first surface 11a of the substrate 11, so that the front surfaces of the image sensor chips 12 are all located on the same plane. The corresponding structure is shown in top view in fig. 2B and 2D above.
As another embodiment of the present application, a plurality of image sensing chips 12 may be disposed in one through hole 114, wherein the front surface of each image sensing chip 12 is flush with the first surface 11a of the substrate 11, so as to ensure that the front surfaces of the image sensing chips 12 are all located on the same plane. The top view of the corresponding package structure is shown in fig. 2E.
When the thickness of the image sensor chip 12 is smaller than the thickness of the substrate 11, a height difference exists between the back surface of the image sensor chip 12 and the second surface 11b of the substrate 11, and in order to fill up the height difference, a region not occupied by the image sensor chip 12 in the through hole 114 may be filled with a plastic sealing material.
The control chip package 20 comprises a second substrate 21 and at least one control chip 22, wherein the second substrate 21 comprises a first surface 21a and a second surface 21b which are opposite to each other, and the first surface 21a of the second substrate comprises a first area I and a second area II;
the control chip 22 is located on the second surface 21b side of the second substrate and is electrically connected to the second surface 21b of the second substrate;
the image sensor chip package 10 and the circuit board 30 are both located on the first surface 21a side of the second substrate 21, the circuit board 30 is located on the side of the image sensor chip package 10, the second surface 11b of the first substrate 11 is electrically connected to the first region i of the first surface 21a of the second substrate 21, and the circuit board 30 is electrically connected to the second region ii of the first surface 21a of the second substrate 21. Wherein the circuit board 30 may extend beyond the second area ii.
The first surface 11a and the second surface 11b of the first substrate are respectively provided with a first pad 111 and a second pad 112, and the first substrate 11 is internally provided with an electrical connection structure 113 for electrically connecting the first pad 111 and the second pad 112. The front surface of the image sensor chip 12 is provided with a photosensitive area 121 and a third bonding pad 122 outside the photosensitive area. The image sensing chip 12 is electrically connected to the first surface 11a of the first substrate, specifically, the third pad 122 on the image sensing chip is electrically connected to the first pad 111 through the second lead 13.
The second substrate 21 has a first surface 21a and a second surface 21b on which a fourth pad 211 and a fifth pad 212 are disposed, respectively, and an electrical connection structure 213 is disposed inside the second substrate 21. The control chip 22 may be flip-chip mounted on the second surface 21b of the second substrate 21. One or more control chips 22 may be provided in the control chip package 20. When the control chip 22 is plural, the plural control chips may form a vertical stack structure.
When a plurality of control chips are formed in a vertically stacked structure, the surfaces of the different control chips 22 do not completely overlap in order to facilitate electrical connection of the control chips 22 with the second surface 21b of the second substrate 21. That is, the surfaces of the respective control chips 22 are partially offset from each other to reserve electrical connections for leads.
As a specific example of the present application, a sixth pad 221 may be disposed on a region of the control chip 22 not covered by the control chip adjacent thereto, and the sixth pad 221 on the control chip 22 is electrically connected to a fifth pad on the second surface 21b of the second substrate 21 through the first lead 23.
The control chip 22 is used to control the image sensing chip 12, and the present application does not limit the specific functions of the control chip 22, and the control chip 22 and the image sensing chip 12 can satisfy the "control" mentioned in the present application as long as the control chip establishes electrical signal transmission. Wherein, one control chip 22 corresponds to at least one image sensing chip 12. That is, one control chip 22 controls at least one image sensing chip 12. Moreover, in order to simplify the circuit design of the control chip 22, as a specific example of the present application, there is a one-to-one correspondence relationship between the control chip 22 and the image sensing chips 12, that is, one control chip 22 controls only one image sensing chip 12.
As an example, the control chip 22 may be an Application Specific Integrated Circuit (ASIC) chip.
In the embodiment of the present application, the second surface 11b of the first substrate 11 and the first area i of the first surface 21a of the second substrate 21 are adhered together by the conductive adhesive 40, and the back surface of the circuit board 30 and the second area ii of the first surface 21a of the second substrate 21 are adhered together by the conductive adhesive 40. As a specific example of the present application, the conductive paste 40 may be an anisotropic conductive paste. Note that the conductive paste 40 may be coated on at least one of the two surfaces to be electrically connected. Specifically, in order to electrically connect the second surface 11b of the first substrate 11 and the first region i of the first surface 21a of the second substrate 21, the conductive paste 40 may be coated on the second surface 11b of the first substrate 11, the conductive paste 40 may be coated on the first region i of the first surface 21a of the second substrate 21, or the conductive paste 40 may be coated on both the second surface 11b of the first substrate 11 and the first region i of the first surface 21a of the second substrate 21. In order to electrically connect the circuit board 30 and the second area ii of the first surface 21a of the second substrate 21, the back surface of the circuit board 30 may be coated with the conductive adhesive 40, the second area ii of the first surface 21a of the second substrate 21 may be coated with the conductive adhesive 40, and both the back surface of the circuit board 30 and the second area ii of the first surface 21a of the second substrate 21 may be coated with the conductive adhesive 40.
In this way, the circuit board 30, the control chip 22 and the image sensing chip 12 realize signal transmission through the conductive adhesive 40, the fourth pad 211, the fifth pad 212 and the sixth pad 221 electrically connected to each other, and the first pad 111, the second pad 112 and the third pad 122 electrically connected to each other.
The circuit board 30 may be a flexible circuit board FPC, and the shape of the circuit board 23 may match the shape of the second area ii. As a specific example of the present application, fig. 2B to 2D show top views of a package-on-package structure of an image sensor chip. As can be seen from fig. 2B to fig. 2D, the shape of the circuit board may be a long strip shape or a trapezoid-like shape, and the shape of the circuit board may be set according to requirements, which is not limited in the embodiment of the present invention.
As another specific example of the present application, in order to realize the transmission of the signal, the electrical connection may be realized by metal bonding, in addition to the conductive adhesive 40. As shown in fig. 3, the second surface 11b of the first substrate 11 and the first region i of the first surface 21a of the second substrate 21 are electrically connected by metal bonding, and the back surface of the circuit board and the second region ii of the first surface of the second substrate are electrically connected by metal bonding. Specifically, the metal solder 41 may be coated on the first surface 21a of the second substrate 21, and the second surface 11b of the first substrate 11 and the first area i of the first surface 21a of the second substrate 21 may be soldered together by the metal solder 41. As another example, the metal solder 41 may be coated on the second surface 11b of the first substrate 21 and the back surface of the circuit board 30 to realize the connection of the second surface 11b of the first substrate 11 and the first region i of the first surface 21a of the second substrate 21 and the connection of the circuit board 30 and the second region II of the first surface 21a of the second substrate 21. As still another example, it is also possible to coat the metallic solder on both surfaces to be connected, that is, on both the second surface 11b of the first substrate 21 and the back surface of the circuit board 30 and the first area i and the second area II of the second surface 11b and the first surface 21a of the second substrate 21.
As another specific example of the present application, in order to realize the signal transmission, in addition to the conductive paste 40, the electrical connection may be realized by means of a metal solder ball 42. As shown in fig. 4, the second surface 11b of the first substrate 11 and the back surface of the circuit board 30 are provided with metal solder balls 42, the second surface 11b of the first substrate 11 and the first area i of the first surface 21a of the second substrate 21 are connected together by the metal solder balls 42, and the back surface of the circuit board 30 and the second area ii of the first surface 21a of the second substrate 21 are connected together by the metal solder balls. As another example, the metal solder balls 42 may be respectively disposed in the first region i and the second region II of the first surface 21a of the second substrate 21, so as to connect the second surface 11b of the first substrate 11 and the first region i of the first surface 21a of the second substrate 21 and connect the circuit board 30 and the second region II of the first surface 21a of the second substrate 21. As still another example, the metal solder balls 42 may also be provided on both surfaces to be connected, that is, the metal solder balls 42 may be provided on both the second surface 11b of the first substrate 21 and the back surface of the circuit board 30 and the first area i and the second area II of the second surface 11b and the first surface 21a of the second substrate 21.
In the above embodiment, the first substrate 11 is provided with the through hole 114, the image sensing chip 12 is located in the through hole 114, and the front surface of the image sensing chip 11 is flush with the first surface 11a of the first substrate 11. Because the height of the image sensing chip 12 is controlled by using the first surface 11a of the substrate 11 as a reference, and the first surface 11a of the substrate 11 does not change during the packaging process, uncontrollable factors influencing the height of the image sensing chip 12 hardly exist in the stacked packaging structure, so that the height of the image sensing chip 12 can be accurately controlled by the packaging structure, which is beneficial to reducing the deviation between the actual height and the design height of the image sensing chip 12, so that the actual height and the design height of the image sensing chip 12 are basically consistent, and therefore, the specific implementation mode can reduce the deviation between the actual height and the design height of the image sensing chip 12, realize the strict control on the height of the image sensing chip 12, and further improve the imaging quality of the image sensor.
In addition, as another specific example of the present application, the image sensing chip 12 may also be located on the first surface 11a of the first substrate 11. As shown in fig. 5, the image sensing chip 12 is located on the first surface 11a of the first substrate 11, and the image sensing chip 12 is adhered to the first surface 11a of the first substrate 11 by the adhesive 14.
In the above example, the image sensing chip 12 is changed from being disposed in the first substrate 11 to being disposed on the first surface 11a of the first substrate 11 in the stacked package structure of fig. 2A, but as an extension of the embodiment of the present application, the image sensing chip 12 may be disposed on the first surface 11a of the first substrate 11 in the stacked package structure shown in the example of fig. 3 or 4. Based on the disclosed implementation of changing the position of the image sensing chip 12 based on the package-on-package structure shown in fig. 2A, a person skilled in the art can easily find a specific implementation of changing the position of the image sensing chip 12 to a package-on-package structure located on the first surface 11a of the first substrate 11 based on the package-on-package structure shown in any one of fig. 3 to 4. For the sake of brevity, this particular implementation is not described in detail herein.
As another specific example of the present application, on the basis of the stacked package structure shown in any one of the above specific examples, in order to protect the second leads 13 from being scratched, as shown in fig. 6, the second leads 13 may also be wrapped by a plastic molding material 14. In order to package the second leads 13 with the molding compound 14, the first surface 11a of the substrate 11 and the front surface of the image sensing chip 12 except for the photosensitive area 121 are all packaged with the molding compound, so as to form a molding structure.
In addition, as another alternative embodiment of the present application, in order to prevent the photosensitive area 121 from being contaminated by the outside, as shown in fig. 7, on the basis of the stacked package structure shown in any of the above specific examples, a transparent protection layer 15 disposed on the first surface 11a of the substrate 11 for protecting the photosensitive area 121 may be further included. The transparent protective layer 15 may be an antireflection glass layer. In addition, the transparent protective layer 15 may be a plastic film.
It should be noted that the package-on-package structure shown in fig. 7 is a structure improved from the package-on-package structure shown in fig. 2A. As an extension of the embodiment of the present application, a transparent protection layer 15 may be further added to any of the package structures shown in fig. 3 to 6 to prevent the photosensitive area 121 from being contaminated by the outside.
It should be noted that, since the transparent protection layer 15 is a transparent material layer, when assembling the lens module assembly subsequently, the lens module assembly can be directly assembled on the transparent protection layer 15, or the lens module assembly can be assembled on the first surface 11a of the substrate 11 by removing the transparent protection layer 15. Moreover, the lens module assembly is assembled after the transparent protective layer 15 is removed, so that the formed image sensor does not have optical phenomena such as chromatic aberration or ghost, and the like, and the image quality of the image sensor is improved.
As a specific example of the present application, the transparent protection layer 15 may be closely adjacent to the first surface 21a of the substrate 21, and the corresponding cross-sectional structure is shown in fig. 7. As another specific example of the present application, as shown in fig. 8, a certain distance exists between the transparent protection layer 15 and the first surface 11a of the substrate 11, so that a sealed cavity 16 is formed between the transparent protection layer 15 and the image sensing chip 12, and the photosensitive area 121 is located in the sealed cavity 16, so that the photosensitive area 121 can be prevented from being polluted by dust and other contaminants. As an embodiment of the present invention, in order to form the sealed cavity 16 between the transparent protection layer 15 and the image sensing chip 12, a supporting structure 17 for supporting the transparent protection layer 15 is formed on the first surface 11a of the substrate 11, the supporting structure 17 is located between the transparent protection layer 15 and the image sensing chip 12, and the three surround to form the sealed cavity 16.
In the embodiment of the present application, the supporting structure 17 may be made of a photosensitive resist, and is formed on the first surface 11a of the substrate 11 by an exposure and development process.
In other embodiments, the first surface 11a of the substrate 11 may also have other devices, such as resistors, inductors, capacitors, integrated circuit blocks or optical components, and the specific device type may be selected according to the types of the substrate and the image sensing chip.
In the specific implementation of the package on package structure shown in fig. 2A to 8, no lens module assembly is disposed on the first surface 11a of the substrate 11. In order to manufacture the image device, it is necessary to mount the lens module assembly on the first surface 11a of the substrate 11 when manufacturing the image device, and the lens in the lens module assembly is opposite to the photosensitive area 121 of the image sensor chip 12.
As another specific implementation manner of the present application, a lens module assembly may be further disposed on the first surface 11a of the substrate. Fig. 9 is a schematic cross-sectional structure diagram corresponding to the specific implementation manner.
It should be noted that fig. 9 is an improvement of the stacked package structure of the image sensor chip shown in fig. 2A, and the package structure of the image sensor chip shown in fig. 9 has many similarities with the stacked package structure of the image sensor chip shown in fig. 2A, and for the sake of brevity, only the differences are described here, and the similarities are described with reference to the related description of fig. 2A.
The package-on-package structure of the image sensor chip shown in fig. 9 may include, in addition to the components shown in fig. 2A: a lens module assembly 18 disposed on the first surface 11a of the substrate 11.
The lens module assembly 18 includes a lens 181 and a lens holder 182, wherein the lens holder 182 is fixedly connected to the first surface 11b of the substrate 11. As an example, the lens holder 182 may be adhered to the first surface 11a of the substrate 11 by an adhesive glue 183. In order to make the light passing through the lens 181 easily detected by the photosensitive area 121, the lens 181 may be opposite to the photosensitive area 121 of the image sensor chip 12, for example. Further, as an example, one lens 181 may correspond to one image sensing chip 12, or one lens 181 may correspond to a plurality of image sensing chips 12.
In the embodiment of the present application, there is a certain space between the first substrate 11 and the lens 181, and therefore, other devices can be further formed on the first surface 11a between the lens 181 and the first substrate 11, and the other devices can form a high-density stacked structure between the lens holder 182 and the first substrate 11, thereby facilitating miniaturization of the devices. In addition, an optical component, such as a polarizer, an infrared filter, etc., may be further formed between the lens 181 and the first surface 11a of the first substrate 11 for improving the imaging quality of the image sensor.
It should be noted that the above example is an example of adding a lens module assembly to the package-on-package structure of fig. 2A. As an extension of the embodiment of the present application, a lens module assembly may be added to the package structure shown in any one of fig. 3 to 8. Based on the disclosed implementation of adding a lens module assembly to the package structure of fig. 2A, a person skilled in the art can easily find out a specific implementation of adding a lens module assembly to the package structure of any one of fig. 3 to 8. For the sake of brevity, this particular implementation is not described in detail herein.
In the above specific implementation manner with the lens module assembly, the package structure of the image sensor chip includes the lens module assembly, so that when the image sensor is formed, an additional process of assembling the lens module assembly is not required, and the assembling process of the image sensor is saved.
The foregoing is a specific implementation manner of the stacked package structure of the image sensor chip provided in the embodiment of the present application. In the above specific implementation manner, the image sensing chip package 10 and the circuit board 30 are located on the same surface side of the control chip package 20, and the circuit board 30 is located beside the image sensing chip package 10, so that the circuit board 30 does not affect the thickness of the whole stacked package structure 200, and the total thickness of the stacked package structure 200 is the sum of the thicknesses of the image sensing chip package 10 and the control chip package 20, therefore, compared with the stacked package structure in the prior art, the stacked package structure provided in the embodiment of the present application has a thinner thickness, a better flatness, a simpler structure, reduces the process difficulty, and is beneficial to miniaturization of the image sensor.
The foregoing is a specific implementation manner of the stacked package structure of the image sensor chip provided in the embodiment of the present application. Based on the specific implementation mode, the embodiment of the application also provides a specific implementation mode of the stack packaging method of the image sensing chip.
Referring to fig. 10, a method for packaging a stack of image sensor chips according to an embodiment of the present disclosure includes the following steps:
s1001: providing an image sensing chip package 10, a control chip package 20 and a circuit board 30; the image sensing chip package 10 includes a first substrate 11 and an image sensing chip 12, the first substrate 11 includes a first surface 11a and a second surface 11b opposite to each other, and the image sensing chip 12 is electrically connected to the first surface 11a of the first substrate 11; the control chip package 20 comprises a second substrate 21 and a control chip 22, wherein the second substrate 21 comprises a first surface 21a and a second surface 21b which are opposite to each other, and the first surface 21a of the second substrate 21 comprises a first area I and a second area II; the control chip 22 is located on the second surface 21b side of the second substrate 21, and is electrically connected to the second surface 21b of the second substrate 21.
The image sensing chip package 10 includes a first substrate 11 and at least one image sensing chip 12. The first substrate 11 includes opposing first and second surfaces 11a and 11 b. As an example, the first substrate 11 may be a printed circuit board, i.e., a PCB board. The control chip package 20 includes a second substrate 21 and a control chip 22. The control chip 22 may be an ASIC chip, the number of the control chips 22 may be plural, and one control chip 22 may correspond to at least one image sensing chip 12. Similarly, the second substrate 21 includes a first surface 21a and a second surface 21b opposite to each other, and the second substrate may be a PCB.
A first pad 111 is disposed on the first surface 11a of the first substrate 11; the second surface 11b of the substrate 11 is provided with a second pad 112, and the second pad 112 is used for electrically connecting the substrate 11 and the control chip 22.
The cross-sectional structure of the step is shown in fig. 11A.
S1002: the first area i and the second area ii of the first surface 21a of the second substrate 21 are coated with conductive paste 40, respectively.
In this step, the conductive paste 40 may be continuous, and the conductive paste 40 may be coated on both the first surface side 21b of the second substrate 21, so that both the first area i and the second area ii of the second substrate 21 are covered with the conductive paste 40. As another example of the present application, the conductive paste 40 on the first surface 21a of the second substrate 21 may be discontinuous, and the conductive paste 40 may be coated at positions where the first region and the second region need to be electrically connected, respectively.
The cross-sectional structure of the step is shown in fig. 11B.
S1003: the image sensor chip package 10 and the circuit board 30 are disposed in parallel on the first surface 21a side of the second substrate 21, the first region i is electrically connected to the second surface 11b of the first substrate 11 through the conductive adhesive 40, and the second region ii is electrically connected to the circuit board 30.
In this step, the second surface 11b of the first substrate 11 may be aligned with the first region i coated with the conductive paste 40, and the second surface 11b of the first substrate 11 may be attached to the first region i to electrically connect the first region i with the second surface 11b of the first substrate 11. Similarly, the back surface of the circuit board 30 may be aligned with the second area ii coated with the conductive paste 40, and the back surface of the circuit board 30 may be attached to the second area ii to implement the circuit connection of the second area ii and the circuit board 30.
By arranging the image sensing chip package and the circuit board 30 in parallel on the same side of the second substrate 21, the number of layers of the stacked package structure can be reduced by one layer, thereby reducing the total thickness of the stacked package structure. The first region i and the second surface 11b of the first substrate 11 can be electrically connected through the conductive adhesive 40, and the second region ii and the circuit board 30 can be electrically connected, so that signals can be transmitted among the circuit board 30, the control chip 22 and the image sensing chip 12.
The corresponding cross-sectional structure schematic diagram after the step is executed can be seen in fig. 2A.
In the above embodiment, the first area i is electrically connected to the second surface 11b of the first substrate 11 by coating the conductive adhesive 40 on the first area and the second area of the first surface 21a of the second substrate 21, and the second area ii is electrically connected to the circuit board 30, as an extension of the embodiment of the present application, the conductive adhesive 40 may be coated on the second surface 11b of the first substrate and the back surface of the circuit board 30, or the conductive adhesive 40 may be coated on the second surface 11b of the first substrate 11, the first area i, and the back surface and the second area of the circuit board 30, the second surface 11b of the first substrate 11 and the first area i of the first surface 21a of the second substrate 21 are bonded together by the conductive adhesive 40, and the back surface of the circuit board 30 and the second area ii of the first surface 21a of the second substrate 21 are bonded together by the conductive adhesive 40.
The conductive paste 40 functions to realize an electrical connection between the two surfaces. As an extension of the embodiment of the present application, it is easily suggested by those skilled in the art that a metal solder 41 or a metal solder ball 42 is used instead of the conductive paste 40 to realize the electrical connection between the two surfaces. The process of electrically connecting the first region i and the second surface 11b of the first substrate 11 by the metal solder 41 or the metal solder ball 42 and electrically connecting the second region ii and the circuit board 30 is similar to the above-mentioned embodiment of electrically connecting by the conductive paste 40, and reference can be made to the above-mentioned embodiment. Wherein,
fig. 3 shows a schematic cross-sectional structure of the circuit board 30, which is obtained by soldering the second surface 11b of the first substrate 11 and the first area i of the first surface 21a of the second substrate 21 by the metal solder 41 and soldering the front surface of the circuit board 21 and the second area ii of the first surface 21a of the second substrate 21 by the metal solder 41 through a metal bonding process.
Fig. 4 shows a schematic cross-sectional structure of the circuit board 30, which is obtained by soldering the second surface 11b of the first substrate 11 and the first area i of the first surface 21a of the second substrate 21 together through the solder balls 42 and soldering the front surface of the circuit board and the second area ii of the first surface 21a of the second substrate 21 together through the solder balls 42.
The foregoing is a method for packaging stacked image sensor chips according to an embodiment of the present application. In the stack package method, the circuit board 30 and the image sensing chip package 10 are arranged in parallel on the same surface side of the control chip package 20, specifically, the circuit board 30 is located beside the image sensing chip package 10, and both are arranged on the first surface 21a of the second substrate of the control chip package 20, so that the circuit board 30 does not affect the thickness of the whole stack package structure 200, and the total thickness of the stack package structure 200 is the sum of the thicknesses of the image sensing chip package 10 and the control chip package 20.
The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.
Claims (26)
1. A package on package structure, comprising:
the image sensor comprises an image sensing chip packaging body, a control chip packaging body and a circuit board;
the image sensing chip package comprises a first substrate and at least one image sensing chip, wherein the first substrate comprises a first surface and a second surface which are opposite, and the image sensing chip is electrically connected to the first surface of the first substrate;
the control chip package comprises a second substrate and at least one control chip, wherein the second substrate comprises a first surface and a second surface which are opposite, the first surface of the second substrate comprises a first area and a second area,
the control chip is positioned on the second surface side of the second substrate and is electrically connected to the second surface of the second substrate;
the image sensing chip package and the circuit board are both located on the first surface side of the second substrate, the circuit board is located beside the image sensing chip package, the second surface of the first substrate is electrically connected with the first region of the first surface of the second substrate, and the circuit board is electrically connected with the second region of the first surface of the second substrate.
2. The package on package structure of claim 1, wherein the second surface of the first substrate and the first region of the first surface of the second substrate are bonded together by a conductive adhesive, and the back surface of the circuit board and the second region of the first surface of the second substrate are bonded together by a conductive adhesive.
3. The package on package structure of claim 2, wherein the conductive adhesive is an anisotropic conductive adhesive.
4. The package on package structure of claim 1, wherein the second surface of the first substrate and the first region of the first surface of the second substrate are electrically connected together by means of metal bonding, and the back surface of the circuit board and the second region of the first surface of the second substrate are electrically connected together by means of metal bonding.
5. The package on package structure of claim 1, wherein the second surface of the first substrate and the back surface of the circuit board are provided with solder balls, the second surface of the first substrate and the first region of the first surface of the second substrate are connected together through the solder balls, and the back surface of the circuit board and the second region of the first surface of the second substrate are connected together through the solder balls.
6. The package on package structure of claim 1, wherein the control chip is flip-chip mounted on the second surface of the second substrate.
7. The package on package structure of claim 6, wherein the control chip is multiple, the multiple control chips form a vertical stack structure, and surfaces of different control chips do not completely overlap.
8. The package on package structure of claim 7, wherein the control chip is electrically connected to the second surface of the second substrate through a first lead.
9. The package on package structure of claim 1, wherein one of the control chips corresponds to at least one of the image sensor chips.
10. The package on package structure of claim 1, wherein the control chip is an ASIC chip.
11. The package on package structure of claim 1, wherein the first substrate has a through hole, the image sensor chip is located in the through hole, and a front surface of the image sensor chip is flush with the first surface of the first substrate.
12. The package structure of claim 11, wherein one of the image sensor chips is disposed in one of the through holes, and a front surface of each of the image sensor chips is flush with the first surface of the substrate.
13. The package structure of claim 11, wherein at least two of the image sensor chips are disposed in one of the through holes, and a front surface of each of the image sensor chips is flush with the first surface of the substrate.
14. The package on package structure of claim 1, wherein the image sensor chip is located on the first surface of the first substrate.
15. The package on package structure of claim 14, wherein the image sensor chip is bonded to the first surface of the first substrate by an adhesive.
16. The package on package structure of any one of claims 1 to 15, wherein a light sensing area and a bonding pad outside the light sensing area are disposed on the front surface of the image sensing chip, and the bonding pad is electrically connected to the first surface of the first substrate through a second lead.
17. The package on package structure of claim 16, wherein the second leads are encased by a mold compound.
18. The package on package structure of any one of claims 1 to 15, wherein the image sensor chip package further comprises a lens module assembly disposed on the first surface of the first substrate.
19. The package on package structure of claim 17, wherein the lens module assembly comprises a lens and a lens holder, the lens holder being fixedly connected to the first surface of the substrate.
20. The package on package structure of any one of claims 1-15, wherein the image sensor chip package further comprises: a transparent protective layer formed over the first substrate first surface.
21. The package on package structure of claim 20, wherein the transparent protective layer is an anti-reflective glass layer.
22. The package on package structure of claim 20, wherein a sealed cavity is formed between the transparent protection layer and the image sensor chip.
23. A stack packaging method, comprising:
providing an image sensing chip package, a control chip package and a circuit board; the image sensing chip package comprises a first substrate and at least one image sensing chip, wherein the first substrate comprises a first surface and a second surface which are opposite, and the image sensing chip is electrically connected to the first surface of the first substrate; the control chip package comprises a second substrate and at least one control chip, wherein the second substrate comprises a first surface and a second surface which are opposite, and the first surface of the second substrate comprises a first area and a second area; the control chip is positioned on the second surface side of the second substrate and is electrically connected to the second surface of the second substrate;
the image sensing chip package and the circuit board are arranged in parallel on the first surface side of the second substrate, the first region is electrically connected to the second surface of the first substrate, and the second region is electrically connected to the circuit board.
24. The package on package method according to claim 23, wherein the arranging the image sensor chip package and the circuit board in parallel on the first surface side of the second substrate, electrically connecting the first region to the second surface of the first substrate, and electrically connecting the second region to the circuit board comprises:
coating a conductive adhesive on the second surface of the first substrate and/or on the first area of the first surface of the second substrate, and coating a conductive adhesive on the back surface of the circuit board and/or on the second area of the first surface of the second substrate;
and bonding the second surface of the first substrate and the first area of the first surface of the second substrate together through a conductive adhesive, and bonding the back surface of the circuit board and the second area of the first surface of the second substrate together through a conductive adhesive.
25. The package on package method according to claim 23, wherein the arranging the image sensor chip package and the circuit board in parallel on the first surface side of the second substrate, electrically connecting the first region to the second surface of the first substrate, and electrically connecting the second region to the circuit board comprises:
coating a metallic solder on the second surface of the first substrate and/or on a first area of the first surface of the second substrate, and coating a metallic solder on the front surface of the circuit board and/or on a second area of the first surface of the second substrate;
and welding the second surface of the first substrate and the first area of the first surface of the second substrate together through a metal welding material by a metal bonding process, and welding the front surface of the circuit board and the second area of the first surface of the second substrate together through a metal welding material.
26. The package on package method of claim 23,
the disposing the image sensing chip package and the circuit board in parallel on the first surface side of the second substrate, electrically connecting the first region with the second surface of the first substrate, and electrically connecting the second region with the circuit board specifically includes:
forming a metal solder ball on the second surface of the first substrate and/or on the first area of the first surface of the second substrate, and forming a metal solder ball on the front surface of the circuit board and/or on the second area of the first surface of the second substrate;
and welding the second surface of the first substrate and the first area of the first surface of the second substrate together through a metal welding ball by a welding process, and welding the front surface of the circuit board and the second area of the first surface of the second substrate together through the metal welding ball.
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| CN201711226357.1A CN107808889B (en) | 2017-11-29 | 2017-11-29 | Stacked package structure and packaging method |
| US16/194,080 US10541264B2 (en) | 2017-11-29 | 2018-11-16 | Package-on-package structure and package-on-package method |
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