KR20100053189A - Semiconductor package - Google Patents

Abstract

PURPOSE: A semiconductor package is provided to prevent the thickness of a semiconductor package from increasing due to the lamination of semiconductor chips by applying a step type window design. CONSTITUTION: A circuit pattern(111) is situated on one side of a first substrate(110). A window penetrated from one side of the first substrate and throughout another side, is formed. A circuit pattern(121) is located on one side of a second substrate(120). A window penetrated from one side of the second substrate and throughout another side, is formed. The second substrate comprises a step part which is exposed to the window of the first substrate. The step part comprises a die bonding area(122) and a wire bonding area.

Description

Semiconductor Package {Semiconductor package}

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of implementing a function of a thin high density chip while increasing the possibility of stacking semiconductor chips.

With the rapid development of semiconductor technology and the popularization of the semiconductor industry, the role of semiconductors has become very important in all electronic products that can be encountered in everyday life. The semiconductor industry has evolved toward making smaller, thinner semiconductors that are highly functional. One of the big trends has been to develop a package form and develop a semiconductor chip stacking method for the development of a high-performance package with a small volume.

Accordingly, there is a need for a semiconductor substrate and a semiconductor packaging method for implementing the functions of a thin high density chip while increasing the possibility of stacking semiconductor chips. In particular, it is necessary to develop a new type of substrate for accommodating high density semiconductor chips. Therefore, the present invention can be widely applied to a semiconductor package related field.

The conventional stacked semiconductor package has a larger capacity semiconductor package by stacking semiconductor chips in various shapes and directions on a semiconductor substrate and performing wire bonding, or by stacking a package in which one or more semiconductor chips are stacked. There may be a method of making or laminating using both sides simultaneously regardless of the top and bottom surfaces.

In addition, the development of semiconductor substrate materials with high-density fine pitch patterns to secure input and output terminals of high-density semiconductor chips, as well as development of components such as wire bonding equipment and gold wires that enable wire bonding of high-density patterns. This must be done at the same time.

However, this problem requires a lot of time because of simultaneous development in equipment and materials field and price competitiveness.

An object of the present invention is to provide a semiconductor package that can easily secure a wire bonding region and can minimize an increase in thickness due to stacking of semiconductor chips.

The present invention provides a display device comprising: a first substrate having a circuit pattern disposed on at least one surface thereof and a window penetrating from one surface to the other surface; And a second substrate having a circuit pattern disposed on at least one surface thereof and stacked on the first substrate to form a window penetrating from one surface to the other surface, wherein the window of the first substrate is larger than the window of the second substrate. It provides a semiconductor package having a stepped portion that is large and the second substrate is exposed to the window of the first substrate.

The stepped portion may include a die seating portion on which a semiconductor chip is seated, and a wire bonding region in which a wire bonding portion may be disposed, the wire bonding portion being extended from the circuit pattern of the second substrate to be electrically connected to the semiconductor chip. can do.

A wire bonding part may be provided on an opposite surface of the die mounting part of the second substrate to electrically connect the second substrate to the semiconductor chip by a bonding wire.

A plurality of the semiconductor chips may be stacked.

The semiconductor chip is stacked on a first surface of the first semiconductor chip that is seated on the die seat, a first surface that is opposite to a surface of the first semiconductor chip that is in contact with the die seat, and the second The third semiconductor chip may be stacked in a space formed by the window of the second substrate on the second surface, which is the surface opposite to the first surface of the first semiconductor chip.

The first semiconductor chip seated on the die mounting part may be electrically connected to the second substrate by flip chip bonding.

The display device may further include a molding part including the semiconductor chip and the bonding wire to surround surfaces exposed to the outside of the first substrate and the second substrate.

At least one solder ball may be further disposed on a surface opposite to a surface on which the first substrate of the second substrate is stacked.

A window formed on a surface on which the solder balls are disposed may have a shape in which at least one of a straight line, a cross, a square, a rectangle, and a circle is combined.

The height of the semiconductor chip seated on the second substrate may be lower than or equal to the first substrate.

Another aspect of the present invention provides a semiconductor package in which a plurality of semiconductor packages are stacked.

According to the semiconductor package according to the present invention, it is possible to easily secure the wire bonding region and minimize the increase in thickness due to the stacking of the semiconductor chips.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention according to a preferred embodiment.

1 shows a cross section of a semiconductor package 10, which is a preferred embodiment of the present invention. FIG. 2 schematically shows a first substrate 110 and a second substrate 120 on which semiconductor chips are mounted in the semiconductor package 10. 7 illustrates various window shapes formed on the second substrate 120.

Referring to the drawings, the semiconductor package 10 according to the present invention includes a first substrate 110; And a second substrate 120. The circuit pattern 111 may be disposed on at least one surface of the first substrate 110, and a window penetrated from one surface to the other surface may be formed. A circuit pattern 121 is disposed on at least one surface of the second substrate 120, and a window penetrating from one surface to the other surface by being stacked on the first substrate 110 may be formed.

In this case, in the present invention, the windows of the first substrate 110 are larger than the windows of the second substrate 120, and the step portions 122 and 123a exposing the second substrate 120 to the windows of the first substrate 110. It may be provided.

The semiconductor package 10 according to the present invention applies a stepped window design using a step, thereby securing sufficient space for the wire bonding unit for the electrical connection by the semiconductor chip 140 and the wire bonding and of the semiconductor chips 141 and 142. The increase in thickness due to lamination can be minimized.

That is, in the present invention, two or more substrates 110 and 120 are stacked, and windows that penetrate both surfaces are formed on the substrates 110 and 120, and the thickness of the substrates 110 and 120 formed by the window is increased. The semiconductor chip 140 may be accommodated in the space to be formed.

In this case, the stepped portions 122 and 123a may be formed on the second substrate 120 by the window size difference with the first substrate 110. Therefore, a space in which the wire bonding portion 123 may be disposed may be secured in the stepped portions 122 and 123a according to the stacking of two or more substrates 110 and 120, thereby resulting in a bonding distance for wire bonding. Can be shortened.

In addition, since two or more substrates 110 and 120 are stacked, the circuit patterns 111 and 121 formed on the respective substrates 110 and 120 are formed in each layer of the substrates 110 and 120. The circuit patterns 111 and 121 can be used with ease. Therefore, even if a plurality of semiconductor chips 141 and 142 are stacked, sufficient circuit wiring for efficiently using the stacked semiconductor chips 141 and 142 can be used.

In this case, the step portions 122 and 123a may include the die seating portion 122 and the wire bonding region 123a. The die mounting part 122 is an area where the semiconductor chip is seated. The wire bonding area 123 may be disposed to extend from the circuit pattern 121 of the second substrate 120 to be electrically connected to the semiconductor chip 140 so that the bonding wire 115 is connected. Area.

In addition, the second wire 120 has a back wire bonding part 124 which is electrically connected to the second substrate 120 by the semiconductor chip 140 and the bonding wire 115 on the opposite side of the surface on which the die seating part is located. ) May be provided.

In this case, a bonding pad 115 is provided on a surface of the bonding wire 115 exposed through the window of the surface attached to the die seat 122 of the semiconductor chip 140 through the window of the second substrate 120. ) And the back wire bonding unit 124 may be electrically connected.

Accordingly, more necessary circuit wirings may be more efficiently used according to the stacking of the semiconductor chips 140.

The number of stacked substrates 110 and 120 may be determined according to a required level of the semiconductor chip 140 stacked and mounted, and the number of stacked substrates 110 and 120 is not limited. In addition, there is no particular limitation on the number of stacked semiconductor chips 140, and designs such as the width and shape of the terminal parts 122 and 123a may be changed by the size of the semiconductor chips 140 to be mounted.

In this case, the semiconductor chip 140 is preferably stacked in the upper surface direction of the substrate, but the present invention is not limited thereto. The semiconductor chip 140 may also be stacked in the lower surface direction, or may be stacked in both the upper surface direction and the lower surface direction. Therefore, the stacking density of the semiconductor chip 140 can be increased.

Meanwhile, as shown in FIG. 7, the shape of the window may be designed in various forms according to the utilization of the semiconductor chip 140. The shape of the window may be straight (71), cross (72), square (73), rectangle (74), and round (not shown). In addition, the shape of the window may be a combination of two or more of straight, cross, square, rectangular, and circular (not shown). In one embodiment, a shape may be formed by a combination 75 of crosses and squares, a combination of crosses and rectangles (not shown), and a combination of crosses and circles (not shown).

That is, the window formed on the surface on which the solder balls 160 are disposed may be formed in a shape in which at least one of a date, a cross, a square, a rectangle, and a circle is combined. Therefore, the semiconductor package 10 according to the present invention may be applied to the semiconductor chip 140 having various designs.

In addition, the semiconductor package 10 according to the present invention includes a semiconductor chip 140 and a bonding wire 115 to cover at least a portion of the surface exposed to the outside of the first substrate 110 and the second substrate 120. The molding unit 150 may be further provided. Accordingly, the circuit patterns 111 and 121, the semiconductor chip 140, and the bonding wires 115 formed on the substrates 110 and 120 may be protected.

In addition, the semiconductor package 10 according to the present disclosure may further include at least one solder ball 160 disposed on a surface opposite to a surface on which the first substrate 110 of the second substrate 120 is stacked. The solder ball 160 may function as an external connection terminal connecting the semiconductor package 10 to the outside.

3 illustrates a semiconductor package 30 in which the semiconductor chip 340 is stacked on the surface on which the semiconductor chip 340 is mounted, and on the opposite surface thereof.

Referring to the drawings, the semiconductor package 30 may be stacked on the surface on which the semiconductor chip 340 is seated on the second substrate 320 and on the opposite surface thereof. As an example, the semiconductor chip 340 may be stacked in three or more layers including the first semiconductor chip 341, the second semiconductor chip 342, and the third semiconductor chip 343.

The first semiconductor chip 341 may be mounted on the die mounting part 322. The second semiconductor chip 342 may be stacked on a first surface that is opposite to a surface of the first semiconductor chip 341 that is in contact with the die seating portion 322. The third semiconductor chip 343 may be stacked into a space formed by a window of the second substrate 320 on the second surface, which is the opposite surface of the first surface of the first semiconductor chip 341.

Accordingly, by allowing the third semiconductor chip 343 to be disposed in a space formed by the window of the second substrate 320, the increase in thickness due to the stacking of the semiconductor chips 340 may be minimized.

In this case, a back wire bonding part for allowing the second substrate 320 to be electrically connected to the third mounting surface 322 of the second substrate 320 by the third semiconductor chip 343 and the bonding wire 315. 324 is preferably provided.

In this case, a bonding pad (not shown) is provided on the surface of the bonding wire 315 exposed through the window of the surface attached to the die seating portion 322 of the semiconductor chip 340 through the window of the second substrate 320. And the back wire bonding portion 324 may be electrically connected. Accordingly, more necessary circuit wirings may be more efficiently used according to the stacking of the semiconductor chips 340.

In this case, the stacked substrates 310, 320, and 330 may include a first substrate 310, a second substrate 320, and a third substrate 330, and may be stacked in three or more layers. Here, in the cross-section of the stacked substrates 310, 320, and 330, a portion where each substrate is stacked may be provided with a stepped portion, and each step may be provided with a wire bonding region including a wire bonding portion.

However, wire bonding areas are not required to be formed in every single layer in a portion where each of the substrates are stacked, and a wire bonding area may be selectively provided only in a layer requiring wire bonding.

In addition, the semiconductor chip 340 may further include a fourth semiconductor chip 344, and the semiconductor package 30 may include the semiconductor chip 340 stacked in three or more layers according to an embodiment. As a result, the degree of integration of the semiconductor chip 340 included in one package may be improved, and the increase in the thickness of the semiconductor package 30 may be minimized even when the number of stacked semiconductor chips 340 is increased.

Meanwhile, the semiconductor package 30 illustrated in FIG. 3 includes a second semiconductor chip 342 and a third semiconductor chip 343 mounted on the second substrate 320 with respect to the semiconductor package 10 illustrated in FIG. 1. As an embodiment in which each is stacked on both sides of the first semiconductor chip 341, the same components as in the semiconductor package 10 of FIG.

In addition, each of the semiconductor packages 40, 50, and 60 illustrated in FIGS. 4 to 5 is a modified embodiment of the semiconductor package 10 illustrated in FIG. 1, and the semiconductor package 10 of FIGS. The same reference numerals are used for the same components as in 30, and detailed descriptions thereof are omitted.

4 illustrates a semiconductor package 40 in which the semiconductor chip 440 mounted on the die mounting part 422 is electrically connected to the second substrate 420 by flip chip bonding. That is, the first semiconductor chip 441 seated on the die mounting part 422 in the semiconductor package 40 may be electrically connected to the second substrate 420 by flip chip bonding.

Accordingly, the second substrate 420 having the die mounting part 422 on which the semiconductor chip 440 is mounted may be applied in a form that does not require a space required for the wire bonding region for wire bonding.

That is, in the semiconductor package 40 according to the present exemplary embodiment, a complex multilayer design in which wire bonding and flip chip bonding types are combined is possible. Therefore, the advantage of the flip chip bonding can be utilized.

5 illustrates a semiconductor package 50 in which the height of the stacked semiconductor chips 540 is not higher than the height of the substrate 510. That is, in the semiconductor package 50 according to the present exemplary embodiment, the height of the semiconductor chip 540 mounted on the second substrate 520 may be lower than or equal to that of the first substrate 510.

Accordingly, even when the semiconductor chips 540 are stacked, the semiconductor package 50 can be formed without increasing the thickness of the semiconductor package 50.

FIG. 6 illustrates a stacked semiconductor package 60 in which two semiconductor packages 61 and 62 are stacked. To this end, each of the semiconductor packages 61 and 62 may be provided with ball lands 617 and 627 in which solder balls 616 and 626 may contact the upper surface of the exposed substrate.

In addition, each of the upper molding parts 615 and 625 of each of the semiconductor packages 61 and 62 is formed in a trapezoidal shape so that the ball lands 617 and 627 to which the solder balls 616 and 626 may contact are exposed. Can be.

Meanwhile, the semiconductor packages 10, 30, 40, 50, and 60 according to the present invention may be manufactured by the following process. In this case, the method of manufacturing a semiconductor package may include stacking a semiconductor chip and a substrate, wire bonding and / or flip chip bonding, and a molding process. At this time, each process can be a variety of orders and combinations, it can be determined by the level of stacking and ease of operation.

According to one embodiment of the method for manufacturing a semiconductor package, a process of laminating a top semiconductor chip, a top wire bonding, a top molding, a bottom semiconductor chip attachment, a bottom wire bonding, and a bottom molding may be provided. In this case, the semiconductor package may be manufactured by the order of the listed processes.

In another embodiment, the steps of stacking top and bottom semiconductor chips, top wire bonding, top protection cap installation, bottom wire bonding, and molding may be provided. In this case, the semiconductor package may be manufactured by the order of the listed processes.

In another embodiment, a process of top flip chip bonding, top semiconductor chip stacking, top wire bonding, top molding, bottom semiconductor chip attachment, bottom wire bonding, and bottom molding may be provided. In this case, the semiconductor package may be manufactured by the order of the listed processes.

In another embodiment, a process of top flip chip bonding, bottom semiconductor chip stacking, bottom wire bonding, bottom protection cap installation, top semiconductor chip stacking, top wire bonding, and molding may be provided. In this case, the semiconductor package may be manufactured by the order of the listed processes.

In another embodiment, a process of top flip chip bonding, top semiconductor chip stacking, top wire bonding, top molding, bottom semiconductor chip attachment, bottom wire bonding, and bottom molding may be provided. In this case, the semiconductor package may be manufactured by the order of the listed processes.

On the other hand, in the case of the simultaneous molding process of the upper surface and the lower surface, it is preferable to proceed with the subsequent process after the protective cap is installed on the surface where the wire bonding operation is first performed.

According to the present invention, by applying the stepped wire bonding area design, the wire bonding area which can be connected to the output terminal which becomes denser due to the multilayer stacking of the high capacity and thin semiconductor chip is increased by the stacking factor of the substrate. Therefore, as compared with the case where the wire bonding region is formed in the single layer, the space efficiency is increased and the increase in the wire bonding distance is minimized, thereby reducing the defect rate and improving the reliability.

In addition, by securing both the surface where the semiconductor chip is attached and the surface where the solder ball is attached to the wire bonding area, the density of the wire bonding area can be lowered as compared with the case of the multilayer lamination using the conventional cross section, and thus the application range of the lamination can be expanded. The failure rate due to wire bonding can be reduced.

In addition, since a step is formed in the semiconductor chip seating portion of the substrate to be stacked and stacked therebetween, even if the number of stacking of semiconductor chips increases, there is an effect that the thickness is reduced as compared with the general stacking method. It becomes possible.

In addition, since the semiconductor chip may be stacked in the space of the widow formed on the substrate, a thickness reduction effect of at least one layer may be obtained as compared with the general lamination method.

In addition, since the substrate has a stepped window, it becomes more competitive than general lamination methods when stacking semiconductor chips, and it is possible to stack substrates in multiple layers, so that a fine pitch pattern needs to be implemented even when a high density semiconductor chip is applied. Therefore, the defective rate can be lowered at the time of manufacturing the substrate. In addition, if the fine pitch pattern technology is stabilized in the future, the stepped window substrate according to the present invention can implement the fine pitch pattern on the laminated surface pattern, it can double the effect.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, it is merely an example, and those skilled in the art may realize various modifications and equivalent other embodiments therefrom. I can understand. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

1 is a cross-sectional view schematically showing a cross section of a semiconductor package according to a preferred embodiment of the present invention.

FIG. 2 schematically illustrates a first substrate and a second substrate on which a semiconductor chip is mounted in the semiconductor package of FIG. 1.

3 is a diagram illustrating an embodiment in which a semiconductor chip is stacked on a surface on which a semiconductor chip is seated on a second substrate and on an opposite surface thereof.

FIG. 4 is a diagram illustrating an embodiment in which a semiconductor chip seated on a die seat is electrically connected to a second substrate by flip chip bonding.

FIG. 5 is a diagram illustrating an embodiment in which the height of the stacked semiconductor chips is not higher than the substrate height.

FIG. 6 is a diagram schematically illustrating a stacked semiconductor package in which two semiconductor packages are stacked.

7 is a diagram schematically illustrating various window shapes.

<Explanation of symbols for the main parts of the drawings>

10: semiconductor package, 110: first substrate,

120: second substrate, 140: semiconductor chip,

122, die seat, 123a: wire bonding area,

113, 123: wire bonding portion.

Claims (11)

A first substrate on which at least one circuit pattern is disposed, wherein a window penetrated from one surface to the other surface is formed; And A second substrate having a circuit pattern disposed on at least one surface thereof and stacked on the first substrate to form a window penetrating from one surface to the other surface; The semiconductor package of claim 1, wherein the window of the first substrate is larger than the window of the second substrate and the second substrate is exposed to the window of the first substrate. The method of claim 1, The stepped portion, A die mounting portion on which the semiconductor chip is seated, and And a wire bonding region in which a wire bonding portion may be disposed to extend from the circuit pattern of the second substrate to be electrically connected to the semiconductor chip. The method of claim 1, And a wire bonding part provided at an opposite surface of the die mounting part of the second substrate to electrically connect the second substrate to the semiconductor chip by a bonding wire. The method of claim 2, A semiconductor package in which a plurality of the semiconductor chip is stacked. The method of claim 4, wherein The semiconductor chip, A first semiconductor chip seated on the die mounting part; A second semiconductor chip stacked on a first surface opposite to a surface of the first semiconductor chip which is in contact with the die seating portion; A third semiconductor chip stacked in a space formed by a window of the second substrate on a second surface that is the opposite surface of the first surface of the first semiconductor chip A semiconductor package having a. The method of claim 2, And a first semiconductor chip seated on the die seating portion is electrically connected to the second substrate by flip chip bonding. The method of claim 2, And a molding part including the semiconductor chip and the bonding wire to surround surfaces exposed to the outside of the first substrate and the second substrate. The method of claim 2, And at least one solder ball disposed on a surface opposite to a surface on which the first substrate of the second substrate is stacked. The method of claim 3, And a window formed on a surface on which the solder ball is disposed, in which at least one of a straight line, a cross, a square, a rectangle, and a circle is combined. The method of claim 2, And a height of the semiconductor chip seated on the second substrate is lower than or equal to the first substrate. A semiconductor package in which a plurality of semiconductor packages of any one of claims 2 to 10 are stacked.

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