CN115332215B - Interposer for chip packaging and manufacturing method - Google Patents
Interposer for chip packaging and manufacturing method Download PDFInfo
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- CN115332215B CN115332215B CN202211257955.6A CN202211257955A CN115332215B CN 115332215 B CN115332215 B CN 115332215B CN 202211257955 A CN202211257955 A CN 202211257955A CN 115332215 B CN115332215 B CN 115332215B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
Abstract
The embodiment of the invention provides an interposer for chip packaging and a manufacturing method thereof, belonging to the field of semiconductors and packaging. The material of the interposer comprises an organic material, the interposer comprising a first portion and a second portion, the first portion being located at a periphery of the second portion; the coefficient of thermal expansion of the first portion is less than the coefficient of thermal expansion of the second portion. The interposer has low stress remaining in the whole and low warpage in the whole.
Description
Technical Field
The invention relates to the field of semiconductors and packaging, in particular to an interposer for chip packaging and a manufacturing method thereof.
Background
The transition layer between the wafer die and the printed circuit substrate board is referred to as an interposer. As semiconductor chip design and fabrication technologies become more complex, the cost of a single large chip becomes prohibitive, and the same performance can be achieved at a lower cost by stacking chiplets through an interposer, which is used to facilitate connection of chiplets and transmit signals, but is expensive to fabricate and not widely used for connection with chiplets. The preparation process of the organic intermediate layer is mature, and the material and process cost is low, so that the requirements and the applications in more fields can be met.
The carrier needs to be peeled off in the manufacturing process of the organic interposer, and the residual stress of the interposer is released in the carrier peeling process, which causes the concave warpage of the interposer after the carrier is peeled off from the interposer.
The warpage of the interposer is usually improved by adjusting the process temperature and heat treatment in the prior art, but the improvement effect is also limited.
Disclosure of Invention
Embodiments of the present invention provide an interposer for chip packaging and a method for fabricating the same, wherein the interposer has low residual stress and low warpage.
In order to achieve the above object, embodiments of the present invention provide an interposer for chip packaging, the material of the interposer including an organic material; the interposer includes a first portion and a second portion, the first portion being located at a perimeter of the second portion; the coefficient of thermal expansion of the first portion is less than the coefficient of thermal expansion of the second portion.
Optionally, the coefficient of thermal expansion of the first portion is in the range of 10 × 10 -6 -30×10 -6 Degree/degree; the coefficient of thermal expansion of the second portion is in the range of 16 x 10 -6 -50×10 -6 Degree/deg.
Optionally, a metal through hole is formed in the interposer, and the metal is copper; the filler is arranged on the outer side of the through hole of the intermediate layer and is inorganic oxide; the proportion range of the fillers is as follows: 0% -75%, the proportion of the filler is proportional to the distance of the first part far away from the second part.
Optionally, the through hole is a conductive metal pillar for connecting multiple chips; the size of the perforations is 20-100 microns.
Optionally, the second part is a plate-shaped body; the first part is a rectangular frame structure, and the rectangular frame structure is positioned on the periphery of the first surface of the plate-shaped body; the cross-sectional area of the rectangular frame structure is smaller than the area of the first surface.
Optionally, the rectangular frame-like structure at least comprises a hollow rectangular frame.
Optionally, the thickness of the first portion is 100-200 microns, and the thickness of the second portion is 100-200 microns.
In another aspect, the present invention provides a method for fabricating an interposer for chip packaging, the method comprising the steps of: s1: adding a stripping glue to one side of the carrier plate; s2: preparing redistribution wires on the lift-off glue, comprising: sequentially forming a first seed conductive layer and a dielectric layer on the stripping glue, wherein the dielectric layer is provided with a circuit pattern; s3: filling electroplating materials into the gaps of the dielectric layer to form a conductive connecting layer; s4: repeating S2 and S3 for preparing a plurality of layers of redistribution wires to obtain a second part of the interposer; s5: forming a new seed conductive layer on the second part and coating a light resistor; s6: photoetching the light resistance to form a conducting channel; s7: electroplating the conducting channel to form a conducting metal column for leading out a chip pin; s8: removing the photoresist and etching to remove the redundant part of the seed conducting layer; s9: carrying out die pressing on the etched conductive metal column by using an organic material for wrapping the conductive metal column to obtain a first part of the intermediate layer, wherein the thermal expansion coefficient of the first part is smaller than that of the second part, and carrying out multiple die pressing by using die materials with different thermal expansion coefficients for adjusting the thermal expansion coefficient of the first part; s10: and removing the carrier plate to form the intermediate layer.
Optionally, the method further includes: operations S6-S7 are repeated for increasing the height of the conductive metal pillar before step S9.
Optionally, the carrier plate is made of silicon or glass; the electroplating material is copper; the conductive metal column is a copper column.
Optionally, the seed conductive layer is a metal with adhesiveness or conductivity; the dielectric layer is made of organic photosensitive materials or low-dielectric-coefficient materials, the organic photosensitive materials are at least one of polyimide and cyclobutene resin, and the low-dielectric-coefficient materials comprise at least one of silicon oxide and silicon oxynitride.
Optionally, the peeling glue is a temporary bonding glue, and the peeling mode is light peeling and/or heating peeling.
The invention provides an interposer for chip packaging, wherein the material of the interposer comprises an organic material; the interposer includes a first portion and a second portion, the first portion being located at a perimeter of the second portion; the coefficient of thermal expansion of the first portion is less than the coefficient of thermal expansion of the second portion. The interposer greatly reduces the residual stress of the interposer by setting different thermal expansion coefficients for different parts, and the interposer balances the stress of the interposer by using materials with different filling material proportions, so that the warpage of the interposer is reduced.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIGS. 1a-1b are schematic diagrams of a conventional interposer for chip packaging;
FIGS. 2a-2c are schematic diagrams of an interposer for chip packaging according to the present invention;
FIG. 3 is a schematic diagram of the distribution of the filler outside the through holes in the interposer of the present invention;
fig. 4 is a schematic diagram of a method for fabricating an interposer for chip packaging according to the present invention.
Description of the reference numerals
201-a first portion;
202-a second portion;
203-carrier plate.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Fig. 1a-1b are schematic diagrams of a conventional interposer for chip packaging, and as shown in fig. 1a-1b, in a conventional process for manufacturing the interposer, since the interposer is a plate-type structure, and a lower portion of the interposer is tightly bonded to a carrier 203, an upper surface of the interposer has a large tensile stress, and since the carrier 203 has a small thermal expansion during a manufacturing process, the interposer has a large tensile stress on the upper surface, and thus, in a process of peeling off the carrier 203, the large tensile stress on the upper surface of the interposer is released, which causes a concave warpage of the interposer after the carrier 203 peels off the interposer.
The inventors have found through research that the tensile stress of the interposer can be changed by changing the coefficient of thermal expansion of the specific material of the interposer, and according to a specific embodiment, the invention provides an interposer for chip packaging, wherein the material of the interposer comprises an organic material, and the type of the organic material is at least one of a molding material and a resin.
The interposer includes a first portion 201 and a second portion 202, the first portion 201 being located at a periphery of the second portion 202. In a preferred embodiment, fig. 2a-2c are schematic diagrams of an interposer for chip packaging according to the present invention, and specifically, fig. 2a is an integrated structure of the interposer and a carrier 203, and the interposer needs to be fixedly supported by the carrier at an early stage of manufacturing the interposer; FIG. 2b shows the interposer structure with the carrier 203 removed from the overall structure; fig. 2c is a top view of the interposer of fig. 2 b. Specifically, as shown in fig. 2a to 2c, the second portion 202 is a plate-shaped body, which may be rectangular; the first part 201 is a rectangular frame fence structure, and the rectangular frame structure is positioned on the periphery of the first surface of the plate-shaped body; the rectangular frame-shaped structure may be a hollow rectangular frame, and the area of the cross section of the rectangular frame-shaped structure is smaller than the area of the first surface.
The coefficient of thermal expansion of the first portion 201 is less than the coefficient of thermal expansion of the second portion 202. The thermal expansion coefficient refers to the length change proportion value of a solid substance when the temperature changes by 1 degree centigrade. The coefficients of linear expansion of the objects are different, and the coefficient of linear expansion of a typical metal is about 1X 10 -5 -2×10 -5 The linear expansion coefficient of the carrier plate 203 is about 3 x 10 in degrees centigrade (centigrade) -6 -7×10 -6 Degree/deg. Preferably, the coefficient of thermal expansion of the first portion 201 is in the range of 10 × 10 -6 -30×10 -6 Degree/degree; the second portion 202 has a coefficient of thermal expansion in the range of 16 x 10 -6 -50×10 -6 In degrees.
The medium layer is provided with a through hole; the outer side of the through hole of the medium layer is provided with a filler; the proportion range of the filler is as follows: 0 to 75 percent. The through holes are conductive metal posts and are used for connecting multiple chips; the size of the perforations is 20-100 microns, and the size is the pore size of the perforations. The thickness of the first portion 201 is 100-200 microns; the thickness of the second portion 202 is 100-200 microns.
The proportion of the filler is proportional to the distance from the first portion 201 to the second portion 202, i.e. the proportion of the filler is larger and larger in the direction from the second portion 202 to the first portion 201, as shown in fig. 3, the filler (particulate matter) is shown in the figure, and the first portion 201 and the second portion 202 both contain the filler, wherein the proportion of the filler outside the through holes is proportional to the distance from the second portion 202, i.e. the proportion of the filler at both ends of the interposer is the maximum value and the minimum value of the proportion of the filler. The method enables the medium layer to change in an increasing mode along with the increase of the proportion of the filler, and therefore the coefficient of thermal expansion changes in a decreasing mode.
In a preferred embodiment, the second part 202 of the interposer of the present invention is polyimide, the conductive metal is copper, and the overall thermal expansion coefficient is 18 × 10 -6 -20×10 -6 The thermal expansion coefficient of the first portion 201 is reduced to 7 x 10 by using a silicon oxide-filled resin material -6 -10×10 -6 And/degree, the warpage is reduced to below 3 mm after the carrier plate 203 is removed.
In the conventional interposer, the warpage of the interposer 203 after removing the polyimide is larger than 6 mm.
According to the interposer disclosed by the invention, different thermal expansion coefficients are set for different parts, so that the first part 201 has smaller tension, the second part 202 has larger tension, in the process of peeling the carrier plate 203, the lower surface of the second part 202 has smaller deformation under the action of the carrier plate 203, and if the upper surface of the second part 202 does not limit the release of tensile stress, the second part 202 has larger deformation, which can cause the warpage of the whole interposer.
The invention also provides a manufacturing method of the interposer for chip packaging, which comprises the following steps: s1: adding a stripping glue to one side of the carrier plate 203; s2: preparing redistribution wires on the lift-off glue, comprising: sequentially forming a first seed conductive layer and a dielectric layer on the stripping glue, wherein the dielectric layer is provided with a circuit pattern; s3: filling electroplating materials into the gaps of the dielectric layer to form a conductive connecting layer; s4: repeating S2 and S3 for preparing a plurality of layers of redistribution traces to obtain a second portion 202 of the interposer; s5: forming a seed conductive layer on the second portion 202 and coating a photoresist; s6: photoetching the light resistance to form a conducting channel; s7: electroplating the conduction channel to form a conductive metal column for leading out a chip pin; s8: removing the photoresist and etching to remove the redundant part of the seed conducting layer; s9: carrying out die pressing on the etched conductive metal column by using an organic material for wrapping the conductive metal column to obtain a first part 201 of the intermediate layer, wherein the thermal expansion coefficient of the first part 201 is smaller than that of the second part 202, and carrying out multiple die pressing by using die materials with different thermal expansion coefficients for adjusting the thermal expansion coefficient of the first part 201; s10: the carrier 203 is removed to form the interposer.
The method further comprises the following steps: operations S6-S7 are repeated for increasing the height of the conductive metal pillar before step S9. The material of the carrier plate 203 is silicon or glass; the electroplating material is copper; the conductive metal column is a copper column. The seed conducting layer is a metal with adhesiveness or conductivity; the dielectric layer is made of an organic photosensitive material or a low dielectric coefficient material, the organic photosensitive material is at least one of polyimide and cyclobutene resin, and the low dielectric coefficient material comprises at least one of silicon oxide and silicon oxynitride. The stripping glue is a temporary bonding glue, and the stripping mode is light stripping and/or heating stripping.
Fig. 4 is a schematic view illustrating a method for manufacturing an interposer for chip packaging according to the present invention, and as shown in fig. 4, step S201 is to add a release liner to one side of a carrier 203. The material of the carrier 203 is preferably silicon or glass. The release adhesive is preferably a temporary bonding adhesive, which is a peelable adhesive used for bonding the carrier plate 203 and materials in subsequent steps. The present invention preferably uses spin coating, spray coating, or at least one of the adhesive films is coated with a peelable adhesive on one side of the carrier 203, and the adhesive bond may fail and be peeled off at high temperature or under laser.
Step S202 is to prepare redistribution wires on the stripper rubber, including: and sequentially forming a first seed conductive layer and a dielectric layer on the stripping glue, wherein the dielectric layer is provided with a circuit pattern and is an organic dielectric layer. The Redistribution lead is arranged on a Redistribution Layer (RDL Redistribution Layer), and the Redistribution lead Layer is used for realizing the electrical connection among all parts of the package and mainly belongs to metal and high polymer dielectric materials.
According to a preferred embodiment, a seed conductive layer is physically deposited on the release liner, and a dielectric layer is coated or deposited, wherein the seed conductive layer can be a metal with good adhesion (such as titanium) or a conductive metal (such as copper), and the material of the dielectric layer can be an organic photosensitive material (such as polyimide and cyclobutene resin), or other materials with low dielectric coefficient and good dielectric properties. The dielectric layer is an organic intermediate layer, the circuit pattern arranged on the dielectric layer is determined by circuit design, and the preparation process of the dielectric layer is preferably a photoetching process.
Step S203 is to fill the electroplating material into the gap of the dielectric layer to form a conductive connection layer. The voids are voids in the circuit pattern. According to a preferred embodiment, the electrically conductive connection layer of the circuit is produced using said plating material, preferably copper. In the electroplating process, if the surface of the electroplating material has overlarge undulation, the undulation can be removed by carrying out chemical mechanical polishing on the electroplating material, so that the precision of the next step of photoetching is improved.
Step S204 is to repeat S203 and S203, and then remove the excess seed conductive layer by an etching process for preparing a multi-layer redistribution conductive line, so as to obtain the second part 202 of the interposer.
Step S205 is to form a new seed conductive layer on the second portion 202, so that the seed conductive layer is plated on one surface of the second portion 202, and is coated with a photoresist to prepare for manufacturing a higher metal pillar (copper pillar). According to a preferred embodiment, the seed conductive layer is formed by deposition plating. The photoresist, also known as photoresist, is a photosensitive material used in many industrial processes, such as photolithography, to pattern a coating on the surface of the material.
Step S206 is to perform photolithography on the photoresist to fabricate a pattern to be plated for forming a conduction channel.
Step S207, electroplating the conduction channel to form a conductive metal column, and filling a photoetching pattern through the conductive metal column for leading out a chip pin; operations S206-S207 may also be repeated for increasing the height of the conductive metal pillar.
Step S208 is to remove the photoresist and perform etching to remove the excess portion of the seed conductive layer.
Step S209 is to perform a die pressing on the etched conductive metal pillar by using an organic material, so as to wrap the conductive metal pillar, thereby obtaining the first portion 201 of the interposer, where a die of the die is formed between the dielectric and the conductive metal pillar.
In step S210, the carrier 203 is removed to form an interposer. Preferably, the excess molding compound is removed by grinding to expose the conductive metal pillar, and after the solder ball is implanted on the conductive metal pillar, the conductive metal pillar is connected to the substrate through the solder ball. The carrier plate 203 can be removed by thermal decomposition bonding stripping or laser decomposition bonding stripping according to the material and process requirements.
The manufacturing method of the interposer utilizes the organic composite material to manufacture the interposer, so that the design of the metal through hole is not limited by the punching technology; the organic composite material comprises more material types, so that the material which is relatively close to the thermal expansion coefficient of the chip is easy to find to reduce the stress of the chip; and the manufacturing method can utilize the panel manufacturing process, thereby greatly reducing the manufacturing cost.
In another aspect, the present invention further provides a method for fabricating an interposer for chip packaging, the method comprising: s1: adding a stripping glue to one side of the carrier plate 203; s2: preparing redistribution wires on the lift-off glue, comprising: sequentially forming a first seed conductive layer and an organic dielectric layer on the stripping glue, wherein the dielectric layer is provided with a circuit pattern; s3: filling electroplating materials into the gaps of the dielectric layer to form a conductive connecting layer; s4: repeating S2 and S3 for preparing a plurality of layers of redistribution traces to obtain a second portion 202 of the interposer; s5: routing the redistribution wires on the periphery of the second part 202 to obtain a conductive metal column; s6: the conductive metal posts are compression molded with an organic material for wrapping the conductive metal posts to obtain the first portion 201 of the interposer, wherein the carrier plate 203 is removed at any step after step S4 or step S6. The method is suitable for products with lower performance requirements and lower cost requirements, and is suitable for chip packaging with low linear density.
The interposer for chip packaging of the invention comprises a first part 201 and a second part 202, wherein the first part 201 is positioned at the periphery of the second part 202; the coefficient of thermal expansion of the first portion 201 is less than the coefficient of thermal expansion of the second portion 202. The interposer is filled with different fillers, and the proportion of copper in different layers is adjusted to reduce the warpage of the interposer; the lower surface adopts lower filling and copper distribution, and the upper surface adopts higher filling and copper distribution, and the filling and copper distribution can be gradually changed, so that the intermediate layer is relatively flat, the subsequent process is easy to package, and the yield is relatively high.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (12)
1. An interposer for chip packaging, wherein a material of the interposer comprises an organic material;
the interposer includes a first portion and a second portion, the first portion being located at a perimeter of the second portion;
the coefficient of thermal expansion of the first portion is less than the coefficient of thermal expansion of the second portion,
the intermediate layer is provided with metal through holes;
the filler is arranged on the outer side of the through hole of the intermediate layer and is inorganic oxide;
the proportion range of the fillers is as follows: 0% -75%, the proportion of the filler is proportional to the distance of the first part far away from the second part.
2. The interposer of claim 1,
the first portion has a coefficient of thermal expansion in the range of 10 x 10 -6 -30×10 -6 Degree/degree;
the coefficient of thermal expansion of the second portion is in the range of 16 x 10 -6 -50×10 -6 Degree/deg.
3. The interposer of claim 1,
the metal is copper; the filler is silicon oxide; the organic material is at least one of polyimide and cyclobutene resin.
4. The interposer of claim 1,
a conductive metal column is arranged in the through hole and used for connecting multiple chips;
the size of the perforations is 20-100 microns.
5. The interposer of claim 1,
the second part is a plate-shaped body;
the first part is a rectangular frame structure, and the rectangular frame structure is positioned on the periphery of the first surface of the plate-shaped body;
the cross-sectional area of the rectangular frame structure is smaller than the area of the first surface.
6. The interposer of claim 5,
the rectangular frame structure at least comprises a hollow rectangular frame.
7. The interposer of claim 1 or 5,
the thickness of the first portion is 100-200 microns;
the thickness of the second portion is 100-200 microns.
8. A method for fabricating an interposer for chip packaging, the method comprising:
s1: adding a stripping glue to one side of the carrier plate;
s2: preparing redistribution wires on the lift-off glue, comprising: sequentially forming a first seed conductive layer and a dielectric layer on the stripping glue, wherein the dielectric layer is provided with a circuit pattern;
s3: filling electroplating materials into the gaps of the dielectric layer to form a conductive connecting layer;
s4: repeating S2 and S3 for preparing a plurality of layers of redistribution wires to obtain a second part of the interposer;
s5: forming a seed conductive layer on the second part and coating a light resistance;
s6: photoetching the light resistance to form a conducting channel;
s7: electroplating the conducting channel to form a conducting metal column for leading out a chip pin;
s8: removing the photoresist and etching to remove the redundant part of the seed conducting layer;
s9: carrying out die pressing on the etched conductive metal column by using an organic material for wrapping the conductive metal column to obtain a first part of an intermediate layer, wherein the coefficient of thermal expansion of the first part is smaller than that of the second part, and carrying out multiple die pressing by using die materials with different coefficients of thermal expansion for adjusting the coefficient of thermal expansion of the first part;
s10: and removing the carrier plate to form the intermediate layer.
9. The method of manufacturing of claim 8, further comprising:
operations S6-S7 are repeated for increasing the height of the conductive metal pillar before step S9.
10. The method of manufacturing according to claim 8,
the carrier plate is made of silicon or glass;
the electroplating material is copper;
the conductive metal column is a copper column.
11. The method of manufacturing according to claim 8,
the seed conducting layer is a metal with adhesiveness or conductivity;
the dielectric layer is made of organic photosensitive materials or low-dielectric-coefficient materials, the organic photosensitive materials are at least one of polyimide and cyclobutene resin, and the low-dielectric-coefficient materials comprise at least one of silicon oxide and silicon oxynitride.
12. The method of manufacturing according to claim 8,
the stripping glue is temporary bonding glue, and the stripping mode is light stripping and/or heating stripping.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047652A (en) * | 2015-09-01 | 2015-11-11 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor device packaging structure and manufacturing method thereof |
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| CN107195594A (en) * | 2016-03-14 | 2017-09-22 | 美光科技公司 | The semiconductor packages and its manufacture method of redistribution layer intermediary layer are protected with side wall |
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