CN114743945A

CN114743945A - Advanced package structure with Si and organic interposer and method of making the same

Info

Publication number: CN114743945A
Application number: CN202210238998.3A
Authority: CN
Inventors: 方立志
Original assignee: Espoo International Co ltd
Current assignee: Espoo International Co ltd
Priority date: 2022-03-11
Filing date: 2022-03-11
Publication date: 2022-07-12

Abstract

The invention discloses an advanced packaging structure with Si and an organic intermediate layer and a manufacturing method thereof. The advanced packaging structure simultaneously uses the three mediums with different wiring densities, and can provide a processor, logic and a multi-chip to be integrated in the advanced packaging structure, 1 to 6 chips can be put into the packaging body, and the more chips are, the better the operation efficiency of the processor is.

Description

Advanced packaging structure with Si and organic interposer and method of making the same

Technical Field

The invention belongs to the field of semiconductor packaging, and particularly relates to an advanced packaging structure with Si and an organic intermediate layer and a manufacturing method thereof.

Background

With the demand for higher memory bandwidth for various applications such as Artificial Intelligence (AI), data centers, High Performance Computing (HPC), networks, and graphics acceleration display cards, advanced packaging becomes an increasingly important factor for supporting High Bandwidth Memory (HBM) wide I/O. Currently, there are three major advanced packaging technologies used in the industry, CoWOS (chip on Wafer on substrate) for station integrated circuit TSMC, EMIB (Embedded Multi-Die Interconnect Bridge) for Intel, and H-Cube of Samsung, three stars.

CoWOS of the Taiwan accumulation TSMC: in a typical 2.5D package, a chip of a Processor, a logic and an HBM is mounted on a Si interposer, a plurality of redistribution layers (RDLs) are provided on the Si interposer, and the line width and line pitch of the distribution layer wiring is less than 1.2 micrometers (um). Such fine routing can provide high and medium density signal connections between chips, which cannot be provided by FCBGA substrates (or carriers), and medium and low density signal connections. The Si interposer is mounted on the FCBGA substrate, and has Through Silicon Vias (TSVs) for conducting signals from the upper layer to the lower layer, and then conducting signals with the FCBGA substrate. The fabrication of the Si interposer wafer is completed by the foundry, and because of the limitations of the mask (reticle) and the exposure process equipment, it is difficult to make the Si interposer large enough to hold many chips, and the cost is high and is a problem to be solved by cowoes.

EMIB by Intel: intel's approach is to reduce the size of expensive Si interposers, which do not have TSVs (through silicon vias) to route signals from the upper layer to the lower layer, because the signals are only transmitted in the RDLs on the surface of the Si interposer, and there are no TSVs that would potentially degrade the performance of the chip.

A single or a plurality of Si intermediate layers are embedded in an FCBGA substrate, wiring needing high-density and medium-density signal connection is designed on the Si intermediate layer, wiring of low-density signal connection is designed on the FCBGA substrate, although the size of the Si intermediate layer is reduced, the cost is reduced, the wiring of medium-density signal connection (the line width and the line distance is between 8um and 1.5 um) cannot be designed on the FCBGA substrate, silicon dioxide filler (silicon filler) is arranged in an ABF material, a blind hole (blind via hole) cannot be drilled in an etching (etching) mode, a laser is used for drilling the blind hole (blind via hole), the size is limited, a hole which is too small cannot be drilled, the size and the distance between a joint of the substrate and a chip cannot be reduced, the sizes of the Si intermediate layer and the chip cannot be further reduced, and the cost cannot be reduced.

The current pitch of the contacts for the chip to the Si interposer is 55um, and the pitch of the contacts for the chip to the FCBGA substrate is 130 um.

H-Cube of Samsung, H-Cube, Samsung, H-Cube, Samsung, H-Cube, Samsung, H-Cube, Samsung, H-Cube, Samsung, H-Cube, Samsung, H-Cube, Samsung, H-Cube, Samsung, H-Cube, Samsung, Samsbeing: basically similar to CoWOS of the mesa-integrated TSMC, the chip is mounted on a large Si interposer, which is in turn mounted on a fine pitch (fine pitch) substrate, and then on a High Density Interconnect (HDI) substrate. Because of the use of a large Si interposer and two substrates, the Si interposer is difficult to make large enough and costly, as is the case with CoWoS.

Thus, current practice is not that Si interposers are large in size (since all high, medium, and low density wiring is on top), making them too expensive. The Si interposer is reduced in size, high-density and medium-density wirings are arranged on the Si interposer, the FCBGA substrate can only be designed with low-density wirings (the line width and the line distance are larger than 8um), the Si interposer cannot be further reduced in size, and even more chips can be mounted, the Si interposer is increased in size, and the cost cannot be further reduced.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the present invention provides an advanced package structure with Si and organic interposer and a method for manufacturing the same, which has low cost and high input/output density, and is helpful for integrating more HBMs and processor chips (or logic chips) to improve the performance of the operation.

The technical scheme adopted by the invention is as follows:

an advanced packaging structure with Si and an organic intermediate layer comprises a substrate with low-density wiring, a Si intermediate layer with high-density RDL wiring and an organic dielectric layer with medium-density RDL wiring, wherein the Si intermediate layer is embedded in the surface of the substrate, and the organic dielectric layer is packaged on the surfaces of the Si intermediate layer and the substrate by adopting a fan-out panel level and is electrically connected with the substrate and the Si intermediate layer; the line width and line distance of the low-density wiring is larger than that of the medium-density RDL wiring, and the line width and line distance of the medium-density RDL wiring is larger than that of the high-density RDL wiring.

Optionally, the substrate is an FCBGA substrate, and includes a core layer and a plurality of build-up circuit layers stacked on the surfaces of two sides of the core layer in a pressed manner, and each build-up circuit layer and the core layer are electrically connected through laser drilling and in-hole metallization.

Optionally, a line width and a line distance of the low-density wiring are greater than 8 μm, a line width and a line distance of the medium-density RDL wiring are between 8 μm and 1.5 μm, and a line width and a line distance of the high-density RDL wiring are less than 1.5 μm.

Optionally, the organic dielectric layer comprises a plurality of layers of polyimide and a plurality of layers of middle-density RDL wiring which are stacked alternately, and the middle-density RDL wiring is electrically connected with each other by etching the polyimide among the holes and metal plating in the holes.

Optionally, the Si interposer and the organic dielectric layer are disposed on the upper surface of the substrate, the lower surface of the substrate is provided with a solder ball pad, and the upper surface contact of the organic dielectric layer is provided with a solder-copper bump.

Optionally, the line width and line pitch of the medium density RDL routing decreases with decreasing distance from the location where the memory chip is to be mounted.

Optionally, a cavity is formed on the upper surface of the substrate at a position corresponding to the Si interposer, and a gap between the Si interposer and the cavity is filled with resin.

Optionally, the surface contact of the Si interposer is provided with a metal bump, and when the Si interposer is embedded in the substrate, the metal bump is coplanar with the surface contact of the substrate.

A method of manufacturing an advanced package structure with Si and an organic interposer as described above, the method of manufacturing comprising:

manufacturing a Si intermediate layer of the high-density RDL wiring;

manufacturing a substrate with low-density wiring, and forming a cavity on the upper surface of the substrate corresponding to the position of the Si intermediate layer;

embedding the Si interposer in the cavity;

adhering the lower surface of the substrate embedded with the Si interposer on a carrier, and manufacturing a plurality of organic dielectric layers of medium-density RDL (radio frequency identification) wiring on the upper surface by adopting fan-out panel-level packaging so that the RDL wiring of the organic dielectric layers is electrically connected with the Si interposer and the substrate;

manufacturing tin-copper bumps on the upper surface joints of the Si interposer;

and removing the carrier and cutting into single pieces.

Optionally, the substrate is an FCBGA substrate, and the step of manufacturing the FCBGA substrate includes:

manufacturing a substrate core layer, and conducting circuits on the surfaces of two sides of the core layer by opening through holes on the core layer and plating metal;

and laminating and stacking a plurality of layer-adding circuit layers on the surfaces of the two sides of the core layer respectively, wherein the layer-adding circuit layers and the core layer are electrically connected through laser drilling and in-hole metal plating.

Optionally, a metal bump is disposed at a joint on the upper surface of the Si interposer, after the Si interposer is embedded in the cavity, resin is filled between the Si interposer and the cavity, a build-up circuit layer is continuously laminated on the upper surfaces of the Si interposer and the substrate, and a height of a metal plated portion in the laser opening between the build-up circuit layer is consistent with a height of the metal bump.

Optionally, before the fabrication of the organic dielectric layer on the upper surface of the substrate by adopting fan-out panel-level package, the method further includes:

and grinding the substrate and the build-up circuit layer on the upper surface of the Si intermediate layer until the metal plated part in the laser opening between the metal convex body and the build-up circuit layer is exposed, and the designed thickness and flatness are achieved.

Optionally, the step of fabricating the organic dielectric layer includes: and alternately stacking a plurality of layers of polyimide and a plurality of layers of medium-density RDL (radio frequency identification) wirings on the upper surfaces of the substrate and the Si intermediate layer, wherein the medium-density RDL wirings are electrically connected through etching the polyimide among the holes and the plated metal in the holes.

Optionally, after the last organic dielectric layer is manufactured, blind holes are opened on the polyimide by exposure, development and etching, and the tin-copper bump electrically connected with the medium-density RDL wiring is manufactured.

Optionally, the manufacturing method further comprises the steps of:

inversely installing a processor, logic and a plurality of high-bandwidth memory chips on the Si intermediate layer cut into the single substrate upper surface, and welding a plurality of tin-copper bumps on the chips and the tin-copper bumps on the Si intermediate layer upper surface for electrical conduction;

filling the bottom of the gap between the chip and the Si intermediate layer, and attaching a heat sink, wherein the heat sink and the back surface of the chip are provided with thermal interface materials to assist in heat conduction;

and manufacturing a tin ball pad on the lower surface of the substrate.

Due to the adoption of the technical scheme, the invention has the following beneficial effects:

the advanced packaging structure with the Si and the organic medium layer provides high-density RDL wiring, the organic dielectric layer of the fan-out panel level packaging process provides medium-density RDL wiring, the substrate of the FCBGA provides low-density wiring, the advanced packaging structure simultaneously uses the three mediums with different wiring densities, a Processor (Processor), a logic (logic) and a High Bandwidth Memory (HBM) can be integrated in the advanced packaging structure, the HBMs can be placed in the packaging body from 1 to 6, and the higher the number of the HBMs, the better the operation efficiency of the Processor.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 to 5 are schematic structural diagrams of steps of an FCBGA substrate processing process according to an embodiment of the invention.

FIG. 6 is a schematic structural diagram of a process for fabricating an embedded Si interposer on an FCBGA substrate in accordance with one embodiment of the present invention.

Fig. 7-11 are schematic structural diagrams illustrating steps of a process for fabricating an organic dielectric layer on an FCBGA substrate according to an embodiment of the present invention.

The corresponding relation of the reference numbers is as follows:

1-FCBGA substrate; 11-a core layer; 111-a via; 112-copper foil; 12-a build-up circuit layer; 121-ABF build-up membrane; 122-copper wire; 123-blind hole; 124-electroplating copper; 13-a cavity; a 2-Si interposer; 21-copper bumps or pillars; 22-DAF mucosa; 23-a resin; 3-an organic dielectric layer; 31-Polyimide (PI); 32-medium density RDL routing; 33-photoresist or photoresist film; 4-tin-copper bumps; 5-solder ball pad; 6-a glass carrier; 7-gluing; 8-Processor (Processor); 9-high bandwidth inner chip (HBM); 10-underfill.

Detailed Description

The following further describes embodiments of the present invention with reference to the drawings. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

First, the explanation is made for technical terms appearing in the text as follows:

RDL: the Redistribution Layer comprises copper connecting lines or routing lines for realizing the electrical connection among all parts of the package, and is a metal or high-molecular dielectric material Layer, and the bare chips can be stacked in the package so as to reduce the I/O (input/output) distance of the chipset; RDL has become an integral part of 2.5D and 3D packaging solutions, allowing chips thereon to communicate with each other through an interposer;

DAF: die Attach Film, the purpose is that when laser cutting, the chips can be cut and separated together for stripping, so that the chips after cutting can be adhered on the Film without scattered arrangement caused by cutting;

FCBGA (Flip Chip Ball Grid array): the packaging format of the ball grid array of the flip chip is also the most main packaging format of the graphic acceleration chip;

adding a layer: the method is a processing technology for forming a film on the surface of a wafer;

ABF: compared with BT base materials, the ABF material can be used for manufacturing ICs with thin lines, high pin count and high transmission, and is mainly used for large-scale high-end chips such as CPU, GPU, Chip sets and the like; the ABF is used as a layer-adding material, and the ABF is directly attached to the copper foil substrate to be used as a circuit, so that a hot-pressing process is not needed;

HBM: high Bandwidth Memory chip;

PI: polyimide, a polymer containing imide rings (-CO-N-CO-) in the main chain, is one of the best organic polymer materials with the best comprehensive properties. The high-temperature-resistant insulating material has high temperature resistance of more than 400 ℃, a long-term use temperature range of-200-300 ℃, no obvious melting point at part, high insulating property, dielectric constant of 4.0 at 103 Hz and dielectric loss of only 0.004-0.007, and belongs to F-H grade insulation.

At present, three major types of packages for efficient operation combined with processors and HBM chips are available, namely cofos of TSMC, EMIB of Intel, and schemes proposed by some companies to integrate CPU and HBM chips in FO packages and then package the FO in FCBGA. Where CoWOS can provide the best high input/output density solution, but at a high cost. The other two solutions, although less costly, can provide a lower density of inputs/outputs. The invention has low cost and high input/output density, and is helpful to integrate more HBMs to improve the operation efficiency.

Specifically, refer to fig. 1 to 11, wherein fig. 1 to 5 are schematic structural diagrams of steps of an FCBGA substrate processing process according to an embodiment of the present invention; FIG. 6 is a schematic structural diagram of an FCBGA substrate embedded Si interposer process according to an embodiment of the present invention; fig. 7-11 are schematic structural diagrams illustrating steps of a process for fabricating an organic dielectric layer on an FCBGA substrate according to an embodiment of the present invention.

The advanced packaging structure with the Si and the organic interposer provided by the embodiments of the present invention mainly utilizes interposers of different materials to show widths and pitches of different lines, so as to support interconnection of signals between high Input/Output (I/O) density chips.

The advanced packaging structure with the Si and the organic intermediate layer mainly comprises a substrate 1 with low-density wiring, a Si intermediate layer 2 with high-density RDL wiring and an organic dielectric layer 3 with medium-density RDL wiring, wherein the Si intermediate layer 2 is embedded in the surface of the substrate 1, and the organic dielectric layer 3 is packaged on the surfaces of the Si intermediate layer 2 and the substrate 1 by adopting a fan-out panel level and is electrically connected with the substrate 1 and the Si intermediate layer 2; the line width and line distance of the low-density wiring is larger than that of the medium-density RDL wiring, and the line width and line distance of the medium-density RDL wiring is larger than that of the high-density RDL wiring. Preferably, the line width and line distance of the low-density wiring is larger than 8 μm, the line width and line distance of the medium-density RDL wiring is between 8 μm and 1.5 μm, and the line width and line distance of the high-density RDL wiring is smaller than 1.5 μm.

As shown in fig. 1 to 5, the substrate 1 is preferably an FCBGA substrate, and includes a core layer 11 and a plurality of build-up circuit layers 12 stacked on two side surfaces of the core layer 11 in a pressing manner, and the build-up circuit layers 12 and the core layer 11 are electrically connected through laser openings and in-hole metallization.

As shown in fig. 1, the core layer 11 of the FCBGA substrate 1 has several layers, the main three layers are intermediate layers made of glass fiber and resin, and the upper and lower layers of the intermediate layers are copper foils 112. A through hole 111 is formed in a substrate of a core layer 11, copper (or other equivalent metal) is plated in the through hole 111, a copper foil 112 outside a circuit part is removed by etching, a circuit is formed, and upper and lower layers of circuits are conducted through the through hole 111 and the copper plated in the hole.

The upper and lower surfaces of the core layer 11 are respectively pressed with a plurality of build-up circuit layers 12, and the build-up circuit layers 12 on the two surfaces of the core layer 11 are electrically conducted through the through holes 111 and the copper plated holes. Each build-up circuit layer 12 further includes an ABF build-up film 121 and a circuit formed by copper wires 122 (or other equivalent metal wires) formed on the surface of the ABF build-up film 121. Specifically, an ABF (Ajinomoto Build-up Film) or the like is laminated on both sides of the core layer 11 by a Build-up process (or called Build-up process), and the circuit pattern is exposed and directly formed into a copper wiring circuit by a copper plating process by development, etching and plating. The process is repeated many times to proceed stacking and layer-adding (laminating), there is blind via 123(blind via hole) for electrical connection between each layer of copper wires 122, the blind via 123 is drilled by laser, the size is limited, too small hole can not be drilled, the blind via 123 is filled with electroplated copper 124 (or other equivalent metal). The lamination process is repeated several times to the required number of layers, as shown in fig. 2 to 4.

The cavity 13 is opened in the ABF build-up film 121 of the last build-up wiring layer 12 on the top surface of the FCBGA substrate 1 for placing the Si interposer 2, and as shown in fig. 5 and 6, the resin 23 is filled in the gap between the Si interposer 2 and the cavity 13. The Si interposer 2 is provided with high-density RDL wiring, and the upper surface contact position of the Si interposer 2 is provided with copper bumps or copper pillars 21 (or other equivalent metal bumps), when the Si interposer 2 is embedded in the cavity 13 on the upper surface of the FCBGA substrate 1, the copper bumps or copper pillars 21 are upward and coplanar with the surface contact of the FCBGA substrate 1, as shown in fig. 7, after the Si interposer 2 is embedded in the FCBGA substrate 1, the build-up circuit layer 12 is continuously pressed on the upper surface of the FCBGA substrate 1, and the height of the electroplated copper 124 in the laser opening between the build-up circuit layers 12 is consistent with the height of the copper bumps or copper pillars 21.

As shown in fig. 8 to 10, the organic dielectric layer 3 includes a plurality of polyimide layers 31 and a plurality of middle-density RDL wirings 32 stacked alternately, the middle-density RDL wirings 32 in each layer are electrically connected by etching the polyimide 31 between the openings and electroplating copper (or other equivalent metal) in the openings, the middle-density RDL wirings 32 and the polyimide 31 in the organic dielectric layer 3 are fabricated on the FCBGA substrate 1 and the Si interposer 2 by fan-out panel-level packaging, and the middle-density RDL wirings 32 electrically connect the low-density wirings on the FCBGA substrate 1 and the high-medium-density RDL wirings on the Si interposer 2. The Si interposer 2 and the organic dielectric layer 3 are disposed on the upper surface of the FCBGA substrate 1, the lower surface of the FCBGA substrate 1 is provided with solder ball pads 5, and as shown in fig. 11, the upper surface contacts of the organic dielectric layer 3 are provided with solder bumps 4. The tin-copper bump 4 can be used for soldering the tin-copper bump on the memory chip 9, and the line width and line pitch of the medium-density RDL wiring 32 in the organic dielectric layer 3 are finer, even 1.5 μm to 2.0 μm, at a position approximately close to the memory chip 8.

The reduced size of the Si interposer embedded in the FCBGA can reduce the cost, the packaging process is relatively simple, and the packaging cost is relatively low. However, since high and medium density wiring is on top of the Si interposer, the Si interposer cannot be further scaled down, and the Si interposer will be larger when scaling up to even more chips.

The invention can design medium-density wiring (the RDL line width and line distance is between 10 and 1.5 microns) by removing the medium-density wiring from the Si intermediate layer and placing the medium-density wiring on the polyimide organic dielectric layer, and has lower cost.

Throughout the entire electronic and semiconductor supply chain, the process of the wafer factory mainly processes the line width and line distance from 1 micrometer (um) to 3 nanometers (nm), the process of the printed circuit board processes the line width and line distance above several millimeters (mm), the process of the packaging factory processes the line width and line distance from several millimeters (mm) to several micrometers (um), the process of the substrate used by the packaging factory processes the line width and line distance from 8 micrometers (um) to several hundred micrometers, the bump of the packaging factory, and the fan-in/fan-out packaging process can process the line width and line distance from dozens of micrometers to 1 micrometer, so that the bottleneck encountered by the current advanced packaging can be solved.

The difference between the FI-WLP (fan in wafer level package) and the fan-out wafer level package (FO-WLP) is mainly: the solder balls fanned into the package are within the range of the chip, and the solder balls fanned out of the package are outside the range of the chip.

The fan-out wafer level packaging process in a packaging fab (or some fabs) pulls the required circuits from the terminals (PAD) of the semiconductor die to the Redistribution Layer (Redistribution Layer) to form the package. Therefore, a package substrate, a Wire bonding (Wire) and a Bump (Bump) are not required, the production cost can be reduced, and the chip and the package can be thinner. To form the redistribution layer, the front end process is required to be introduced into the package, which greatly increases the process capability of the packaging factory, from several millimeters to several micrometers.

Wafer level packaging is based on wafer level processes, which are performed on one or more wafers.

The FOWLP process is divided into two categories:

chip priority FO: the wafer level carrier (carrier) is placed with a perfect wafer (KGD) picked from the original device wafer, and is covered with molding resin to form a reconstituted wafer (re-registration wafer), which is further processed into RDL, ball-planting, carrier removal, and singulation on the wafer.

RDL priority FO: the wafer level carrier builds a RDL layer and temporarily bonds, places the KGD on top and then mold resin wraps (molding), grinds, removes the carrier, plants the balls, and singulates.

Under these two process architectures, various changes, such as die-up bonding, die-down bonding, RDL thin line first, and RDL thick line first, can be extended according to different requirements of customers. The RDL linewidth spacing capability of FOWLP can be as small as 1.5 microns.

FOWLP is more suitable for chip size less than 5mm²If the chip is large, the wafer level is arc-shaped, which wastes a lot of wafer space. The solution is to use fan-out package FOPLP (fan out panel level package) and panel level process to save space, increase the output of unit and greatly reduce the cost.

The process capability at the panel level can be the same as that at the wafer level, and if the working area of the wafer level equipment is enlarged, it is of course necessary to develop appropriate materials and process equipment together with the materials and equipment vendors to achieve the same process capability, and the RDL line width line spacing capability can be as small as 1.5 μm.

By using newly developed materials and equipment, the line width and line distance of RDL (radio frequency identification) process of fan-out panel level packaging can be as small as 1.5 micrometers, which just meets the requirement of medium-density wiring (the line width and line distance capability of RDL is between 10 and 1.5 micrometers), so that the intermediate layer with medium wiring density can be manufactured by the process of fan-out panel level packaging.

The Si intermediate layer provides high RDL wiring density, the organic dielectric layer of the fan-out panel level packaging process provides medium-density RDL wiring, the FCBGA substrate provides low-density wiring, advanced packaging can provide integration of a Processor, a logic and HBM multiple chips in the advanced packaging if three mediums with different wiring densities are used simultaneously, the HBMs can be placed into the packaging body from 1 to 6, and the larger the number of HBMs is, the better the operation efficiency of the Processor is.

The scheme provided by the invention is that a Si intermediate layer of high-density RDL wiring is embedded in an FCBGA substrate of low-density wiring, the work can be completed in a substrate factory, the process of the substrate factory is a panel level, so that the substrate factory is not cut into single pieces, and then the single pieces are sent to a place with a fan-out panel level packaging process (the RDL line width and line distance capability is as small as 1.5 microns), a plurality of layers of organic dielectric layers of RDL (medium-density wiring) are made on the surface of the substrate, and a copper-tin bump is arranged at the top to be used as the electrical connection of a chip to be mounted later. Finally, the FCBGA is cut into single pieces and delivered to a packaging factory for subsequent FCBGA manufacturing processes.

Referring to fig. 1 to 11, a method for manufacturing an advanced package structure with Si and an organic interposer according to an embodiment of the present invention includes:

step 1: and manufacturing a Si interposer with high-density RDL wiring, wherein the high-density RDL wiring is arranged on the Si interposer 2, and a copper bump or copper pillar 21 (or other equivalent metal convex bodies) is arranged at the contact position on the upper surface of the Si interposer 2, and the copper bump or copper pillar 21 is electrically connected with the high-density RDL wiring.

Step 2: an FCBGA substrate 1 with low-density wiring is fabricated, and a cavity 13 is opened in the upper surface of the FCBGA substrate 1 corresponding to the position of the Si interposer 2.

Specifically, the step of manufacturing the FCBGA substrate 1 further includes:

manufacturing a substrate core layer 11, and forming a circuit by etching through holes 111 on the core layer 11 and plating copper (or other equivalent metals) to connect copper foils 122 on two side surfaces of the core layer 11, as shown in fig. 1;

a plurality of build-up circuit layers 12 are respectively stacked on the two side surfaces of the core layer 11 in a pressing manner, and each build-up circuit layer 12 and the core layer 11 are electrically conducted through the laser blind hole 123 and the electroplated copper 124 (or other equivalent metals) filled in the blind hole 123.

More specifically, the build-up wiring layer 12 is formed by a build-up process (or build-up process). An ABF (Ajinomoto Build-up Film) Build-up Film 121 or the like is pressed on both sides of the core layer, and a circuit pattern is exposed and directly formed (i.e., a circuit formed of copper wires 122) by copper plating. The process is repeated many times to build up layers (build up layers), there are blind vias 123(blind via hole) between each layer of copper wires 122 for electrical connection, the blind vias 123 are drilled by laser, the size is limited, too small holes cannot be drilled. The lamination process is repeated several times to a desired number of layers, as shown in fig. 2 to 4.

And 3, step 3: a cavity is dug in the upper surface of the FCBGA substrate 1 at the position where the Si interposer 2 (having a plurality of RDL lines with a width less than 1.5 μm) is to be placed, a copper bump or copper pillar 21 is connected to the upper surface of the Si interposer 2, the copper bump or copper pillar 21 of the Si interposer 2 faces upward, the bottom of the Si interposer 2 is fixed in the cavity 13, a resin 23 is filled in the gap between the Si interposer 2 and the cavity 13, then the ABF build-up film 121 is pressed to cover the Si interposer 2 (having the copper bump or copper pillar 21 on the upper surface) and the copper wire 122 on the substrate 1, a blind hole 123(blind via hole) is opened in the substrate 1 by a laser, and the blind hole 123 is filled with electroplated copper 124 (or other equivalent metal) and has a height consistent with that of the copper bump or copper pillar 21 on the upper surface of the Si interposer 2, as shown in fig. 5 to 7.

And 4, step 4: after the build-up step, an outer layer step is performed to clean and inspect the appearance and electrical characteristics, thereby completing the FCBGA substrate 1.

And 5, step 5: the panel of the substrate 1 is sent to a production line of fan-out panel level packaging, and the surface topography of the substrate panel prepared by the substrate factory is uneven, which has adverse effects (disconnection, short circuit, etc.) on the formation of the fine lines later. After the panel is cleaned, the lower surface is adhered to the glass carrier 6 by the adhesive 7, the upper surface is the ABF build-up membrane 121 (a plurality of blind holes 123 are formed thereon, the blind holes 123 are filled with the electroplated copper 124, the surface of the ABF build-up membrane 121 is ground by mechanical grinding or Chemical Mechanical Polishing (CMP), and the copper bumps or copper pillars 21 on the upper surface of the Si interposer 2 and the electroplated copper 124 filled in the blind holes 123 are exposed to achieve the designed thickness and flatness.

And 6, step 6: after polishing, the substrate 1 panel is cleaned, a plurality of middle-density RDL wirings 32 and a plurality of dielectric layers (polyimide or equivalent material) are formed on the flat surface, the polyimide 31 between the middle-density RDL wirings 32 and the layers is provided with blind via holes (blind via hole), the blind holes are provided with holes by etching, and the electroplating buried holes are used for electric connection between the copper wires of each layer. The closer to the medium-density RDL wiring 32 of the chip, the finer the line width and the line distance, even 1.5-2.0 microns, so the surface appearance of the dielectric layer can be made as flat as possible by controlling the thicknesses of the medium-density RDL wiring 32 layer and the dielectric layer, selecting the material of the dielectric layer and optimizing the manufacturing method of the manufacturing process, and the copper wire of the patterned RDL can meet the requirement of thinning. As shown in FIGS. 8 to 10.

And 7, step 7: after the final layer of middle density RDL wiring 32 and polyimide 31 is made, the polyimide 31 is etched by exposure, development and etching, and the size and the pitch of the holes can be reduced, so that the tin-copper bumps 4 are formed at the contact portions of the mounted chip (bare chip). The panel is cut into a plurality of single FCBGA substrates, the appearance and electrical characteristics are checked, and the FCBGA substrates are shipped to a packaging factory for further subsequent processing. The polyimide 31 is etched to have smaller size and pitch than those of ABF laser, so that the pitch of the contact connected between the chip and the Si interposer can be reduced to 35-40 um (55 um at present). The size of the chip and the Si interposer may be reduced accordingly. The cost is reduced. As shown in fig. 11.

And 8, step 8: a packaging factory inversely mounts a processor 8(processor), a logic (logic) chip 9 and 1 to 6 High Bandwidth Memory (HBM) chips 9 on the upper surface of the FCBGA substrate 1, a plurality of tin-copper bumps on the chip 9 are electrically connected with the contacts of the plurality of tin-copper bumps 4 on the upper surface of the FCBGA substrate 1 by welding, an underfill 10(underfill) is formed between the chip 9 and the substrate 1, a heat sink is attached, and a Thermal Interface Material (TIM) is arranged on the heat sink and the back surface of the chip to assist heat conduction. Finally, a plurality of solder balls are implanted on the ball pads on the lower surface of the FCBGA substrate 1 to form solder ball pads 5, and the heat sink is stamped to check the appearance and electrical characteristics, thereby completing the packaging process of the FCBGA substrate, as shown in FIG. 11.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present invention.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, and the scope of protection is still within the scope of the invention.

Claims

1. An advanced package structure with Si and organic interposer, comprising: the substrate comprises a substrate with low-density wiring, a Si intermediate layer with high-density RDL wiring and an organic dielectric layer with medium-density RDL wiring, wherein the Si intermediate layer is embedded in the surface of the substrate, and the organic dielectric layer is packaged on the surfaces of the Si intermediate layer and the substrate by adopting a fan-out panel level and is electrically connected with the substrate and the Si intermediate layer;

the line width and line distance of the low-density wiring is larger than that of the medium-density RDL wiring, and the line width and line distance of the medium-density RDL wiring is larger than that of the high-density RDL wiring.

2. The advanced packaging structure with Si and organic interposer as claimed in claim 1, wherein: the substrate is an FCBGA substrate and comprises a core layer and a plurality of layer-adding circuit layers stacked on the surfaces of two sides of the core layer in a pressing mode, and the layer-adding circuit layers and the core layer are electrically connected through laser opening and in-hole metal plating.

3. The advanced packaging structure with Si and organic interposer as claimed in claim 1, wherein: the line width and line distance of the low-density wiring is larger than 8 mu m, the line width and line distance of the medium-density RDL wiring is between 8 mu m and 1.5 mu m, and the line width and line distance of the high-density RDL wiring is smaller than 1.5 mu m.

4. The advanced packaging structure with Si and organic interposer as claimed in claim 1, wherein: the organic dielectric layer comprises a plurality of layers of polyimide and a plurality of layers of medium-density RDL wiring which are alternately stacked, and the layers of the medium-density RDL wiring are electrically connected through etching the polyimide among the holes and metal plating in the holes.

5. The advanced packaging structure with Si and organic interposer as claimed in claim 1, wherein: the Si intermediate layer and the organic dielectric layer are arranged on the upper surface of the substrate, the lower surface of the substrate is provided with a tin ball pad, and the upper surface joint of the organic dielectric layer is provided with a tin-copper bump.

6. The advanced packaging structure with Si and organic interposer as claimed in claim 1, wherein: the line width and line pitch of the medium density RDL wiring decreases as the distance from the location where the memory chip is to be mounted decreases.

7. The advanced packaging structure with Si and organic interposer as claimed in claim 1, wherein: and a cavity is formed on the upper surface of the substrate at a position corresponding to the Si interposer, and resin is filled in a gap between the Si interposer and the cavity.

8. The advanced packaging structure with Si and organic interposer as claimed in claim 1, wherein: the surface contact of the Si intermediary layer is provided with a metal convex body, and when the Si intermediary layer is embedded in the substrate, the metal convex body is coplanar with the surface contact of the substrate.

9. A manufacturing method for manufacturing the advanced packaging structure with Si and organic interposer according to any one of claims 1-8, wherein the manufacturing method comprises:

manufacturing a Si intermediate layer of high-density RDL wiring;

embedding the Si interposer in the cavity;

manufacturing a tin-copper bump on the upper surface joint of the Si intermediate layer;

and removing the carrier and cutting into single pieces.

10. The method of manufacturing of claim 9, wherein the substrate is an FCBGA substrate, the step of fabricating the FCBGA substrate comprising:

and laminating and stacking a plurality of layer-adding circuit layers on the surfaces of the two sides of the core layer respectively, wherein the layer-adding circuit layers and the core layer are electrically connected through laser holes and metal plating in the holes.

11. The method of claim 10, wherein the upper surface contact of the Si interposer is provided with a metal bump, and after the Si interposer is embedded in the cavity, resin is filled between the Si interposer and the cavity, and a build-up wiring layer is sequentially laminated on the Si interposer and the upper surface of the substrate, wherein the height of the metal plated portion in the laser opening of the build-up wiring layer is the same as the height of the metal bump.

12. The method of manufacturing of claim 11, further comprising, prior to fabricating the organic dielectric layer on the substrate upper surface with a fan-out panel-level package, the steps of:

13. The method of manufacturing according to claim 9, wherein the step of fabricating the organic dielectric layer comprises: and alternately stacking a plurality of layers of polyimide and a plurality of layers of medium-density RDL (radio frequency identification) wiring on the upper surfaces of the substrate and the Si intermediate layer, wherein the layers of medium-density RDL wiring are electrically connected through etching the polyimide among the holes and plated metal in the holes.

14. The method as claimed in claim 13, wherein after the final organic dielectric layer is formed, the polyimide is blind-drilled by exposure, development and etching to form the tin-copper bump electrically connected to the medium-density RDL trace.

15. The method of manufacturing according to claim 9, further comprising the steps of:

filling the gap between the chip and the Si intermediate layer with bottom, and attaching a heat sink, wherein the heat sink and the back of the chip are provided with thermal interface materials to assist in heat conduction;

and manufacturing a tin ball pad on the lower surface of the substrate.