CN115332088A - Package based on interposer and manufacturing method - Google Patents

Package based on interposer and manufacturing method Download PDF

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Publication number
CN115332088A
CN115332088A CN202211258121.7A CN202211258121A CN115332088A CN 115332088 A CN115332088 A CN 115332088A CN 202211258121 A CN202211258121 A CN 202211258121A CN 115332088 A CN115332088 A CN 115332088A
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China
Prior art keywords
layer
chip
package
interposer
dielectric layer
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CN202211258121.7A
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Chinese (zh)
Inventor
华菲
赵作明
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Beijing Huafeng Jixin Electronics Co ltd
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Beijing Huafeng Jixin Electronics Co ltd
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Priority to CN202211258121.7A priority Critical patent/CN115332088A/en
Publication of CN115332088A publication Critical patent/CN115332088A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

The embodiment of the invention provides a packaging based on an interposer and a manufacturing method thereof, belonging to the field of semiconductor packaging. The manufacturing method comprises the following steps: s1: forming a carrier plate; s2: adding a stripping glue to one side of the carrier plate; s3: preparing a layer of redistributed wires on the lift-off glue comprising: forming a seed conducting layer and a dielectric layer in sequence on the stripping glue, wherein circuit patterns are arranged on the conducting layer and the dielectric layer; s4: filling electroplating materials into the gaps of the dielectric layer to form a conductive connecting layer; s5: repeating S3 and S4 for preparing a plurality of layers of redistributed conductor layers; s6: connecting at least one chip on the redistribution lead layer through a flip-chip process; s7: carrying out plastic molding and pressing and/or bottom filling on the chip through a plastic mold, and connecting the chip and the redistribution lead layer in a wrapping manner; s8: and removing the carrier plate and arranging welding spots to form the package with the medium layer. The preparation method has simple process and low preparation cost.

Description

Package based on interposer and manufacturing method
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a packaging based on an interposer and a manufacturing method.
Background
With the rapid development of the electronic industry, electronic devices are required to be more and more miniaturized, multi-functionalized, and have a large capacity in order to meet the needs of users, and thus, a semiconductor package having a plurality of semiconductor chips is required. The semiconductor package in the prior art has the problems of complex process, high manufacturing cost and the like.
Disclosure of Invention
Embodiments of the present invention provide an interposer-based package and a method for manufacturing the same, which has a simple process and a low manufacturing cost.
In order to achieve the above object, an embodiment of the present invention provides a method for manufacturing an interposer-based package, including: s1: forming a carrier plate; s2: adding a stripping glue to one side of the carrier plate; s3: preparing a layer of redistributed wires on the lift-off glue comprising: forming a seed conducting layer and a dielectric layer in sequence on the stripping glue, wherein circuit patterns are arranged on the conducting layer and the dielectric layer; s4: filling electroplating materials into the gaps of the dielectric layer to form a conductive connecting layer; s5: repeating S3 and S4 for preparing a plurality of layers of redistribution wires; s6: connecting at least one chip on the redistribution lead layer by a flip-chip process; s7: carrying out plastic molding and pressing and/or bottom filling on the chip through a plastic mold, and connecting the chip and the redistribution lead layer in a wrapping manner; s8: and removing the carrier plate and arranging welding spots to form the package with the intermediate layer.
Optionally, the carrier plate is made of silicon or glass; the electroplating material is copper.
Optionally, the seed conductive layer is a metal having adhesion or conductivity.
Optionally, the dielectric layer is made of an organic photosensitive material or a low dielectric coefficient material; the organic light-sensitive material is at least one of polyimide and cyclobutene resin; the low dielectric coefficient material includes at least one of silicon oxide and silicon oxynitride.
Optionally, the peeling glue is a temporary bonding glue, and the peeling mode is light peeling and/or heating peeling.
Optionally, the chip and the interposer are connected by a flip chip mounting method.
In another aspect, the present invention provides an interposer-based package, comprising at least: an interposer and at least one die; the interposer at least comprises a redistribution wire layer and metal through holes; the chip is arranged on one side of the redistribution lead layer, the chip is connected with the redistribution lead layer through a flip-chip process, and the plastic package pressing die and/or bottom filling is carried out on the chip through a plastic mould; the line width of the redistribution lead layer is less than 5 microns; the pins of the chip are led out through the interposer.
Optionally, the interposer is provided with metal vias and conductive lines for connecting the chips; the size of the perforations is less than 30 microns; the perforation mode is at least one of laser perforation and photoetching and etching opening; the perforated material is metal.
Optionally, the thickness of the interposer is in a range of 20-200 microns.
Optionally, the chip and the interposer are connected by flip chip bonding.
Optionally, the material of the mold is resin with a filler and/or a high molecular organic polymer.
Optionally, the redistribution layer includes a conductive layer and a dielectric layer; and circuit patterns are arranged on the conductive layer and the dielectric layer.
Optionally, the dielectric layer is made of an organic material and/or an inorganic material, the inorganic material is an inorganic material with a low dielectric coefficient, and the organic material is at least one of a molding material and a resin with a filler.
The manufacturing method of the package based on the interposer comprises the following steps: s1: forming a carrier plate; s2: adding a stripping glue to one side of the carrier plate; s3: preparing a layer of redistributed wires on the lift-off glue comprising: forming a seed conducting layer and a dielectric layer in sequence on the stripping glue, wherein circuit patterns are arranged on the conducting layer and the dielectric layer; s4: filling electroplating materials into the gaps of the dielectric layer to form a conductive connecting layer; s5: repeating S3 and S4 for preparing a plurality of layers of redistribution wires; s6: connecting at least one chip on the redistribution lead layer through a flip-chip process; s7: carrying out plastic package pressing mold or bottom filling on the chip through a plastic mold, and connecting the chip and the redistribution lead layer in a wrapping manner; s8: and removing the carrier plate and arranging welding spots to form the package with the medium layer. The manufacturing method can independently manufacture the intermediate layer, and any bad redistribution lead layer can not lose the chip, thereby greatly reducing the loss of the chip; and the chip is connected to the redistribution lead layer by using the patch, so that chips with different functions and different processes can be flexibly connected, the process limitation of a wafer factory can not be caused, and the flexible design of chip packaging is improved.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention and not to limit the embodiments of the invention. In the drawings:
fig. 1-2 are flow diagrams illustrating a method of fabricating an interposer based package in accordance with the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Fig. 1-2 are schematic flow charts illustrating a method for manufacturing an interposer-based package according to the present invention, and as shown in fig. 1 and 2, step S1 is to form a carrier board. The material of the carrier plate is silicon or glass.
And S2, adding a stripping glue to one side of the carrier plate. The stripping glue is a temporary bonding glue, and the stripping mode is light stripping and/or heating stripping. The invention preferably uses at least one of spin coating, spray coating and film pasting to coat a strippable glue on one surface of the carrier plate, and the bonding of the strippable glue can fail under high temperature or laser so as to be stripped.
Step S3 is to prepare a redistribution wire layer on the stripper rubber, and the method comprises the following steps: and sequentially forming a seed conductive layer and a dielectric layer on the stripping glue, wherein circuit patterns are arranged on the conductive layer and the dielectric layer. The dielectric layer is at least one of an organic dielectric layer or an inorganic material with a low dielectric coefficient. The Redistribution lead Layer is arranged on a Redistribution Layer (RDL Redistribution Layer), is used for realizing electrical connection among all parts of the package, and belongs to a metal material.
According to a specific embodiment, a seed conducting layer is physically deposited on the stripper glue, and a dielectric layer is coated or deposited, wherein the seed conducting layer is a metal with adhesiveness or conductivity. The dielectric layer is made of organic photosensitive material or low dielectric coefficient material; the organic photosensitive material is at least one of polyimide and cyclobutene resin, or other materials with good dielectric property and low dielectric coefficient; the low dielectric coefficient material includes at least one of silicon oxide and silicon oxynitride. The circuit pattern arranged on the dielectric layer is determined by circuit design, and the preparation process of the circuit pattern is preferably a photoetching process.
And S4, filling electroplating materials into gaps of the dielectric layer to form a conductive connecting layer. The plating material is preferably copper. The voids are voids in the circuit pattern. According to a preferred embodiment, the electrically conductive connection layer of the circuit is produced using said plating material, preferably copper. In the electroplating process, if the surface of the electroplating material has overlarge undulation, the undulation can be removed by carrying out chemical mechanical polishing on the electroplating material, so that the precision of the next step of photoetching is improved.
And step S5, repeating S3 and S4, and preparing a plurality of layers of redistributed lead layers. Specifically, the excess seed conducting layer is removed through an etching process, and the method is used for preparing a multilayer redistribution lead layer.
And step S6, connecting at least one chip on the redistribution lead layer through a flip-chip process. The chip and the intermediate layer are connected in a flip chip mounting mode, the existing flip chip mounting process is mature, and loss of good chips can be avoided. In fig. 2, two chips (Die 1 is chip 1, die2 is chip 2) are disposed on the redistribution layer, and a plurality of chips may be disposed thereon. By adopting the flip-chip technology, the manufacturing yield of the interposer is improved, the loss is reduced, and the manufacturing cost is reduced.
Step S7 is to perform molding and/or underfill on the chip through a molding die for wrapping the connection between the chip and the interposer. The material of the mould is resin or high molecular organic polymer with filler, and the filler is inorganic oxide, such as silicon oxide, aluminum oxide and the like.
And S8, removing the carrier plate and setting welding spots to form the package with the medium layer.
The manufacturing method can independently manufacture the intermediate layer, and any bad redistribution lead layer can not lose the chip, thereby greatly reducing the loss of the chip; and the chip is connected to the redistribution lead layer by using the patch, so that chips with different functions can be flexibly connected, the chips with different processes can not be limited by the process of a wafer factory, and the flexible design of chip packaging is improved and the cost is saved by using the rear-end preparation process of the wafer.
The manufacturing method of the intermediate layer utilizes the organic composite material to manufacture the intermediate layer, so that the design of the metal through hole is not limited by the punching technology; the organic composite material comprises more material types, so that the material which is relatively close to the thermal expansion coefficient of the chip is easy to find to reduce the stress of the chip; and the manufacturing method can also utilize the panel manufacturing process, thereby greatly reducing the manufacturing cost.
In another aspect, the present invention also provides an interposer based package, the package comprising at least: an interposer and at least one die; the interposer at least comprises a redistribution wire layer and a metal through hole; the chip is arranged on one side of the redistribution lead layer, the chip and the interposer are connected with a plastic mold or bottom filling, and specifically, the chip is connected with the redistribution lead layer through a flip-chip process, and the plastic mold pressing mold and/or the bottom filling is carried out on the chip through the plastic mold; the line width of the redistribution lead layer is less than 5 microns; the pins of the chip are led out through the interposer.
According to a specific embodiment, the interposer is provided with through holes, and the through holes are conductive metal and are used for connecting the chips; the size of the perforations is less than 30 microns; the perforation mode is at least one of laser perforation and photoetching and etching opening; the perforated material is metal. The interposer has a thickness in the range of 20-200 microns. The chip and the intermediate layer are connected in a flip chip mounting mode. The redistribution lead layer comprises a conductive layer and a dielectric layer; and circuit patterns are arranged on the conductive layer and the dielectric layer. The material of the mould is resin or high molecular organic polymer with filler, the filler is inorganic oxide such as silicon oxide, aluminum oxide and the like, the material of the dielectric layer is organic matter and/or inorganic matter, the inorganic matter is inorganic matter with low dielectric coefficient, and the type of the organic matter is at least one of the mould material and the resin with filler.
The manufacturing method of the package based on the interposer comprises the following steps: s1: forming a carrier plate; s2: adding a stripping glue to one side of the carrier plate; s3: preparing a layer of redistributed wires on the lift-off glue comprising: forming a seed conducting layer and a dielectric layer in sequence on the stripping glue, wherein circuit patterns are arranged on the conducting layer and the dielectric layer; s4: filling electroplating materials into the gaps of the dielectric layer to form a conductive connecting layer; s5: repeating S3 and S4 for preparing a plurality of layers of redistribution wires; s6: connecting at least one chip on the redistribution lead layer by a flip-chip process; s7: molding and/or underfilling the die through a mold to encapsulate the die and interposer connections; s8: and removing the carrier plate and arranging welding spots to form the package with the medium layer. The manufacturing method can independently manufacture the intermediate layer, and any bad redistribution lead layer can not lose the chip, thereby greatly reducing the loss of the chip; and the chip is connected to the redistribution lead layer by using the patch, so that chips with different functions and different processes can be flexibly connected, the process limitation of a wafer factory can not be caused, and the flexible design of chip packaging is improved.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (13)

1. A method of fabricating an interposer based package, the method comprising:
s1: forming a carrier plate;
s2: adding a stripping glue to one side of the carrier plate;
s3: preparing a layer of redistributed wires on the lift-off glue comprising: forming a seed conducting layer and a dielectric layer in sequence on the stripping glue, wherein circuit patterns are arranged on the conducting layer and the dielectric layer;
s4: filling electroplating materials into the gaps of the dielectric layer to form a conductive connecting layer;
s5: repeating S3 and S4 for preparing a plurality of layers of redistributed conductor layers;
s6: connecting at least one chip on the redistribution lead layer by a flip-chip process;
s7: carrying out plastic package compression molding and/or bottom filling on the chip through a plastic mold, and connecting the chip and the redistribution lead layer;
s8: and removing the carrier plate and arranging welding spots to form the package with the medium layer.
2. The method of claim 1,
the carrier plate is made of silicon or glass;
the electroplating material is copper.
3. The method of claim 1,
the seed conductive layer is a metal having adhesiveness or conductivity.
4. The method of claim 1,
the dielectric layer is made of organic photosensitive material or low dielectric coefficient material;
the organic light-sensitive material is at least one of polyimide and cyclobutene resin;
the low dielectric coefficient material includes at least one of silicon oxide and silicon oxynitride.
5. The method of claim 1,
the stripping glue is temporary bonding glue, and the stripping mode is light stripping and/or heating stripping.
6. The method of claim 1,
the chip and the intermediate layer are connected in a flip chip mounting mode.
7. An interposer-based package, comprising:
an interposer and at least one die;
the interposer at least comprises a redistribution wire layer and metal through holes;
the chip is arranged on one side of the redistribution lead layer, the chip is connected with the redistribution lead layer through a flip-chip process, and the chip is subjected to plastic package pressing and/or bottom filling through a plastic mould;
the line width of the redistribution lead layer is less than 5 microns;
and the pins of the chip are led out through the interposer.
8. The package of claim 7,
the interposer is provided with metal through holes and conducting wires for connecting the chips;
the size of the perforations is less than 30 microns;
the perforation mode is at least one of laser perforation and photoetching and etching opening;
the perforated material is metal.
9. The package of claim 7,
the interposer has a thickness in the range of 20-200 microns.
10. The package of claim 7,
the chip and the intermediate layer are connected in a flip chip mounting mode.
11. The package of claim 7,
the material of the mould is resin with a filler and/or a high molecular organic polymer; the filler is an inorganic oxide.
12. The package of claim 7,
the redistribution lead layer comprises a conductive layer and a dielectric layer;
and circuit patterns are arranged on the conductive layer and the dielectric layer.
13. The package of claim 12,
the dielectric layer is made of organic and/or inorganic substances, the inorganic substances are inorganic substances with low dielectric coefficients, and the organic substances are at least one of molding materials and resins with fillers.
CN202211258121.7A 2022-10-14 2022-10-14 Package based on interposer and manufacturing method Pending CN115332088A (en)

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Cited By (1)

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CN116092949A (en) * 2023-04-10 2023-05-09 北京华封集芯电子有限公司 Method for manufacturing interposer, interposer and chip package

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CN116092949B (en) * 2023-04-10 2023-06-09 北京华封集芯电子有限公司 Method for manufacturing interposer, interposer and chip package

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